fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53

Change internal function to call when updating value for WUPMSKCA57/53.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Sig

fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53

Change internal function to call when updating value for WUPMSKCA57/53.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id20e65e27861dd73a149ff487123859581a9b5c5

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fix(plat/rcar): change process that copy code to system ram

Change processing of invalidate instruction cache to after changing
the RAM attribute.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.

fix(plat/rcar): change process that copy code to system ram

Change processing of invalidate instruction cache to after changing
the RAM attribute.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM
Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9

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fix(plat/rcar): fix cache maintenance process of reading cert header

Move calling inv_dcache_range from before io_read to after that.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
S

fix(plat/rcar): fix cache maintenance process of reading cert header

Move calling inv_dcache_range from before io_read to after that.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ic0dabf3eb94eeeb04099ed5127cdfda79bbac9b3

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fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled

- Modify load destination variable of the Cert Header to static.
- Modify the return value to error (IO_FAIL) when failed t

fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled

- Modify load destination variable of the Cert Header to static.
- Modify the return value to error (IO_FAIL) when failed to check
the Cert Header.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ief09a841ec8d2ae236de82d04855e6a47cfb43f0

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feat(drivers/rcar3): add extra offset if booting B-side

In case MFISBTSTSR bit 4 is 1, that means the loader was started as
B-side. Load the remaining boot components from 8 MiB offset.

Signed-off-

feat(drivers/rcar3): add extra offset if booting B-side

In case MFISBTSTSR bit 4 is 1, that means the loader was started as
B-side. Load the remaining boot components from 8 MiB offset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10

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feat(plat/rcar3): modify SWDT counter setting for R-Car D3

Modified the SWDT counter setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Oga

feat(plat/rcar3): modify SWDT counter setting for R-Car D3

Modified the SWDT counter setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: If1fa12bf644486f3fad3c6b54cda6c4cbb604103

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feat(plat/rcar3): update DDR setting for R-Car D3

Update R-Car D3 DDR setting rev.0.02.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.o

feat(plat/rcar3): update DDR setting for R-Car D3

Update R-Car D3 DDR setting rev.0.02.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I3e3a202fbb0ff1f0f38a968ab5f8633604a46432

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feat(plat/rcar3): add process of SSCG setting for R-Car D3

- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by

feat(plat/rcar3): add process of SSCG setting for R-Car D3

- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by the
SSCG (MD12) setting value for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9

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feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR

Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.

Signed-off-by: Hidey

feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR

Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9a0820b6414425fa2f4197f60852137827414a4d

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feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up

Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.

Signed-off-by: Hideyuki Nitta <hideyuki.nitt

feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up

Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b

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fix(drivers/rcar3): console: fix a return value of console_rcar_init

This commit fixes a return value of console_rcar_init because it is
expected to return 1 on success but the function always retur

fix(drivers/rcar3): console: fix a return value of console_rcar_init

This commit fixes a return value of console_rcar_init because it is
expected to return 1 on success but the function always returns 0.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I97a6800578e3c517c0c1e3c00dc75f0ef75e8778

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feat(drivers/rcar3): ddr: add function to judge a DDR rank

This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.

Signed-off-by: To

feat(drivers/rcar3): ddr: add function to judge a DDR rank

This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I94d550cea620748f5b15499fed1b791a69d61592

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fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi H

fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168

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fix(drivers/rcar3): i2c_dvfs: fix I2C operation

This commit fixes value to write to the ICCR register according to
the hardware manual.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hi

fix(drivers/rcar3): i2c_dvfs: fix I2C operation

This commit fixes value to write to the ICCR register according to
the hardware manual.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I1f612a482c012a6739e2f31db80224b222df766c

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fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by

fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de

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fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition

emmc_registers.h contains redefinition of
CPG_CPGWPR from bl2_cpg_register.h

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hita

fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition

emmc_registers.h contains redefinition of
CPG_CPGWPR from bl2_cpg_register.h

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ie13590100df08f32193653e50191e66ed42d2b28

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drivers: renesas: common: watchdog: Add support for RZ/G2E

Add watchdog support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.da

drivers: renesas: common: watchdog: Add support for RZ/G2E

Add watchdog support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551

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drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC

DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.

Signed-off-by: Lad Prabhakar <prabhakar.ma

drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC

DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df

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drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC

Select MMC_CH1 for eMMC on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Da

drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC

Select MMC_CH1 for eMMC on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee

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drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC

Add support for initializing DRAM on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R

drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC

Add support for initializing DRAM on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0

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drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC

Select MMC_CH1 for eMMC on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Da

drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC

Select MMC_CH1 for eMMC on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d

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drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC

Add support for initializing DRAM on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R

drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC

Add support for initializing DRAM on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9

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drivers: renesas: rzg: Switch using common ddr code

Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.r

drivers: renesas: rzg: Switch using common ddr code

Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f

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drivers: renesas: ddr: Move to common

Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Lad Prabhakar <prabhakar.

drivers: renesas: ddr: Move to common

Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727

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renesas: rzg: emmc: Enable RZ/G2M support

Enable eMMC driver support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.ren

renesas: rzg: emmc: Enable RZ/G2M support

Enable eMMC driver support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I34803060c5b592ac24720b11d4a8cd3f9f40caee

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