1 /* 2 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <arch_helpers.h> 10 #include <bl1/bl1.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/console.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_storage.h> 17 #include <libfdt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_defs.h> 20 #include <platform_def.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "board.h" 25 #include "boot_init_dram.h" 26 #include "cpg_registers.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 #include "io_common.h" 31 #include "io_rcar.h" 32 #include "qos_init.h" 33 #include "rcar_def.h" 34 #include "rcar_private.h" 35 #include "rcar_version.h" 36 #include "rom_api.h" 37 38 #define MAX_DRAM_CHANNELS 4 39 /* 40 * DDR ch0 has a shadow area mapped in 32bit address space. 41 * Physical address 0x4_0000_0000 - 0x4_7fff_ffff in 64bit space 42 * is mapped to 0x4000_0000 - 0xbfff_ffff in 32bit space. 43 */ 44 #define MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE 0x80000000ULL 45 46 #if RCAR_BL2_DCACHE == 1 47 /* 48 * Following symbols are only used during plat_arch_setup() only 49 * when RCAR_BL2_DCACHE is enabled. 50 */ 51 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 52 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 53 54 #if USE_COHERENT_MEM 55 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 56 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 57 #endif /* USE_COHERENT_MEM */ 58 59 #endif /* RCAR_BL2_DCACHE */ 60 61 extern void plat_rcar_gic_driver_init(void); 62 extern void plat_rcar_gic_init(void); 63 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 64 extern void bl2_system_cpg_init(void); 65 extern void bl2_secure_setting(void); 66 extern void bl2_cpg_init(void); 67 extern void rcar_io_emmc_setup(void); 68 extern void rcar_io_setup(void); 69 extern void rcar_swdt_release(void); 70 extern void rcar_swdt_init(void); 71 extern void rcar_rpc_init(void); 72 extern void rcar_dma_init(void); 73 extern void rzg_pfc_init(void); 74 75 static void bl2_init_generic_timer(void); 76 77 /* RZ/G2 product check */ 78 #if RCAR_LSI == RZ_G2M 79 #define TARGET_PRODUCT PRR_PRODUCT_M3 80 #define TARGET_NAME "RZ/G2M" 81 #elif RCAR_LSI == RZ_G2H 82 #define TARGET_PRODUCT PRR_PRODUCT_H3 83 #define TARGET_NAME "RZ/G2H" 84 #elif RCAR_LSI == RCAR_AUTO 85 #define TARGET_NAME "RZ/G2M" 86 #endif /* RCAR_LSI == RZ_G2M */ 87 88 #define GPIO_INDT (GPIO_INDT1) 89 #define GPIO_BKUP_TRG_SHIFT (1U << 8U) 90 91 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 92 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 93 assert_bl31_params_do_not_fit_in_shared_memory); 94 95 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 96 97 /* FDT with DRAM configuration */ 98 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 99 static void *fdt = (void *)fdt_blob; 100 101 static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string) 102 { 103 /* Just need enough space to store 64 bit decimal integer */ 104 char num_buf[20]; 105 int i = 0; 106 unsigned int rem; 107 108 do { 109 rem = unum % radix; 110 if (rem < 0xaU) { 111 num_buf[i] = '0' + rem; 112 } else { 113 num_buf[i] = 'a' + (rem - 0xaU); 114 } 115 i++; 116 unum /= radix; 117 } while (unum > 0U); 118 119 while (--i >= 0) { 120 *string++ = num_buf[i]; 121 } 122 *string = 0; 123 } 124 125 #if RCAR_LOSSY_ENABLE == 1 126 typedef struct bl2_lossy_info { 127 uint32_t magic; 128 uint32_t a0; 129 uint32_t b0; 130 } bl2_lossy_info_t; 131 132 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 133 uint64_t end_addr, uint32_t format, 134 uint32_t enable, int fcnlnode) 135 { 136 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 137 char nodename[40] = { 0 }; 138 int ret, node; 139 140 /* Ignore undefined addresses */ 141 if (start_addr == 0UL && end_addr == 0UL) { 142 return; 143 } 144 145 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 146 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 147 148 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 149 if (ret < 0) { 150 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 151 panic(); 152 } 153 154 ret = fdt_setprop_string(fdt, node, "compatible", 155 "renesas,lossy-decompression"); 156 if (ret < 0) { 157 NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n", 158 "renesas,lossy-decompression", ret); 159 panic(); 160 } 161 162 ret = fdt_appendprop_string(fdt, node, "compatible", 163 "shared-dma-pool"); 164 if (ret < 0) { 165 NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n", 166 "shared-dma-pool", ret); 167 panic(); 168 } 169 170 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 171 if (ret < 0) { 172 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 173 panic(); 174 } 175 176 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 177 if (ret < 0) { 178 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 179 panic(); 180 } 181 182 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 183 if (ret < 0) { 184 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 185 panic(); 186 } 187 188 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 189 if (ret < 0) { 190 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 191 panic(); 192 } 193 } 194 195 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 196 uint64_t end_addr, uint32_t format, 197 uint32_t enable, int fcnlnode) 198 { 199 bl2_lossy_info_t info; 200 uint32_t reg; 201 202 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 203 204 reg = format | (start_addr >> 20); 205 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); 206 mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20); 207 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); 208 209 info.magic = 0x12345678U; 210 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no); 211 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no); 212 213 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 214 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0); 215 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0); 216 217 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 218 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no), 219 mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no)); 220 } 221 #endif /* RCAR_LOSSY_ENABLE == 1 */ 222 223 void bl2_plat_flush_bl31_params(void) 224 { 225 uint32_t product_cut, product, cut; 226 uint32_t boot_dev, boot_cpu; 227 uint32_t reg; 228 229 reg = mmio_read_32(RCAR_MODEMR); 230 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 231 232 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 233 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 234 emmc_terminate(); 235 } 236 237 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) { 238 bl2_secure_setting(); 239 } 240 241 reg = mmio_read_32(RCAR_PRR); 242 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 243 product = reg & PRR_PRODUCT_MASK; 244 cut = reg & PRR_CUT_MASK; 245 246 if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) || 247 (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) { 248 /* Disable MFIS write protection */ 249 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U); 250 } 251 252 reg = mmio_read_32(RCAR_MODEMR); 253 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 254 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 255 boot_cpu == MODEMR_BOOT_CPU_CA53) { 256 if (product_cut == PRR_PRODUCT_H3_CUT20) { 257 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 258 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 259 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 260 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 261 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 262 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 263 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 264 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 265 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 266 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 267 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 268 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 269 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 270 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 271 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 272 } 273 274 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 275 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 276 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 277 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 278 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 280 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 281 282 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 283 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 284 } 285 } 286 287 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 288 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 289 290 rcar_swdt_release(); 291 bl2_system_cpg_init(); 292 293 #if RCAR_BL2_DCACHE == 1 294 /* Disable data cache (clean and invalidate) */ 295 disable_mmu_el3(); 296 #endif /* RCAR_BL2_DCACHE == 1 */ 297 } 298 299 static uint32_t is_ddr_backup_mode(void) 300 { 301 #if RCAR_SYSTEM_SUSPEND 302 static uint32_t reason = RCAR_COLD_BOOT; 303 static uint32_t once; 304 305 if (once != 0U) { 306 return reason; 307 } 308 309 once = 1; 310 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) { 311 return reason; 312 } 313 314 reason = RCAR_WARM_BOOT; 315 return reason; 316 #else /* RCAR_SYSTEM_SUSPEND */ 317 return RCAR_COLD_BOOT; 318 #endif /* RCAR_SYSTEM_SUSPEND */ 319 } 320 321 int bl2_plat_handle_pre_image_load(unsigned int image_id) 322 { 323 u_register_t *boot_kind = (void *)BOOT_KIND_BASE; 324 bl_mem_params_node_t *bl_mem_params; 325 326 if (image_id != BL31_IMAGE_ID) { 327 return 0; 328 } 329 330 bl_mem_params = get_bl_mem_params_node(image_id); 331 332 if (is_ddr_backup_mode() != RCAR_COLD_BOOT) { 333 *boot_kind = RCAR_WARM_BOOT; 334 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 335 336 console_flush(); 337 bl2_plat_flush_bl31_params(); 338 339 /* will not return */ 340 bl2_enter_bl31(&bl_mem_params->ep_info); 341 } 342 343 *boot_kind = RCAR_COLD_BOOT; 344 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 345 346 return 0; 347 } 348 349 static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 350 { 351 uint32_t cert, len; 352 int err; 353 354 err = rcar_get_certificate(certid, &cert); 355 if (err != 0) { 356 ERROR("%s : cert file load error", __func__); 357 return 1U; 358 } 359 360 rcar_read_certificate((uint64_t)cert, &len, dest); 361 362 return 0U; 363 } 364 365 int bl2_plat_handle_post_image_load(unsigned int image_id) 366 { 367 static bl2_to_bl31_params_mem_t *params; 368 bl_mem_params_node_t *bl_mem_params; 369 uintptr_t dest; 370 uint64_t ret; 371 372 if (params == NULL) { 373 params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 374 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 375 } 376 377 bl_mem_params = get_bl_mem_params_node(image_id); 378 379 switch (image_id) { 380 case BL31_IMAGE_ID: 381 ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 382 &dest); 383 if (ret == 0U) { 384 bl_mem_params->image_info.image_base = dest; 385 } 386 break; 387 case BL32_IMAGE_ID: 388 ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 389 &dest); 390 if (ret == 0U) { 391 bl_mem_params->image_info.image_base = dest; 392 } 393 394 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 395 sizeof(entry_point_info_t)); 396 break; 397 case BL33_IMAGE_ID: 398 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 399 sizeof(entry_point_info_t)); 400 break; 401 default: 402 break; 403 } 404 405 return 0; 406 } 407 408 struct meminfo *bl2_plat_sec_mem_layout(void) 409 { 410 return &bl2_tzram_layout; 411 } 412 413 static void bl2_populate_compatible_string(void *dt) 414 { 415 uint32_t board_type; 416 uint32_t board_rev; 417 uint32_t reg; 418 int ret; 419 420 fdt_setprop_u32(dt, 0, "#address-cells", 2); 421 fdt_setprop_u32(dt, 0, "#size-cells", 2); 422 423 /* Populate compatible string */ 424 rzg_get_board_type(&board_type, &board_rev); 425 switch (board_type) { 426 case BOARD_HIHOPE_RZ_G2M: 427 ret = fdt_setprop_string(dt, 0, "compatible", 428 "hoperun,hihope-rzg2m"); 429 break; 430 case BOARD_HIHOPE_RZ_G2H: 431 ret = fdt_setprop_string(dt, 0, "compatible", 432 "hoperun,hihope-rzg2h"); 433 break; 434 default: 435 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 436 panic(); 437 break; 438 } 439 440 if (ret < 0) { 441 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 442 panic(); 443 } 444 445 reg = mmio_read_32(RCAR_PRR); 446 switch (reg & PRR_PRODUCT_MASK) { 447 case PRR_PRODUCT_M3: 448 ret = fdt_appendprop_string(dt, 0, "compatible", 449 "renesas,r8a774a1"); 450 break; 451 case PRR_PRODUCT_H3: 452 ret = fdt_appendprop_string(dt, 0, "compatible", 453 "renesas,r8a774e1"); 454 break; 455 default: 456 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 457 panic(); 458 break; 459 } 460 461 if (ret < 0) { 462 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 463 panic(); 464 } 465 } 466 467 static int bl2_add_memory_node(uint64_t start, uint64_t size) 468 { 469 char nodename[32] = { 0 }; 470 uint64_t fdtsize; 471 int ret, node; 472 473 fdtsize = cpu_to_fdt64(size); 474 475 snprintf(nodename, sizeof(nodename), "memory@"); 476 unsigned_num_print(start, 16, nodename + strlen(nodename)); 477 node = ret = fdt_add_subnode(fdt, 0, nodename); 478 if (ret < 0) { 479 return ret; 480 } 481 482 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 483 if (ret < 0) { 484 return ret; 485 } 486 487 ret = fdt_setprop_u64(fdt, node, "reg", start); 488 if (ret < 0) { 489 return ret; 490 } 491 492 return fdt_appendprop(fdt, node, "reg", &fdtsize, sizeof(fdtsize)); 493 } 494 495 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 496 { 497 uint64_t start, size; 498 int ret, chan; 499 500 for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) { 501 start = dram_config[2 * chan]; 502 size = dram_config[2 * chan + 1]; 503 if (size == 0U) { 504 continue; 505 } 506 507 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 508 chan, start, start + size - 1U, 509 (size >> 30) ? : size >> 20, 510 (size >> 30) ? "G" : "M"); 511 } 512 513 /* 514 * We add the DT nodes in reverse order here. The fdt_add_subnode() 515 * adds the DT node before the first existing DT node, so we have 516 * to add them in reverse order to get nodes sorted by address in 517 * the resulting DT. 518 */ 519 for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) { 520 start = dram_config[2 * chan]; 521 size = dram_config[2 * chan + 1]; 522 if (size == 0U) { 523 continue; 524 } 525 526 /* 527 * Channel 0 is mapped in 32bit space and the first 528 * 128 MiB are reserved 529 */ 530 if (chan == 0) { 531 /* 532 * Maximum DDR size in Channel 0 for 32 bit space is 2GB, Add DT node 533 * for remaining region in 64 bit address space 534 */ 535 if (size > MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE) { 536 start = dram_config[chan] + MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 537 size -= MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 538 ret = bl2_add_memory_node(start, size); 539 if (ret < 0) { 540 goto err; 541 } 542 } 543 start = 0x48000000U; 544 size -= 0x8000000U; 545 } 546 547 ret = bl2_add_memory_node(start, size); 548 if (ret < 0) { 549 goto err; 550 } 551 } 552 553 return; 554 err: 555 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 556 panic(); 557 } 558 559 static void bl2_advertise_dram_size(uint32_t product) 560 { 561 uint64_t dram_config[8] = { 562 [0] = 0x400000000ULL, 563 [2] = 0x500000000ULL, 564 [4] = 0x600000000ULL, 565 [6] = 0x700000000ULL, 566 }; 567 568 switch (product) { 569 case PRR_PRODUCT_M3: 570 /* 4GB(2GBx2 2ch split) */ 571 dram_config[1] = 0x80000000ULL; 572 dram_config[5] = 0x80000000ULL; 573 break; 574 case PRR_PRODUCT_H3: 575 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 576 /* 4GB(1GBx4) */ 577 dram_config[1] = 0x40000000ULL; 578 dram_config[3] = 0x40000000ULL; 579 dram_config[5] = 0x40000000ULL; 580 dram_config[7] = 0x40000000ULL; 581 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \ 582 (RCAR_DRAM_SPLIT == 2) 583 /* 4GB(2GBx2 2ch split) */ 584 dram_config[1] = 0x80000000ULL; 585 dram_config[3] = 0x80000000ULL; 586 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 587 /* 8GB(2GBx4: default) */ 588 dram_config[1] = 0x80000000ULL; 589 dram_config[3] = 0x80000000ULL; 590 dram_config[5] = 0x80000000ULL; 591 dram_config[7] = 0x80000000ULL; 592 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 593 break; 594 default: 595 NOTICE("BL2: Detected invalid DRAM entries\n"); 596 break; 597 } 598 599 bl2_advertise_dram_entries(dram_config); 600 } 601 602 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 603 u_register_t arg3, u_register_t arg4) 604 { 605 uint32_t reg, midr, boot_dev, boot_cpu, type, rev; 606 uint32_t product, product_cut, major, minor; 607 int32_t ret; 608 const char *str; 609 const char *unknown = "unknown"; 610 const char *cpu_ca57 = "CA57"; 611 const char *cpu_ca53 = "CA53"; 612 const char *product_g2h = "G2H"; 613 const char *product_g2m = "G2M"; 614 const char *boot_hyper80 = "HyperFlash(80MHz)"; 615 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 616 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 617 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 618 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 619 const char *boot_hyper160 = "HyperFlash(160MHz)"; 620 #if RZG_LCS_STATE_DETECTION_ENABLE 621 uint32_t lcs; 622 const char *lcs_secure = "SE"; 623 const char *lcs_cm = "CM"; 624 const char *lcs_dm = "DM"; 625 const char *lcs_sd = "SD"; 626 const char *lcs_fa = "FA"; 627 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 628 629 #if (RCAR_LOSSY_ENABLE == 1) 630 int fcnlnode; 631 #endif /* (RCAR_LOSSY_ENABLE == 1) */ 632 633 bl2_init_generic_timer(); 634 635 reg = mmio_read_32(RCAR_MODEMR); 636 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 637 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 638 639 bl2_cpg_init(); 640 641 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 642 boot_cpu == MODEMR_BOOT_CPU_CA53) { 643 rzg_pfc_init(); 644 rcar_console_boot_init(); 645 } 646 647 plat_rcar_gic_driver_init(); 648 plat_rcar_gic_init(); 649 rcar_swdt_init(); 650 651 /* FIQ interrupts are taken to EL3 */ 652 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 653 654 write_daifclr(DAIF_FIQ_BIT); 655 656 reg = read_midr(); 657 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 658 switch (midr) { 659 case MIDR_CA57: 660 str = cpu_ca57; 661 break; 662 case MIDR_CA53: 663 str = cpu_ca53; 664 break; 665 default: 666 str = unknown; 667 break; 668 } 669 670 NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str, 671 version_of_renesas); 672 673 reg = mmio_read_32(RCAR_PRR); 674 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 675 product = reg & PRR_PRODUCT_MASK; 676 677 switch (product) { 678 case PRR_PRODUCT_M3: 679 str = product_g2m; 680 break; 681 case PRR_PRODUCT_H3: 682 str = product_g2h; 683 break; 684 default: 685 str = unknown; 686 break; 687 } 688 689 if ((product == PRR_PRODUCT_M3) && 690 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) { 691 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) { 692 /* M3 Ver.1.1 or Ver.1.2 */ 693 NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str); 694 } else { 695 NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str, 696 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 697 } 698 } else { 699 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 700 major = major + RCAR_MAJOR_OFFSET; 701 minor = reg & RCAR_MINOR_MASK; 702 NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor); 703 } 704 705 rzg_get_board_type(&type, &rev); 706 707 switch (type) { 708 case BOARD_HIHOPE_RZ_G2M: 709 case BOARD_HIHOPE_RZ_G2H: 710 break; 711 default: 712 type = BOARD_UNKNOWN; 713 break; 714 } 715 716 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) { 717 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 718 } else { 719 NOTICE("BL2: Board is %s Rev.%d.%d\n", 720 GET_BOARD_NAME(type), 721 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 722 } 723 724 #if RCAR_LSI != RCAR_AUTO 725 if (product != TARGET_PRODUCT) { 726 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 727 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 728 panic(); 729 } 730 #endif /* RCAR_LSI != RCAR_AUTO */ 731 rcar_avs_init(); 732 rcar_avs_setting(); 733 734 switch (boot_dev) { 735 case MODEMR_BOOT_DEV_HYPERFLASH160: 736 str = boot_hyper160; 737 break; 738 case MODEMR_BOOT_DEV_HYPERFLASH80: 739 str = boot_hyper80; 740 break; 741 case MODEMR_BOOT_DEV_QSPI_FLASH40: 742 str = boot_qspi40; 743 break; 744 case MODEMR_BOOT_DEV_QSPI_FLASH80: 745 str = boot_qspi80; 746 break; 747 case MODEMR_BOOT_DEV_EMMC_25X1: 748 str = boot_emmc25x1; 749 break; 750 case MODEMR_BOOT_DEV_EMMC_50X8: 751 str = boot_emmc50x8; 752 break; 753 default: 754 str = unknown; 755 break; 756 } 757 NOTICE("BL2: Boot device is %s\n", str); 758 759 rcar_avs_setting(); 760 761 #if RZG_LCS_STATE_DETECTION_ENABLE 762 reg = rcar_rom_get_lcs(&lcs); 763 if (reg != 0U) { 764 str = unknown; 765 goto lcm_state; 766 } 767 768 switch (lcs) { 769 case LCS_CM: 770 str = lcs_cm; 771 break; 772 case LCS_DM: 773 str = lcs_dm; 774 break; 775 case LCS_SD: 776 str = lcs_sd; 777 break; 778 case LCS_SE: 779 str = lcs_secure; 780 break; 781 case LCS_FA: 782 str = lcs_fa; 783 break; 784 default: 785 str = unknown; 786 break; 787 } 788 789 lcm_state: 790 NOTICE("BL2: LCM state is %s\n", str); 791 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 792 793 rcar_avs_end(); 794 is_ddr_backup_mode(); 795 796 bl2_tzram_layout.total_base = BL31_BASE; 797 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 798 799 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 800 boot_cpu == MODEMR_BOOT_CPU_CA53) { 801 ret = rcar_dram_init(); 802 if (ret != 0) { 803 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 804 panic(); 805 } 806 rzg_qos_init(); 807 } 808 809 /* Set up FDT */ 810 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 811 if (ret != 0) { 812 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 813 panic(); 814 } 815 816 /* Add platform compatible string */ 817 bl2_populate_compatible_string(fdt); 818 819 /* Print DRAM layout */ 820 bl2_advertise_dram_size(product); 821 822 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 823 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 824 if (rcar_emmc_init() != EMMC_SUCCESS) { 825 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 826 panic(); 827 } 828 rcar_emmc_memcard_power(EMMC_POWER_ON); 829 if (rcar_emmc_mount() != EMMC_SUCCESS) { 830 NOTICE("BL2: Failed to eMMC mount operation.\n"); 831 panic(); 832 } 833 } else { 834 rcar_rpc_init(); 835 rcar_dma_init(); 836 } 837 838 reg = mmio_read_32(RST_WDTRSTCR); 839 reg &= ~WDTRSTCR_RWDT_RSTMSK; 840 reg |= WDTRSTCR_PASSWORD; 841 mmio_write_32(RST_WDTRSTCR, reg); 842 843 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 844 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 845 846 reg = mmio_read_32(RCAR_PRR); 847 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) { 848 mmio_write_32(CPG_CA57DBGRCR, 849 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 850 } 851 852 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) { 853 mmio_write_32(CPG_CA53DBGRCR, 854 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 855 } 856 857 if (product_cut == PRR_PRODUCT_H3_CUT10) { 858 reg = mmio_read_32(CPG_PLL2CR); 859 reg &= ~((uint32_t)1 << 5); 860 mmio_write_32(CPG_PLL2CR, reg); 861 862 reg = mmio_read_32(CPG_PLL4CR); 863 reg &= ~((uint32_t)1 << 5); 864 mmio_write_32(CPG_PLL4CR, reg); 865 866 reg = mmio_read_32(CPG_PLL0CR); 867 reg &= ~((uint32_t)1 << 12); 868 mmio_write_32(CPG_PLL0CR, reg); 869 } 870 #if (RCAR_LOSSY_ENABLE == 1) 871 NOTICE("BL2: Lossy Decomp areas\n"); 872 873 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 874 if (fcnlnode < 0) { 875 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 876 fcnlnode); 877 panic(); 878 } 879 880 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 881 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 882 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 883 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 884 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 885 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 886 #endif /* RCAR_LOSSY_ENABLE */ 887 888 fdt_pack(fdt); 889 NOTICE("BL2: FDT at %p\n", fdt); 890 891 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 892 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 893 rcar_io_emmc_setup(); 894 } else { 895 rcar_io_setup(); 896 } 897 } 898 899 void bl2_el3_plat_arch_setup(void) 900 { 901 #if RCAR_BL2_DCACHE == 1 902 NOTICE("BL2: D-Cache enable\n"); 903 rcar_configure_mmu_el3(BL2_BASE, 904 BL2_END - BL2_BASE, 905 BL2_RO_BASE, BL2_RO_LIMIT 906 #if USE_COHERENT_MEM 907 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 908 #endif /* USE_COHERENT_MEM */ 909 ); 910 #endif /* RCAR_BL2_DCACHE == 1 */ 911 } 912 913 void bl2_platform_setup(void) 914 { 915 /* 916 * Place holder for performing any platform initialization specific 917 * to BL2. 918 */ 919 } 920 921 static void bl2_init_generic_timer(void) 922 { 923 uint32_t reg_cntfid; 924 uint32_t modemr; 925 uint32_t modemr_pll; 926 uint32_t pll_table[] = { 927 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 928 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 929 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 930 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 931 }; 932 933 modemr = mmio_read_32(RCAR_MODEMR); 934 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 935 936 /* Set frequency data in CNTFID0 */ 937 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 938 939 /* Update memory mapped and register based frequency */ 940 write_cntfrq_el0((u_register_t)reg_cntfid); 941 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 942 /* Enable counter */ 943 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 944 (uint32_t)CNTCR_EN); 945 } 946