1 /* 2 * Copyright (c) 2015-2020, Renesas Electronics Corporation. 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <stdint.h> 9 #include <string.h> 10 #include <stdio.h> 11 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 15 #include "ddr_regdef.h" 16 #include "init_dram_tbl_h3.h" 17 #include "init_dram_tbl_m3.h" 18 #include "init_dram_tbl_h3ver2.h" 19 #include "init_dram_tbl_m3n.h" 20 #include "boot_init_dram_regdef.h" 21 #include "boot_init_dram.h" 22 #include "dram_sub_func.h" 23 #include "micro_delay.h" 24 #include "rcar_def.h" 25 26 #define DDR_BACKUPMODE 27 #define FATAL_MSG(x) NOTICE(x) 28 29 /* variables */ 30 #ifdef RCAR_DDR_FIXED_LSI_TYPE 31 #ifndef RCAR_AUTO 32 #define RCAR_AUTO 99 33 #define RCAR_H3 0 34 #define RCAR_M3 1 35 #define RCAR_M3N 2 36 #define RCAR_E3 3 /* NON */ 37 #define RCAR_H3N 4 38 39 #define RCAR_CUT_10 0 40 #define RCAR_CUT_11 1 41 #define RCAR_CUT_20 10 42 #define RCAR_CUT_30 20 43 #endif 44 #ifndef RCAR_LSI 45 #define RCAR_LSI RCAR_AUTO 46 #endif 47 48 #if (RCAR_LSI == RCAR_AUTO) 49 static uint32_t prr_product; 50 static uint32_t prr_cut; 51 #else 52 #if (RCAR_LSI == RCAR_H3) 53 static const uint32_t prr_product = PRR_PRODUCT_H3; 54 #elif(RCAR_LSI == RCAR_M3) 55 static const uint32_t prr_product = PRR_PRODUCT_M3; 56 #elif(RCAR_LSI == RCAR_M3N) 57 static const uint32_t prr_product = PRR_PRODUCT_M3N; 58 #elif(RCAR_LSI == RCAR_H3N) 59 static const uint32_t prr_product = PRR_PRODUCT_H3; 60 #endif /* RCAR_LSI */ 61 62 #ifndef RCAR_LSI_CUT 63 static uint32_t prr_cut; 64 #else /* RCAR_LSI_CUT */ 65 #if (RCAR_LSI_CUT == RCAR_CUT_10) 66 static const uint32_t prr_cut = PRR_PRODUCT_10; 67 #elif(RCAR_LSI_CUT == RCAR_CUT_11) 68 static const uint32_t prr_cut = PRR_PRODUCT_11; 69 #elif(RCAR_LSI_CUT == RCAR_CUT_20) 70 static const uint32_t prr_cut = PRR_PRODUCT_20; 71 #elif(RCAR_LSI_CUT == RCAR_CUT_30) 72 static const uint32_t prr_cut = PRR_PRODUCT_30; 73 #endif /* RCAR_LSI_CUT */ 74 #endif /* RCAR_LSI_CUT */ 75 #endif /* RCAR_AUTO_NON */ 76 #else /* RCAR_DDR_FIXED_LSI_TYPE */ 77 static uint32_t prr_product; 78 static uint32_t prr_cut; 79 #endif /* RCAR_DDR_FIXED_LSI_TYPE */ 80 81 static const uint32_t *p_ddr_regdef_tbl; 82 static uint32_t brd_clk; 83 static uint32_t brd_clkdiv; 84 static uint32_t brd_clkdiva; 85 static uint32_t ddr_mbps; 86 static uint32_t ddr_mbpsdiv; 87 static uint32_t ddr_tccd; 88 static uint32_t ddr_phycaslice; 89 static const struct _boardcnf *board_cnf; 90 static uint32_t ddr_phyvalid; 91 static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; 92 static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); 93 static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9]; 94 static uint32_t max_density; 95 static uint32_t ddr0800_mul; 96 static uint32_t ddr_mul; 97 static uint32_t DDR_PHY_SLICE_REGSET_OFS; 98 static uint32_t DDR_PHY_ADR_V_REGSET_OFS; 99 static uint32_t DDR_PHY_ADR_I_REGSET_OFS; 100 static uint32_t DDR_PHY_ADR_G_REGSET_OFS; 101 static uint32_t DDR_PI_REGSET_OFS; 102 static uint32_t DDR_PHY_SLICE_REGSET_SIZE; 103 static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; 104 static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; 105 static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; 106 static uint32_t DDR_PI_REGSET_SIZE; 107 static uint32_t DDR_PHY_SLICE_REGSET_NUM; 108 static uint32_t DDR_PHY_ADR_V_REGSET_NUM; 109 static uint32_t DDR_PHY_ADR_I_REGSET_NUM; 110 static uint32_t DDR_PHY_ADR_G_REGSET_NUM; 111 static uint32_t DDR_PI_REGSET_NUM; 112 static uint32_t DDR_PHY_ADR_I_NUM; 113 #define DDR_PHY_REGSET_MAX 128 114 #define DDR_PI_REGSET_MAX 320 115 static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; 116 static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; 117 static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; 118 static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; 119 static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; 120 static uint32_t pll3_mode; 121 static uint32_t loop_max; 122 #ifdef DDR_BACKUPMODE 123 uint32_t ddr_backup; 124 /* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ 125 #endif 126 127 #ifdef ddr_qos_init_setting /* only for non qos_init */ 128 #define OPERATING_FREQ (400U) /* Mhz */ 129 #define BASE_SUB_SLOT_NUM (0x6U) 130 #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ 131 #define QOSWT_WTSET0_CYCLE \ 132 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \ 133 OPERATING_FREQ) /* unit:ns */ 134 135 uint32_t get_refperiod(void) 136 { 137 return QOSWT_WTSET0_CYCLE; 138 } 139 #else /* ddr_qos_init_setting // only for non qos_init */ 140 extern uint32_t get_refperiod(void); 141 #endif /* ddr_qos_init_setting // only for non qos_init */ 142 143 #define _reg_PHY_RX_CAL_X_NUM 11 144 static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { 145 _reg_PHY_RX_CAL_DQ0, 146 _reg_PHY_RX_CAL_DQ1, 147 _reg_PHY_RX_CAL_DQ2, 148 _reg_PHY_RX_CAL_DQ3, 149 _reg_PHY_RX_CAL_DQ4, 150 _reg_PHY_RX_CAL_DQ5, 151 _reg_PHY_RX_CAL_DQ6, 152 _reg_PHY_RX_CAL_DQ7, 153 _reg_PHY_RX_CAL_DM, 154 _reg_PHY_RX_CAL_DQS, 155 _reg_PHY_RX_CAL_FDBK 156 }; 157 158 #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 159 static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY 160 [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { 161 _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, 162 _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, 163 _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, 164 _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, 165 _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, 166 _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, 167 _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, 168 _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, 169 _reg_PHY_CLK_WRDM_SLAVE_DELAY, 170 _reg_PHY_CLK_WRDQS_SLAVE_DELAY 171 }; 172 173 #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 174 static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY 175 [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { 176 _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, 177 _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, 178 _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, 179 _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, 180 _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, 181 _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, 182 _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, 183 _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, 184 _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 185 }; 186 187 #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 188 static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 189 [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { 190 _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, 191 _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, 192 _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, 193 _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, 194 _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, 195 _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, 196 _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, 197 _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, 198 _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 199 }; 200 201 #define _reg_PHY_PAD_TERM_X_NUM 8 202 static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { 203 _reg_PHY_PAD_FDBK_TERM, 204 _reg_PHY_PAD_DATA_TERM, 205 _reg_PHY_PAD_DQS_TERM, 206 _reg_PHY_PAD_ADDR_TERM, 207 _reg_PHY_PAD_CLK_TERM, 208 _reg_PHY_PAD_CKE_TERM, 209 _reg_PHY_PAD_RST_TERM, 210 _reg_PHY_PAD_CS_TERM 211 }; 212 213 #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 214 static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X 215 [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { 216 _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, 217 _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, 218 _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, 219 _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, 220 _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, 221 _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, 222 223 _reg_PHY_GRP_SLAVE_DELAY_0, 224 _reg_PHY_GRP_SLAVE_DELAY_1, 225 _reg_PHY_GRP_SLAVE_DELAY_2, 226 _reg_PHY_GRP_SLAVE_DELAY_3 227 }; 228 229 /* Prototypes */ 230 static inline uint32_t vch_nxt(uint32_t pos); 231 static void cpg_write_32(uint32_t a, uint32_t v); 232 static void pll3_control(uint32_t high); 233 static inline void dsb_sev(void); 234 static void wait_dbcmd(void); 235 static void send_dbcmd(uint32_t cmd); 236 static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); 237 static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); 238 static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); 239 static inline uint32_t ddr_regdef(uint32_t _regdef); 240 static inline uint32_t ddr_regdef_adr(uint32_t _regdef); 241 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); 242 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, 243 uint32_t val); 244 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); 245 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); 246 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); 247 static void ddr_setval_ach(uint32_t regdef, uint32_t val); 248 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); 249 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); 250 static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); 251 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); 252 static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); 253 static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); 254 static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); 255 static uint32_t ddrphy_regif_chk(void); 256 static inline void ddrphy_regif_idle(void); 257 static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, 258 uint16_t cyc); 259 static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, 260 uint16_t *_js2); 261 static int16_t _f_scale_adj(int16_t ps); 262 static void ddrtbl_load(void); 263 static void ddr_config_sub(void); 264 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); 265 static void ddr_config_sub_h3v1x(void); 266 static void ddr_config(void); 267 static void dbsc_regset(void); 268 static void dbsc_regset_post(void); 269 static uint32_t dfi_init_start(void); 270 static void change_lpddr4_en(uint32_t mode); 271 static uint32_t set_term_code(void); 272 static void ddr_register_set(void); 273 static inline uint32_t wait_freqchgreq(uint32_t assert); 274 static inline void set_freqchgack(uint32_t assert); 275 static inline void set_dfifrequency(uint32_t freq); 276 static uint32_t pll3_freq(uint32_t on); 277 static void update_dly(void); 278 static uint32_t pi_training_go(void); 279 static uint32_t init_ddr(void); 280 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); 281 static uint32_t wdqdm_man1(void); 282 static uint32_t wdqdm_man(void); 283 static uint32_t rdqdm_man1(void); 284 static uint32_t rdqdm_man(void); 285 286 static int32_t _find_change(uint64_t val, uint32_t dir); 287 static uint32_t _rx_offset_cal_updn(uint32_t code); 288 static uint32_t rx_offset_cal(void); 289 static uint32_t rx_offset_cal_hw(void); 290 static void adjust_rddqs_latency(void); 291 static void adjust_wpath_latency(void); 292 293 struct ddrt_data { 294 int32_t init_temp; /* Initial Temperature (do) */ 295 uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ 296 uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */ 297 }; 298 299 static struct ddrt_data tcal; 300 301 static void pvtcode_update(void); 302 static void pvtcode_update2(void); 303 static void ddr_padcal_tcompensate_getinit(uint32_t override); 304 305 /* load board configuration */ 306 #include "boot_init_dram_config.c" 307 308 #ifndef DDR_FAST_INIT 309 static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 310 static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 311 static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 312 static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 313 static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; 314 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); 315 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); 316 317 static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 318 static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 319 static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 320 static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 321 static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 322 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); 323 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); 324 #endif/* DDR_FAST_INIT */ 325 326 /* macro for channel selection loop */ 327 static inline uint32_t vch_nxt(uint32_t pos) 328 { 329 uint32_t posn; 330 331 for (posn = pos; posn < DRAM_CH_CNT; posn++) { 332 if (ddr_phyvalid & (1U << posn)) 333 break; 334 } 335 return posn; 336 } 337 338 #define foreach_vch(ch) \ 339 for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) 340 341 #define foreach_ech(ch) \ 342 for (ch = 0; ch < DRAM_CH_CNT; ch++) 343 344 /* Printing functions */ 345 #define MSG_LF(...) 346 347 /* clock settings, reset control */ 348 static void cpg_write_32(uint32_t a, uint32_t v) 349 { 350 mmio_write_32(CPG_CPGWPR, ~v); 351 mmio_write_32(a, v); 352 } 353 354 static void pll3_control(uint32_t high) 355 { 356 uint32_t data_l, data_div, data_mul, tmp_div; 357 358 if (high) { 359 tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / 360 (brd_clk * ddr_mul) / 2; 361 data_mul = ((ddr_mul * tmp_div) - 1) << 24; 362 pll3_mode = 1; 363 loop_max = 2; 364 } else { 365 tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / 366 (brd_clk * ddr0800_mul) / 2; 367 data_mul = ((ddr0800_mul * tmp_div) - 1) << 24; 368 pll3_mode = 0; 369 loop_max = 8; 370 } 371 372 switch (tmp_div) { 373 case 1: 374 data_div = 0; 375 break; 376 case 2: 377 case 3: 378 case 4: 379 data_div = tmp_div; 380 break; 381 default: 382 data_div = 6; 383 data_mul = (data_mul * tmp_div) / 3; 384 break; 385 } 386 data_mul = data_mul | (brd_clkdiva << 7); 387 388 /* PLL3 disable */ 389 data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; 390 cpg_write_32(CPG_PLLECR, data_l); 391 dsb_sev(); 392 393 if ((prr_product == PRR_PRODUCT_M3) || 394 ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) { 395 /* PLL3 DIV resetting(Lowest value:3) */ 396 data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); 397 cpg_write_32(CPG_FRQCRD, data_l); 398 dsb_sev(); 399 400 /* zb3 clk stop */ 401 data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); 402 cpg_write_32(CPG_ZB3CKCR, data_l); 403 dsb_sev(); 404 405 /* PLL3 enable */ 406 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); 407 cpg_write_32(CPG_PLLECR, data_l); 408 dsb_sev(); 409 410 do { 411 data_l = mmio_read_32(CPG_PLLECR); 412 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 413 dsb_sev(); 414 415 /* PLL3 DIV resetting (Highest value:0) */ 416 data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); 417 cpg_write_32(CPG_FRQCRD, data_l); 418 dsb_sev(); 419 420 /* DIV SET KICK */ 421 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 422 cpg_write_32(CPG_FRQCRB, data_l); 423 dsb_sev(); 424 425 /* PLL3 multiplie set */ 426 cpg_write_32(CPG_PLL3CR, data_mul); 427 dsb_sev(); 428 429 do { 430 data_l = mmio_read_32(CPG_PLLECR); 431 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 432 dsb_sev(); 433 434 /* PLL3 DIV resetting(Target value) */ 435 data_l = (data_div << 16) | data_div | 436 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); 437 cpg_write_32(CPG_FRQCRD, data_l); 438 dsb_sev(); 439 440 /* DIV SET KICK */ 441 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 442 cpg_write_32(CPG_FRQCRB, data_l); 443 dsb_sev(); 444 445 do { 446 data_l = mmio_read_32(CPG_PLLECR); 447 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 448 dsb_sev(); 449 450 /* zb3 clk start */ 451 data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); 452 cpg_write_32(CPG_ZB3CKCR, data_l); 453 dsb_sev(); 454 455 } else { /* H3Ver.3.0/M3N/V3H */ 456 457 /* PLL3 multiplie set */ 458 cpg_write_32(CPG_PLL3CR, data_mul); 459 dsb_sev(); 460 461 /* PLL3 DIV set(Target value) */ 462 data_l = (data_div << 16) | data_div | 463 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); 464 cpg_write_32(CPG_FRQCRD, data_l); 465 466 /* DIV SET KICK */ 467 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 468 cpg_write_32(CPG_FRQCRB, data_l); 469 dsb_sev(); 470 471 /* PLL3 enable */ 472 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); 473 cpg_write_32(CPG_PLLECR, data_l); 474 dsb_sev(); 475 476 do { 477 data_l = mmio_read_32(CPG_PLLECR); 478 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 479 dsb_sev(); 480 } 481 } 482 483 /* barrier */ 484 static inline void dsb_sev(void) 485 { 486 __asm__ __volatile__("dsb sy"); 487 } 488 489 /* DDR memory register access */ 490 static void wait_dbcmd(void) 491 { 492 uint32_t data_l; 493 /* dummy read */ 494 data_l = mmio_read_32(DBSC_DBCMD); 495 dsb_sev(); 496 while (1) { 497 /* wait DBCMD 1=busy, 0=ready */ 498 data_l = mmio_read_32(DBSC_DBWAIT); 499 dsb_sev(); 500 if ((data_l & 0x00000001) == 0x00) 501 break; 502 } 503 } 504 505 static void send_dbcmd(uint32_t cmd) 506 { 507 /* dummy read */ 508 wait_dbcmd(); 509 mmio_write_32(DBSC_DBCMD, cmd); 510 dsb_sev(); 511 } 512 513 static void dbwait_loop(uint32_t wait_loop) 514 { 515 uint32_t i; 516 517 for (i = 0; i < wait_loop; i++) 518 wait_dbcmd(); 519 } 520 521 /* DDRPHY register access (raw) */ 522 static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) 523 { 524 uint32_t val; 525 uint32_t loop; 526 527 val = 0; 528 if ((prr_product != PRR_PRODUCT_M3N) && 529 (prr_product != PRR_PRODUCT_V3H)) { 530 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 531 dsb_sev(); 532 533 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 534 dsb_sev(); 535 } 536 dsb_sev(); 537 538 for (loop = 0; loop < loop_max; loop++) { 539 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 540 dsb_sev(); 541 } 542 (void)val; 543 } else { 544 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); 545 dsb_sev(); 546 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != 547 (regadd | 0x0000C000)) { 548 dsb_sev(); 549 }; 550 val = mmio_read_32(DBSC_DBPDRGA(phyno)); 551 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 552 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 553 dsb_sev(); 554 }; 555 dsb_sev(); 556 557 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 558 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 559 dsb_sev(); 560 }; 561 562 dsb_sev(); 563 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 564 dsb_sev(); 565 (void)val; 566 } 567 return val; 568 } 569 570 static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) 571 { 572 uint32_t val; 573 uint32_t loop; 574 575 if ((prr_product != PRR_PRODUCT_M3N) && 576 (prr_product != PRR_PRODUCT_V3H)) { 577 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 578 dsb_sev(); 579 for (loop = 0; loop < loop_max; loop++) { 580 val = mmio_read_32(DBSC_DBPDRGA(phyno)); 581 dsb_sev(); 582 } 583 mmio_write_32(DBSC_DBPDRGD(phyno), regdata); 584 dsb_sev(); 585 586 for (loop = 0; loop < loop_max; loop++) { 587 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 588 dsb_sev(); 589 } 590 } else { 591 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 592 dsb_sev(); 593 594 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 595 dsb_sev(); 596 }; 597 dsb_sev(); 598 599 mmio_write_32(DBSC_DBPDRGD(phyno), regdata); 600 dsb_sev(); 601 602 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != 603 (regadd | 0x00008000)) { 604 dsb_sev(); 605 }; 606 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 607 608 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 609 dsb_sev(); 610 }; 611 dsb_sev(); 612 613 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 614 } 615 (void)val; 616 } 617 618 static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) 619 { 620 uint32_t ch; 621 uint32_t val; 622 uint32_t loop; 623 624 if ((prr_product != PRR_PRODUCT_M3N) && 625 (prr_product != PRR_PRODUCT_V3H)) { 626 foreach_vch(ch) { 627 mmio_write_32(DBSC_DBPDRGA(ch), regadd); 628 dsb_sev(); 629 } 630 631 foreach_vch(ch) { 632 mmio_write_32(DBSC_DBPDRGD(ch), regdata); 633 dsb_sev(); 634 } 635 636 for (loop = 0; loop < loop_max; loop++) { 637 val = mmio_read_32(DBSC_DBPDRGD(0)); 638 dsb_sev(); 639 } 640 (void)val; 641 } else { 642 foreach_vch(ch) { 643 reg_ddrphy_write(ch, regadd, regdata); 644 dsb_sev(); 645 } 646 } 647 } 648 649 static inline void ddrphy_regif_idle(void) 650 { 651 uint32_t val; 652 653 val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); 654 dsb_sev(); 655 (void)val; 656 } 657 658 /* DDRPHY register access (field modify) */ 659 static inline uint32_t ddr_regdef(uint32_t _regdef) 660 { 661 return p_ddr_regdef_tbl[_regdef]; 662 } 663 664 static inline uint32_t ddr_regdef_adr(uint32_t _regdef) 665 { 666 return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]); 667 } 668 669 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) 670 { 671 return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]); 672 } 673 674 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, 675 uint32_t val) 676 { 677 uint32_t adr; 678 uint32_t lsb; 679 uint32_t len; 680 uint32_t msk; 681 uint32_t tmp; 682 uint32_t regdef; 683 684 regdef = ddr_regdef(_regdef); 685 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; 686 len = DDR_REGDEF_LEN(regdef); 687 lsb = DDR_REGDEF_LSB(regdef); 688 if (len == 0x20) 689 msk = 0xffffffff; 690 else 691 msk = ((1U << len) - 1) << lsb; 692 693 tmp = reg_ddrphy_read(ch, adr); 694 tmp = (tmp & (~msk)) | ((val << lsb) & msk); 695 reg_ddrphy_write(ch, adr, tmp); 696 } 697 698 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) 699 { 700 uint32_t adr; 701 uint32_t lsb; 702 uint32_t len; 703 uint32_t msk; 704 uint32_t tmp; 705 uint32_t regdef; 706 707 regdef = ddr_regdef(_regdef); 708 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; 709 len = DDR_REGDEF_LEN(regdef); 710 lsb = DDR_REGDEF_LSB(regdef); 711 if (len == 0x20) 712 msk = 0xffffffff; 713 else 714 msk = ((1U << len) - 1); 715 716 tmp = reg_ddrphy_read(ch, adr); 717 tmp = (tmp >> lsb) & msk; 718 719 return tmp; 720 } 721 722 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) 723 { 724 ddr_setval_s(ch, 0, regdef, val); 725 } 726 727 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) 728 { 729 uint32_t ch; 730 731 foreach_vch(ch) 732 ddr_setval_s(ch, slice, regdef, val); 733 } 734 735 static void ddr_setval_ach(uint32_t regdef, uint32_t val) 736 { 737 ddr_setval_ach_s(0, regdef, val); 738 } 739 740 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) 741 { 742 uint32_t slice; 743 744 for (slice = 0; slice < SLICE_CNT; slice++) 745 ddr_setval_ach_s(slice, regdef, val); 746 } 747 748 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) 749 { 750 return ddr_getval_s(ch, 0, regdef); 751 } 752 753 static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p) 754 { 755 uint32_t ch; 756 757 foreach_vch(ch) 758 p[ch] = ddr_getval_s(ch, 0, regdef); 759 return p[0]; 760 } 761 762 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) 763 { 764 uint32_t ch, slice; 765 uint32_t *pp; 766 767 pp = p; 768 foreach_vch(ch) 769 for (slice = 0; slice < SLICE_CNT; slice++) 770 *pp++ = ddr_getval_s(ch, slice, regdef); 771 return p[0]; 772 } 773 774 /* handling functions for setteing ddrphy value table */ 775 static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) 776 { 777 uint32_t i; 778 779 for (i = 0; i < size; i++) { 780 to[i] = from[i]; 781 } 782 } 783 784 static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) 785 { 786 uint32_t adr; 787 uint32_t lsb; 788 uint32_t len; 789 uint32_t msk; 790 uint32_t tmp; 791 uint32_t adrmsk; 792 uint32_t regdef; 793 794 regdef = ddr_regdef(_regdef); 795 adr = DDR_REGDEF_ADR(regdef); 796 len = DDR_REGDEF_LEN(regdef); 797 lsb = DDR_REGDEF_LSB(regdef); 798 if (len == 0x20) 799 msk = 0xffffffff; 800 else 801 msk = ((1U << len) - 1) << lsb; 802 803 if (adr < 0x400) { 804 adrmsk = 0xff; 805 } else { 806 adrmsk = 0x7f; 807 } 808 809 tmp = tbl[adr & adrmsk]; 810 tmp = (tmp & (~msk)) | ((val << lsb) & msk); 811 tbl[adr & adrmsk] = tmp; 812 } 813 814 static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) 815 { 816 uint32_t adr; 817 uint32_t lsb; 818 uint32_t len; 819 uint32_t msk; 820 uint32_t tmp; 821 uint32_t adrmsk; 822 uint32_t regdef; 823 824 regdef = ddr_regdef(_regdef); 825 adr = DDR_REGDEF_ADR(regdef); 826 len = DDR_REGDEF_LEN(regdef); 827 lsb = DDR_REGDEF_LSB(regdef); 828 if (len == 0x20) 829 msk = 0xffffffff; 830 else 831 msk = ((1U << len) - 1); 832 833 if (adr < 0x400) { 834 adrmsk = 0xff; 835 } else { 836 adrmsk = 0x7f; 837 } 838 839 tmp = tbl[adr & adrmsk]; 840 tmp = (tmp >> lsb) & msk; 841 842 return tmp; 843 } 844 845 /* DDRPHY register access handling */ 846 static uint32_t ddrphy_regif_chk(void) 847 { 848 uint32_t tmp_ach[DRAM_CH_CNT]; 849 uint32_t ch; 850 uint32_t err; 851 uint32_t PI_VERSION_CODE; 852 853 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 854 (prr_product == PRR_PRODUCT_M3)) { 855 PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ 856 } else { 857 PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ 858 } 859 860 ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); 861 err = 0; 862 foreach_vch(ch) { 863 if (tmp_ach[ch] != PI_VERSION_CODE) 864 err = 1; 865 } 866 return err; 867 } 868 869 /* functions and parameters for timing setting */ 870 struct _jedec_spec1 { 871 uint16_t fx3; 872 uint8_t rlwodbi; 873 uint8_t rlwdbi; 874 uint8_t WL; 875 uint8_t nwr; 876 uint8_t nrtp; 877 uint8_t odtlon; 878 uint8_t MR1; 879 uint8_t MR2; 880 }; 881 882 #define JS1_USABLEC_SPEC_LO 2 883 #define JS1_USABLEC_SPEC_HI 5 884 #define JS1_FREQ_TBL_NUM 8 885 #define JS1_MR1(f) (0x04 | ((f) << 4)) 886 #define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) 887 const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { 888 /* 533.333Mbps */ 889 { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 }, 890 /* 1066.666Mbps */ 891 { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 }, 892 /* 1600.000Mbps */ 893 { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 }, 894 /* 2133.333Mbps */ 895 { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) }, 896 /* 2666.666Mbps */ 897 { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) }, 898 /* 3200.000Mbps */ 899 { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) }, 900 /* 3733.333Mbps */ 901 { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) }, 902 /* 4266.666Mbps */ 903 { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) } 904 }; 905 906 struct _jedec_spec2 { 907 uint16_t ps; 908 uint16_t cyc; 909 }; 910 911 #define js2_tsr 0 912 #define js2_txp 1 913 #define js2_trtp 2 914 #define js2_trcd 3 915 #define js2_trppb 4 916 #define js2_trpab 5 917 #define js2_tras 6 918 #define js2_twr 7 919 #define js2_twtr 8 920 #define js2_trrd 9 921 #define js2_tppd 10 922 #define js2_tfaw 11 923 #define js2_tdqsck 12 924 #define js2_tckehcmd 13 925 #define js2_tckelcmd 14 926 #define js2_tckelpd 15 927 #define js2_tmrr 16 928 #define js2_tmrw 17 929 #define js2_tmrd 18 930 #define js2_tzqcalns 19 931 #define js2_tzqlat 20 932 #define js2_tiedly 21 933 #define js2_tODTon_min 22 934 #define JS2_TBLCNT 23 935 936 #define js2_trcpb (JS2_TBLCNT) 937 #define js2_trcab (JS2_TBLCNT + 1) 938 #define js2_trfcab (JS2_TBLCNT + 2) 939 #define JS2_CNT (JS2_TBLCNT + 3) 940 941 #ifndef JS2_DERATE 942 #define JS2_DERATE 0 943 #endif 944 const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { 945 { 946 /*tSR */ {15000, 3}, 947 /*tXP */ {7500, 3}, 948 /*tRTP */ {7500, 8}, 949 /*tRCD */ {18000, 4}, 950 /*tRPpb */ {18000, 3}, 951 /*tRPab */ {21000, 3}, 952 /*tRAS */ {42000, 3}, 953 /*tWR */ {18000, 4}, 954 /*tWTR */ {10000, 8}, 955 /*tRRD */ {10000, 4}, 956 /*tPPD */ {0, 0}, 957 /*tFAW */ {40000, 0}, 958 /*tDQSCK*/ {3500, 0}, 959 /*tCKEHCMD*/ {7500, 3}, 960 /*tCKELCMD*/ {7500, 3}, 961 /*tCKELPD*/ {7500, 3}, 962 /*tMRR*/ {0, 8}, 963 /*tMRW*/ {10000, 10}, 964 /*tMRD*/ {14000, 10}, 965 /*tZQCALns*/ {1000 * 10, 0}, 966 /*tZQLAT*/ {30000, 10}, 967 /*tIEdly*/ {12500, 0}, 968 /*tODTon_min*/ {1500, 0} 969 }, { 970 /*tSR */ {15000, 3}, 971 /*tXP */ {7500, 3}, 972 /*tRTP */ {7500, 8}, 973 /*tRCD */ {19875, 4}, 974 /*tRPpb */ {19875, 3}, 975 /*tRPab */ {22875, 3}, 976 /*tRAS */ {43875, 3}, 977 /*tWR */ {18000, 4}, 978 /*tWTR */ {10000, 8}, 979 /*tRRD */ {11875, 4}, 980 /*tPPD */ {0, 0}, 981 /*tFAW */ {40000, 0}, 982 /*tDQSCK*/ {3600, 0}, 983 /*tCKEHCMD*/ {7500, 3}, 984 /*tCKELCMD*/ {7500, 3}, 985 /*tCKELPD*/ {7500, 3}, 986 /*tMRR*/ {0, 8}, 987 /*tMRW*/ {10000, 10}, 988 /*tMRD*/ {14000, 10}, 989 /*tZQCALns*/ {1000 * 10, 0}, 990 /*tZQLAT*/ {30000, 10}, 991 /*tIEdly*/ {12500, 0}, 992 /*tODTon_min*/ {1500, 0} 993 } 994 }; 995 996 const uint16_t jedec_spec2_trfc_ab[7] = { 997 /* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ 998 130, 180, 180, 280, 280, 560, 560 999 }; 1000 1001 static uint32_t js1_ind; 1002 static uint16_t js2[JS2_CNT]; 1003 static uint8_t RL; 1004 static uint8_t WL; 1005 1006 static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, 1007 uint16_t cyc) 1008 { 1009 uint32_t tmp; 1010 uint32_t div; 1011 1012 tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps; 1013 div = tmp / (200000 * _ddr_mbpsdiv); 1014 if (tmp != (div * 200000 * _ddr_mbpsdiv)) 1015 div = div + 1; 1016 1017 if (div > cyc) 1018 return (uint16_t)div; 1019 return cyc; 1020 } 1021 1022 static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, 1023 uint16_t *_js2) 1024 { 1025 int i; 1026 1027 for (i = 0; i < JS2_TBLCNT; i++) { 1028 _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv, 1029 1UL * jedec_spec2[JS2_DERATE][i].ps, 1030 jedec_spec2[JS2_DERATE][i].cyc); 1031 } 1032 1033 _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb]; 1034 _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab]; 1035 } 1036 1037 /* scaler for DELAY value */ 1038 static int16_t _f_scale_adj(int16_t ps) 1039 { 1040 int32_t tmp; 1041 /* 1042 * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; 1043 * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 1044 * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 1045 */ 1046 tmp = 1047 (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / 1048 (int32_t)ddr_mbpsdiv; 1049 tmp = (int32_t)tmp / (int32_t)15625; 1050 1051 return (int16_t)tmp; 1052 } 1053 1054 static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = { 1055 { 1056 _reg_PI_MR1_DATA_F0_0, 1057 _reg_PI_MR1_DATA_F0_1, 1058 _reg_PI_MR1_DATA_F0_2, 1059 _reg_PI_MR1_DATA_F0_3}, 1060 { 1061 _reg_PI_MR1_DATA_F1_0, 1062 _reg_PI_MR1_DATA_F1_1, 1063 _reg_PI_MR1_DATA_F1_2, 1064 _reg_PI_MR1_DATA_F1_3} 1065 }; 1066 1067 static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = { 1068 { 1069 _reg_PI_MR2_DATA_F0_0, 1070 _reg_PI_MR2_DATA_F0_1, 1071 _reg_PI_MR2_DATA_F0_2, 1072 _reg_PI_MR2_DATA_F0_3}, 1073 { 1074 _reg_PI_MR2_DATA_F1_0, 1075 _reg_PI_MR2_DATA_F1_1, 1076 _reg_PI_MR2_DATA_F1_2, 1077 _reg_PI_MR2_DATA_F1_3} 1078 }; 1079 1080 static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = { 1081 { 1082 _reg_PI_MR3_DATA_F0_0, 1083 _reg_PI_MR3_DATA_F0_1, 1084 _reg_PI_MR3_DATA_F0_2, 1085 _reg_PI_MR3_DATA_F0_3}, 1086 { 1087 _reg_PI_MR3_DATA_F1_0, 1088 _reg_PI_MR3_DATA_F1_1, 1089 _reg_PI_MR3_DATA_F1_2, 1090 _reg_PI_MR3_DATA_F1_3} 1091 }; 1092 1093 const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = { 1094 { 1095 _reg_PI_MR11_DATA_F0_0, 1096 _reg_PI_MR11_DATA_F0_1, 1097 _reg_PI_MR11_DATA_F0_2, 1098 _reg_PI_MR11_DATA_F0_3}, 1099 { 1100 _reg_PI_MR11_DATA_F1_0, 1101 _reg_PI_MR11_DATA_F1_1, 1102 _reg_PI_MR11_DATA_F1_2, 1103 _reg_PI_MR11_DATA_F1_3} 1104 }; 1105 1106 const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = { 1107 { 1108 _reg_PI_MR12_DATA_F0_0, 1109 _reg_PI_MR12_DATA_F0_1, 1110 _reg_PI_MR12_DATA_F0_2, 1111 _reg_PI_MR12_DATA_F0_3}, 1112 { 1113 _reg_PI_MR12_DATA_F1_0, 1114 _reg_PI_MR12_DATA_F1_1, 1115 _reg_PI_MR12_DATA_F1_2, 1116 _reg_PI_MR12_DATA_F1_3} 1117 }; 1118 1119 const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { 1120 { 1121 _reg_PI_MR14_DATA_F0_0, 1122 _reg_PI_MR14_DATA_F0_1, 1123 _reg_PI_MR14_DATA_F0_2, 1124 _reg_PI_MR14_DATA_F0_3}, 1125 { 1126 _reg_PI_MR14_DATA_F1_0, 1127 _reg_PI_MR14_DATA_F1_1, 1128 _reg_PI_MR14_DATA_F1_2, 1129 _reg_PI_MR14_DATA_F1_3} 1130 }; 1131 1132 /* 1133 * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) 1134 */ 1135 static void regif_pll_wa(void) 1136 { 1137 uint32_t ch; 1138 1139 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1140 // PLL setting for PHY : H3 Ver.1.x 1141 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), 1142 (0x0064U << 1143 ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); 1144 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 1145 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1146 _reg_PHY_PLL_CTRL)); 1147 1148 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), 1149 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1150 _reg_PHY_LP4_BOOT_PLL_CTRL)); 1151 1152 } else { 1153 /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ 1154 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), 1155 (0x5064U << 1156 ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); 1157 1158 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 1159 (ddrtbl_getval 1160 (_cnf_DDR_PHY_ADR_G_REGSET, 1161 _reg_PHY_PLL_CTRL_TOP) << 16) | 1162 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1163 _reg_PHY_PLL_CTRL)); 1164 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 1165 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1166 _reg_PHY_PLL_CTRL_CA)); 1167 1168 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), 1169 (ddrtbl_getval 1170 (_cnf_DDR_PHY_ADR_G_REGSET, 1171 _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | 1172 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1173 _reg_PHY_LP4_BOOT_PLL_CTRL)); 1174 reg_ddrphy_write_a(ddr_regdef_adr 1175 (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), 1176 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1177 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 1178 )); 1179 } 1180 1181 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), 1182 _cnf_DDR_PHY_ADR_G_REGSET 1183 [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - 1184 DDR_PHY_ADR_G_REGSET_OFS]); 1185 1186 /* protect register interface */ 1187 ddrphy_regif_idle(); 1188 pll3_control(0); 1189 1190 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1191 /* non */ 1192 } else { 1193 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), 1194 (0x01U << 1195 ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); 1196 ddrphy_regif_idle(); 1197 } 1198 1199 /* init start */ 1200 /* dbdficnt0: 1201 * dfi_dram_clk_disable=1 1202 * dfi_frequency = 0 1203 * freq_ratio = 01 (2:1) 1204 * init_start =0 1205 */ 1206 foreach_vch(ch) 1207 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); 1208 dsb_sev(); 1209 1210 /* dbdficnt0: 1211 * dfi_dram_clk_disable=1 1212 * dfi_frequency = 0 1213 * freq_ratio = 01 (2:1) 1214 * init_start =1 1215 */ 1216 foreach_vch(ch) 1217 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); 1218 dsb_sev(); 1219 1220 foreach_ech(ch) 1221 if ((board_cnf->phyvalid) & BIT(ch)) 1222 while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) 1223 ; 1224 dsb_sev(); 1225 } 1226 1227 /* load table data into DDR registers */ 1228 static void ddrtbl_load(void) 1229 { 1230 uint32_t i; 1231 uint32_t slice; 1232 uint32_t csab; 1233 uint32_t adr; 1234 uint32_t data_l; 1235 uint32_t tmp[3]; 1236 uint16_t dataS; 1237 1238 /* TIMING REGISTERS */ 1239 /* search jedec_spec1 index */ 1240 for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { 1241 if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) 1242 break; 1243 } 1244 if (i > JS1_USABLEC_SPEC_HI) 1245 js1_ind = JS1_USABLEC_SPEC_HI; 1246 else 1247 js1_ind = i; 1248 1249 if (board_cnf->dbi_en) 1250 RL = js1[js1_ind].rlwdbi; 1251 else 1252 RL = js1[js1_ind].rlwodbi; 1253 1254 WL = js1[js1_ind].WL; 1255 1256 /* calculate jedec_spec2 */ 1257 _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); 1258 1259 /* PREPARE TBL */ 1260 if (prr_product == PRR_PRODUCT_H3) { 1261 if (prr_cut <= PRR_PRODUCT_11) { 1262 /* H3 Ver.1.x */ 1263 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1264 DDR_PHY_SLICE_REGSET_H3, 1265 DDR_PHY_SLICE_REGSET_NUM_H3); 1266 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1267 DDR_PHY_ADR_V_REGSET_H3, 1268 DDR_PHY_ADR_V_REGSET_NUM_H3); 1269 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, 1270 DDR_PHY_ADR_I_REGSET_H3, 1271 DDR_PHY_ADR_I_REGSET_NUM_H3); 1272 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1273 DDR_PHY_ADR_G_REGSET_H3, 1274 DDR_PHY_ADR_G_REGSET_NUM_H3); 1275 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3, 1276 DDR_PI_REGSET_NUM_H3); 1277 1278 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3; 1279 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3; 1280 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3; 1281 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3; 1282 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3; 1283 DDR_PHY_SLICE_REGSET_SIZE = 1284 DDR_PHY_SLICE_REGSET_SIZE_H3; 1285 DDR_PHY_ADR_V_REGSET_SIZE = 1286 DDR_PHY_ADR_V_REGSET_SIZE_H3; 1287 DDR_PHY_ADR_I_REGSET_SIZE = 1288 DDR_PHY_ADR_I_REGSET_SIZE_H3; 1289 DDR_PHY_ADR_G_REGSET_SIZE = 1290 DDR_PHY_ADR_G_REGSET_SIZE_H3; 1291 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3; 1292 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3; 1293 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3; 1294 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3; 1295 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3; 1296 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3; 1297 1298 DDR_PHY_ADR_I_NUM = 1; 1299 } else { 1300 /* H3 Ver.2.0 or later */ 1301 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1302 DDR_PHY_SLICE_REGSET_H3VER2, 1303 DDR_PHY_SLICE_REGSET_NUM_H3VER2); 1304 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1305 DDR_PHY_ADR_V_REGSET_H3VER2, 1306 DDR_PHY_ADR_V_REGSET_NUM_H3VER2); 1307 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1308 DDR_PHY_ADR_G_REGSET_H3VER2, 1309 DDR_PHY_ADR_G_REGSET_NUM_H3VER2); 1310 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2, 1311 DDR_PI_REGSET_NUM_H3VER2); 1312 1313 DDR_PHY_SLICE_REGSET_OFS = 1314 DDR_PHY_SLICE_REGSET_OFS_H3VER2; 1315 DDR_PHY_ADR_V_REGSET_OFS = 1316 DDR_PHY_ADR_V_REGSET_OFS_H3VER2; 1317 DDR_PHY_ADR_G_REGSET_OFS = 1318 DDR_PHY_ADR_G_REGSET_OFS_H3VER2; 1319 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2; 1320 DDR_PHY_SLICE_REGSET_SIZE = 1321 DDR_PHY_SLICE_REGSET_SIZE_H3VER2; 1322 DDR_PHY_ADR_V_REGSET_SIZE = 1323 DDR_PHY_ADR_V_REGSET_SIZE_H3VER2; 1324 DDR_PHY_ADR_G_REGSET_SIZE = 1325 DDR_PHY_ADR_G_REGSET_SIZE_H3VER2; 1326 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2; 1327 DDR_PHY_SLICE_REGSET_NUM = 1328 DDR_PHY_SLICE_REGSET_NUM_H3VER2; 1329 DDR_PHY_ADR_V_REGSET_NUM = 1330 DDR_PHY_ADR_V_REGSET_NUM_H3VER2; 1331 DDR_PHY_ADR_G_REGSET_NUM = 1332 DDR_PHY_ADR_G_REGSET_NUM_H3VER2; 1333 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2; 1334 1335 DDR_PHY_ADR_I_NUM = 0; 1336 } 1337 } else if (prr_product == PRR_PRODUCT_M3) { 1338 /* M3-W */ 1339 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1340 DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); 1341 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1342 DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3); 1343 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, 1344 DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3); 1345 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1346 DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3); 1347 _tblcopy(_cnf_DDR_PI_REGSET, 1348 DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3); 1349 1350 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3; 1351 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3; 1352 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3; 1353 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3; 1354 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3; 1355 DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3; 1356 DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3; 1357 DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3; 1358 DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3; 1359 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3; 1360 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3; 1361 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3; 1362 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3; 1363 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3; 1364 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3; 1365 1366 DDR_PHY_ADR_I_NUM = 2; 1367 } else { 1368 /* M3-N/V3H */ 1369 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1370 DDR_PHY_SLICE_REGSET_M3N, 1371 DDR_PHY_SLICE_REGSET_NUM_M3N); 1372 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N, 1373 DDR_PHY_ADR_V_REGSET_NUM_M3N); 1374 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N, 1375 DDR_PHY_ADR_I_REGSET_NUM_M3N); 1376 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N, 1377 DDR_PHY_ADR_G_REGSET_NUM_M3N); 1378 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N, 1379 DDR_PI_REGSET_NUM_M3N); 1380 1381 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N; 1382 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N; 1383 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N; 1384 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N; 1385 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N; 1386 DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N; 1387 DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N; 1388 DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N; 1389 DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N; 1390 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N; 1391 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N; 1392 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N; 1393 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N; 1394 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N; 1395 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N; 1396 1397 DDR_PHY_ADR_I_NUM = 2; 1398 } 1399 1400 /* PLL CODE CHANGE */ 1401 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { 1402 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 1403 0x1142); 1404 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1405 _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); 1406 } 1407 1408 /* on fly gate adjust */ 1409 if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { 1410 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1411 _reg_ON_FLY_GATE_ADJUST_EN, 0x00); 1412 } 1413 1414 /* Adjust PI parameters */ 1415 #ifdef _def_LPDDR4_ODT 1416 for (i = 0; i < 2; i++) { 1417 for (csab = 0; csab < CSAB_CNT; csab++) { 1418 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1419 reg_pi_mr11_data_fx_csx[i][csab], 1420 _def_LPDDR4_ODT); 1421 } 1422 } 1423 #endif /* _def_LPDDR4_ODT */ 1424 1425 #ifdef _def_LPDDR4_VREFCA 1426 for (i = 0; i < 2; i++) { 1427 for (csab = 0; csab < CSAB_CNT; csab++) { 1428 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1429 reg_pi_mr12_data_fx_csx[i][csab], 1430 _def_LPDDR4_VREFCA); 1431 } 1432 } 1433 #endif /* _def_LPDDR4_VREFCA */ 1434 if ((prr_product == PRR_PRODUCT_M3N) || 1435 (prr_product == PRR_PRODUCT_V3H)) { 1436 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; 1437 if (js2[js2_tiedly] > (RL)) 1438 js2[js2_tiedly] = RL; 1439 } else if ((prr_product == PRR_PRODUCT_H3) && 1440 (prr_cut > PRR_PRODUCT_11)) { 1441 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; 1442 } else if ((prr_product == PRR_PRODUCT_H3) && 1443 (prr_cut <= PRR_PRODUCT_11)) { 1444 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); 1445 } 1446 1447 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 1448 (prr_product == PRR_PRODUCT_M3N) || 1449 (prr_product == PRR_PRODUCT_V3H)) { 1450 if ((js2[js2_tiedly]) >= 0x1e) 1451 dataS = 0x1e; 1452 else 1453 dataS = js2[js2_tiedly]; 1454 } else { 1455 if ((js2[js2_tiedly]) >= 0x0e) 1456 dataS = 0x0e; 1457 else 1458 dataS = js2[js2_tiedly]; 1459 } 1460 1461 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); 1462 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, 1463 (dataS - 2)); 1464 if ((prr_product == PRR_PRODUCT_M3N) || 1465 (prr_product == PRR_PRODUCT_V3H)) { 1466 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1467 _reg_PHY_RDDATA_EN_OE_DLY, dataS - 2); 1468 } 1469 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); 1470 1471 if (ddrtbl_getval 1472 (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { 1473 data_l = WL - 1; 1474 } else { 1475 data_l = WL; 1476 } 1477 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2); 1478 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l); 1479 1480 if (board_cnf->dbi_en) { 1481 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 1482 0x01); 1483 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1484 _reg_PHY_WDQLVL_DATADM_MASK, 0x000); 1485 } else { 1486 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 1487 0x00); 1488 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1489 _reg_PHY_WDQLVL_DATADM_MASK, 0x100); 1490 } 1491 1492 tmp[0] = js1[js1_ind].MR1; 1493 tmp[1] = js1[js1_ind].MR2; 1494 data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); 1495 if (board_cnf->dbi_en) 1496 tmp[2] = data_l | 0xc0; 1497 else 1498 tmp[2] = data_l & (~0xc0); 1499 1500 for (i = 0; i < 2; i++) { 1501 for (csab = 0; csab < CSAB_CNT; csab++) { 1502 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1503 reg_pi_mr1_data_fx_csx[i][csab], tmp[0]); 1504 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1505 reg_pi_mr2_data_fx_csx[i][csab], tmp[1]); 1506 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1507 reg_pi_mr3_data_fx_csx[i][csab], tmp[2]); 1508 } 1509 } 1510 1511 /* DDRPHY INT START */ 1512 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1513 /* non */ 1514 } else { 1515 regif_pll_wa(); 1516 dbwait_loop(5); 1517 } 1518 1519 /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ 1520 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1521 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 1522 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); 1523 1524 /* SET DATA SLICE TABLE */ 1525 for (slice = 0; slice < SLICE_CNT; slice++) { 1526 adr = 1527 DDR_PHY_SLICE_REGSET_OFS + 1528 DDR_PHY_SLICE_REGSET_SIZE * slice; 1529 for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) { 1530 reg_ddrphy_write_a(adr + i, 1531 _cnf_DDR_PHY_SLICE_REGSET[i]); 1532 } 1533 } 1534 1535 /* SET ADR SLICE TABLE */ 1536 adr = DDR_PHY_ADR_V_REGSET_OFS; 1537 for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { 1538 reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); 1539 } 1540 1541 if (((prr_product == PRR_PRODUCT_M3) || 1542 (prr_product == PRR_PRODUCT_M3N)) && 1543 ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) 1544 != 0x00)) { 1545 adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; 1546 for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { 1547 reg_ddrphy_write_a(adr + i, 1548 _cnf_DDR_PHY_ADR_V_REGSET[i]); 1549 } 1550 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1551 _reg_PHY_ADR_DISABLE, 0x02); 1552 DDR_PHY_ADR_I_NUM -= 1; 1553 ddr_phycaslice = 1; 1554 1555 #ifndef _def_LPDDR4_ODT 1556 for (i = 0; i < 2; i++) { 1557 for (csab = 0; csab < CSAB_CNT; csab++) { 1558 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1559 reg_pi_mr11_data_fx_csx[i][csab], 1560 0x66); 1561 } 1562 } 1563 #endif/* _def_LPDDR4_ODT */ 1564 } else { 1565 ddr_phycaslice = 0; 1566 } 1567 1568 if (DDR_PHY_ADR_I_NUM > 0) { 1569 for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) { 1570 adr = 1571 DDR_PHY_ADR_I_REGSET_OFS + 1572 DDR_PHY_ADR_I_REGSET_SIZE * slice; 1573 for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) { 1574 reg_ddrphy_write_a(adr + i, 1575 _cnf_DDR_PHY_ADR_I_REGSET 1576 [i]); 1577 } 1578 } 1579 } 1580 1581 /* SET ADRCTRL SLICE TABLE */ 1582 adr = DDR_PHY_ADR_G_REGSET_OFS; 1583 for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { 1584 reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); 1585 } 1586 1587 /* SET PI REGISTERS */ 1588 adr = DDR_PI_REGSET_OFS; 1589 for (i = 0; i < DDR_PI_REGSET_NUM; i++) { 1590 reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); 1591 } 1592 } 1593 1594 /* CONFIGURE DDR REGISTERS */ 1595 static void ddr_config_sub(void) 1596 { 1597 uint32_t i; 1598 uint32_t ch, slice; 1599 uint32_t data_l; 1600 uint32_t tmp; 1601 uint8_t high_byte[SLICE_CNT]; 1602 const uint32_t _par_CALVL_DEVICE_MAP = 1; 1603 1604 foreach_vch(ch) { 1605 /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ 1606 for (slice = 0; slice < SLICE_CNT; slice++) { 1607 high_byte[slice] = 1608 (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; 1609 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, 1610 board_cnf->ch[ch].dq_swap[slice]); 1611 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, 1612 board_cnf->ch[ch].dm_swap[slice]); 1613 if (high_byte[slice]) { 1614 /* HIGHER 16 BYTE */ 1615 ddr_setval_s(ch, slice, 1616 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1617 0x00); 1618 } else { 1619 /* LOWER 16 BYTE */ 1620 ddr_setval_s(ch, slice, 1621 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1622 0x01); 1623 } 1624 } 1625 1626 /* BOARD SETTINGS (CA,ADDR_SEL) */ 1627 data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | 1628 0x00888888; 1629 1630 /* --- ADR_CALVL_SWIZZLE --- */ 1631 if (prr_product == PRR_PRODUCT_M3) { 1632 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); 1633 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 1634 0x00000000); 1635 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); 1636 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 1637 0x00000000); 1638 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 1639 _par_CALVL_DEVICE_MAP); 1640 } else { 1641 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); 1642 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); 1643 ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, 1644 _par_CALVL_DEVICE_MAP); 1645 } 1646 1647 /* --- ADR_ADDR_SEL --- */ 1648 if ((prr_product == PRR_PRODUCT_H3) && 1649 (prr_cut > PRR_PRODUCT_11)) { 1650 data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1651 } else { 1652 data_l = 0; 1653 tmp = board_cnf->ch[ch].ca_swap; 1654 for (i = 0; i < 6; i++) { 1655 data_l |= ((tmp & 0x0f) << (i * 5)); 1656 tmp = tmp >> 4; 1657 } 1658 } 1659 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l); 1660 if (ddr_phycaslice == 1) { 1661 /* ----------- adr slice2 swap ----------- */ 1662 tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40); 1663 data_l = (tmp & 0x00ffffff) | 0x00888888; 1664 1665 /* --- ADR_CALVL_SWIZZLE --- */ 1666 if (prr_product == PRR_PRODUCT_M3) { 1667 ddr_setval_s(ch, 2, 1668 _reg_PHY_ADR_CALVL_SWIZZLE0_0, 1669 data_l); 1670 ddr_setval_s(ch, 2, 1671 _reg_PHY_ADR_CALVL_SWIZZLE1_0, 1672 0x00000000); 1673 ddr_setval_s(ch, 2, 1674 _reg_PHY_ADR_CALVL_SWIZZLE0_1, 1675 data_l); 1676 ddr_setval_s(ch, 2, 1677 _reg_PHY_ADR_CALVL_SWIZZLE1_1, 1678 0x00000000); 1679 ddr_setval_s(ch, 2, 1680 _reg_PHY_ADR_CALVL_DEVICE_MAP, 1681 _par_CALVL_DEVICE_MAP); 1682 } else { 1683 ddr_setval_s(ch, 2, 1684 _reg_PHY_ADR_CALVL_SWIZZLE0, 1685 data_l); 1686 ddr_setval_s(ch, 2, 1687 _reg_PHY_ADR_CALVL_SWIZZLE1, 1688 0x00000000); 1689 ddr_setval_s(ch, 2, 1690 _reg_PHY_CALVL_DEVICE_MAP, 1691 _par_CALVL_DEVICE_MAP); 1692 } 1693 1694 /* --- ADR_ADDR_SEL --- */ 1695 data_l = 0; 1696 for (i = 0; i < 6; i++) { 1697 data_l |= ((tmp & 0x0f) << (i * 5)); 1698 tmp = tmp >> 4; 1699 } 1700 1701 ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); 1702 } 1703 1704 /* BOARD SETTINGS (BYTE_ORDER_SEL) */ 1705 if (prr_product == PRR_PRODUCT_M3) { 1706 /* --- DATA_BYTE_SWAP --- */ 1707 data_l = 0; 1708 tmp = board_cnf->ch[ch].dqs_swap; 1709 for (i = 0; i < 4; i++) { 1710 data_l |= ((tmp & 0x03) << (i * 2)); 1711 tmp = tmp >> 4; 1712 } 1713 } else { 1714 /* --- DATA_BYTE_SWAP --- */ 1715 data_l = board_cnf->ch[ch].dqs_swap; 1716 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); 1717 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, 1718 (data_l) & 0x0f); 1719 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, 1720 (data_l >> 4 * 1) & 0x0f); 1721 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, 1722 (data_l >> 4 * 2) & 0x0f); 1723 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, 1724 (data_l >> 4 * 3) & 0x0f); 1725 1726 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); 1727 } 1728 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l); 1729 } 1730 } 1731 1732 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) 1733 { 1734 uint32_t slice; 1735 uint32_t tmp; 1736 uint32_t tgt; 1737 1738 if (ddr_csn / 2) { 1739 tgt = 3; 1740 } else { 1741 tgt = 1; 1742 } 1743 1744 for (slice = 0; slice < SLICE_CNT; slice++) { 1745 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 1746 if (tgt == tmp) 1747 break; 1748 } 1749 tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1750 if (slice % 2) 1751 tmp |= 0x00888888; 1752 *p_swz = tmp; 1753 } 1754 1755 static void ddr_config_sub_h3v1x(void) 1756 { 1757 uint32_t ch, slice; 1758 uint32_t data_l; 1759 uint32_t tmp; 1760 uint8_t high_byte[SLICE_CNT]; 1761 uint32_t ca_swizzle; 1762 uint32_t ca; 1763 uint32_t csmap; 1764 uint32_t o_inv; 1765 uint32_t inv; 1766 uint32_t bit_soc; 1767 uint32_t bit_mem; 1768 uint32_t j; 1769 1770 const uint8_t o_mr15 = 0x55; 1771 const uint8_t o_mr20 = 0x55; 1772 const uint16_t o_mr32_mr40 = 0x5a3c; 1773 1774 foreach_vch(ch) { 1775 /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ 1776 csmap = 0; 1777 for (slice = 0; slice < SLICE_CNT; slice++) { 1778 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 1779 0x0f; 1780 high_byte[slice] = tmp % 2; 1781 if (tmp == 1 && (slice >= 2)) 1782 csmap |= 0x05; 1783 if (tmp == 3 && (slice >= 2)) 1784 csmap |= 0x50; 1785 ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, 1786 board_cnf->ch[ch].dq_swap[slice]); 1787 if (high_byte[slice]) { 1788 /* HIGHER 16 BYTE */ 1789 ddr_setval_s(ch, slice, 1790 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1791 0x00); 1792 } else { 1793 /* LOWER 16 BYTE */ 1794 ddr_setval_s(ch, slice, 1795 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1796 0x01); 1797 } 1798 } 1799 /* BOARD SETTINGS (CA,ADDR_SEL) */ 1800 ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1801 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); 1802 ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); 1803 1804 get_ca_swizzle(ch, 0, &ca_swizzle); 1805 1806 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle); 1807 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); 1808 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000); 1809 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); 1810 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01); 1811 1812 for (slice = 0; slice < SLICE_CNT; slice++) { 1813 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM, 1814 0x01); 1815 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START, 1816 0x08); 1817 1818 if (high_byte[slice]) 1819 o_inv = o_mr20; 1820 else 1821 o_inv = o_mr15; 1822 1823 tmp = board_cnf->ch[ch].dq_swap[slice]; 1824 inv = 0; 1825 j = 0; 1826 for (bit_soc = 0; bit_soc < 8; bit_soc++) { 1827 bit_mem = (tmp >> (4 * bit_soc)) & 0x0f; 1828 j |= (1U << bit_mem); 1829 if (o_inv & (1U << bit_mem)) 1830 inv |= (1U << bit_soc); 1831 } 1832 data_l = o_mr32_mr40; 1833 if (!high_byte[slice]) 1834 data_l |= (inv << 24); 1835 if (high_byte[slice]) 1836 data_l |= (inv << 16); 1837 ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, 1838 data_l); 1839 } 1840 } 1841 } 1842 1843 static void ddr_config(void) 1844 { 1845 int32_t i; 1846 uint32_t ch, slice; 1847 uint32_t data_l; 1848 uint32_t tmp; 1849 int8_t _adj; 1850 int16_t adj; 1851 uint32_t dq; 1852 union { 1853 uint32_t ui32[4]; 1854 uint8_t ui8[16]; 1855 } patt; 1856 uint16_t patm; 1857 1858 /* configure ddrphy registers */ 1859 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1860 ddr_config_sub_h3v1x(); 1861 } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ 1862 ddr_config_sub(); 1863 } 1864 1865 /* WDQ_USER_PATT */ 1866 foreach_vch(ch) { 1867 for (slice = 0; slice < SLICE_CNT; slice++) { 1868 patm = 0; 1869 for (i = 0; i < 16; i++) { 1870 tmp = board_cnf->ch[ch].wdqlvl_patt[i]; 1871 patt.ui8[i] = tmp & 0xff; 1872 if (tmp & 0x100) 1873 patm |= (1U << i); 1874 } 1875 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, 1876 patt.ui32[0]); 1877 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, 1878 patt.ui32[1]); 1879 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, 1880 patt.ui32[2]); 1881 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, 1882 patt.ui32[3]); 1883 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); 1884 } 1885 } 1886 1887 /* CACS DLY */ 1888 data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); 1889 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1890 0x00U); 1891 foreach_vch(ch) { 1892 for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) { 1893 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 1894 ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, 1895 _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 1896 data_l + adj); 1897 reg_ddrphy_write(ch, 1898 ddr_regdef_adr 1899 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), 1900 _cnf_DDR_PHY_ADR_V_REGSET 1901 [ddr_regdef_adr 1902 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1903 DDR_PHY_ADR_V_REGSET_OFS]); 1904 } 1905 1906 for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); 1907 i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { 1908 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 1909 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1910 _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 1911 data_l + adj); 1912 reg_ddrphy_write(ch, 1913 ddr_regdef_adr 1914 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), 1915 _cnf_DDR_PHY_ADR_G_REGSET 1916 [ddr_regdef_adr 1917 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1918 DDR_PHY_ADR_G_REGSET_OFS]); 1919 } 1920 1921 if (ddr_phycaslice == 1) { 1922 for (i = 0; i < 6; i++) { 1923 adj = _f_scale_adj 1924 (board_cnf->ch[ch].cacs_adj 1925 [i + 1926 _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); 1927 ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, 1928 _reg_PHY_CLK_CACS_SLAVE_DELAY_X 1929 [i], 1930 data_l + adj); 1931 reg_ddrphy_write(ch, 1932 ddr_regdef_adr 1933 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 1934 0x0100, 1935 _cnf_DDR_PHY_ADR_V_REGSET 1936 [ddr_regdef_adr 1937 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1938 DDR_PHY_ADR_V_REGSET_OFS]); 1939 } 1940 } 1941 } 1942 1943 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1944 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 1945 1946 /* WDQDM DLY */ 1947 data_l = board_cnf->dqdm_dly_w; 1948 foreach_vch(ch) { 1949 for (slice = 0; slice < SLICE_CNT; slice++) { 1950 for (i = 0; i <= 8; i++) { 1951 dq = slice * 8 + i; 1952 if (i == 8) 1953 _adj = board_cnf->ch[ch].dm_adj_w[slice]; 1954 else 1955 _adj = board_cnf->ch[ch].dq_adj_w[dq]; 1956 adj = _f_scale_adj(_adj); 1957 ddr_setval_s(ch, slice, 1958 _reg_PHY_CLK_WRX_SLAVE_DELAY[i], 1959 data_l + adj); 1960 } 1961 } 1962 } 1963 1964 /* RDQDM DLY */ 1965 data_l = board_cnf->dqdm_dly_r; 1966 foreach_vch(ch) { 1967 for (slice = 0; slice < SLICE_CNT; slice++) { 1968 for (i = 0; i <= 8; i++) { 1969 dq = slice * 8 + i; 1970 if (i == 8) 1971 _adj = board_cnf->ch[ch].dm_adj_r[slice]; 1972 else 1973 _adj = board_cnf->ch[ch].dq_adj_r[dq]; 1974 adj = _f_scale_adj(_adj); 1975 ddr_setval_s(ch, slice, 1976 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY 1977 [i], data_l + adj); 1978 ddr_setval_s(ch, slice, 1979 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 1980 [i], data_l + adj); 1981 } 1982 } 1983 } 1984 } 1985 1986 /* DBSC register setting functions */ 1987 static void dbsc_regset_pre(void) 1988 { 1989 uint32_t ch, csab; 1990 uint32_t data_l; 1991 1992 /* PRIMARY SETTINGS */ 1993 /* LPDDR4, BL=16, DFI interface */ 1994 mmio_write_32(DBSC_DBKIND, 0x0000000a); 1995 mmio_write_32(DBSC_DBBL, 0x00000002); 1996 mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); 1997 1998 /* FREQRATIO=2 */ 1999 mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); 2000 2001 /* Chanel map (H3 Ver.1.x) */ 2002 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) 2003 mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); 2004 2005 /* DRAM SIZE REGISTER: 2006 * set all ranks as density=0(4Gb) for PHY initialization 2007 */ 2008 foreach_vch(ch) { 2009 for (csab = 0; csab < 4; csab++) { 2010 mmio_write_32(DBSC_DBMEMCONF(ch, csab), 2011 DBMEMCONF_REGD(0)); 2012 } 2013 } 2014 2015 if (prr_product == PRR_PRODUCT_M3) { 2016 data_l = 0xe4e4e4e4; 2017 foreach_ech(ch) { 2018 if ((ddr_phyvalid & (1U << ch))) 2019 data_l = (data_l & (~(0x000000FF << (ch * 8)))) 2020 | (((board_cnf->ch[ch].dqs_swap & 0x0003) 2021 | ((board_cnf->ch[ch].dqs_swap & 0x0030) 2022 >> 2) 2023 | ((board_cnf->ch[ch].dqs_swap & 0x0300) 2024 >> 4) 2025 | ((board_cnf->ch[ch].dqs_swap & 0x3000) 2026 >> 6)) << (ch * 8)); 2027 } 2028 mmio_write_32(DBSC_DBBSWAP, data_l); 2029 } 2030 } 2031 2032 static void dbsc_regset(void) 2033 { 2034 int32_t i; 2035 uint32_t ch; 2036 uint32_t data_l; 2037 uint32_t data_l2; 2038 uint32_t tmp[4]; 2039 2040 /* RFC */ 2041 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && 2042 (max_density == 0)) { 2043 js2[js2_trfcab] = 2044 _f_scale(ddr_mbps, ddr_mbpsdiv, 2045 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); 2046 } else { 2047 js2[js2_trfcab] = 2048 _f_scale(ddr_mbps, ddr_mbpsdiv, 2049 1UL * jedec_spec2_trfc_ab[max_density] * 2050 1000, 0); 2051 } 2052 2053 /* DBTR0.CL : RL */ 2054 mmio_write_32(DBSC_DBTR(0), RL); 2055 2056 /* DBTR1.CWL : WL */ 2057 mmio_write_32(DBSC_DBTR(1), WL); 2058 2059 /* DBTR2.AL : 0 */ 2060 mmio_write_32(DBSC_DBTR(2), 0); 2061 2062 /* DBTR3.TRCD: tRCD */ 2063 mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); 2064 2065 /* DBTR4.TRPA,TRP: tRPab,tRPpb */ 2066 mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); 2067 2068 /* DBTR5.TRC : use tRCpb */ 2069 mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); 2070 2071 /* DBTR6.TRAS : tRAS */ 2072 mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); 2073 2074 /* DBTR7.TRRD : tRRD */ 2075 mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); 2076 2077 /* DBTR8.TFAW : tFAW */ 2078 mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); 2079 2080 /* DBTR9.TRDPR : tRTP */ 2081 mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); 2082 2083 /* DBTR10.TWR : nWR */ 2084 mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr); 2085 2086 /* 2087 * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff - 2088 * odtlon + tDQSCK - tODTon,min + 2089 * PCB delay (out+in) + tPHY_ODToff 2090 */ 2091 mmio_write_32(DBSC_DBTR(11), 2092 RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon + 2093 js2[js2_tdqsck] - js2[js2_tODTon_min] + 2094 _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0)); 2095 2096 /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ 2097 data_l = WL + 1 + (16 / 2) + js2[js2_twtr]; 2098 mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l); 2099 2100 /* DBTR13.TRFCAB : tRFCab */ 2101 mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab])); 2102 2103 /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ 2104 mmio_write_32(DBSC_DBTR(14), 2105 (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd])); 2106 2107 /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ 2108 mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd])); 2109 2110 /* DBTR16 */ 2111 /* WDQL : tphy_wrlat + tphy_wrdata */ 2112 tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); 2113 /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 2114 * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 2115 */ 2116 tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); 2117 /* DQL : tphy_rdlat + trdata_en */ 2118 /* it is not important for dbsc */ 2119 tmp[2] = RL + 16; 2120 /* DQIENLTNCY : trdata_en */ 2121 tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; 2122 mmio_write_32(DBSC_DBTR(16), 2123 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2124 2125 /* DBTR24 */ 2126 /* WRCSLAT = WRLAT -5 */ 2127 tmp[0] -= 5; 2128 /* WRCSGAP = 5 */ 2129 tmp[1] = 5; 2130 /* RDCSLAT = RDLAT_ADJ +2 */ 2131 if (prr_product == PRR_PRODUCT_M3) { 2132 tmp[2] = tmp[3]; 2133 } else { 2134 tmp[2] = tmp[3] + 2; 2135 } 2136 /* RDCSGAP = 6 */ 2137 if (prr_product == PRR_PRODUCT_M3) { 2138 tmp[3] = 4; 2139 } else { 2140 tmp[3] = 6; 2141 } 2142 mmio_write_32(DBSC_DBTR(24), 2143 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2144 2145 /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ 2146 mmio_write_32(DBSC_DBTR(17), 2147 (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16)); 2148 2149 /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ 2150 mmio_write_32(DBSC_DBTR(18), 0); 2151 2152 /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ 2153 mmio_write_32(DBSC_DBTR(19), 0); 2154 2155 /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ 2156 data_l = js2[js2_trfcab] + js2[js2_tckehcmd]; 2157 mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l); 2158 2159 /* DBTR21.TCCD */ 2160 /* DBTR23.TCCD */ 2161 /* H3 Ver.1.0 cannot use TBTR23 feature */ 2162 if (ddr_tccd == 8 && 2163 !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10)) 2164 ) { 2165 data_l = 8; 2166 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2167 mmio_write_32(DBSC_DBTR(23), 0x00000002); 2168 } else if (ddr_tccd <= 11) { 2169 data_l = 11; 2170 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2171 mmio_write_32(DBSC_DBTR(23), 0x00000000); 2172 } else { 2173 data_l = ddr_tccd; 2174 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2175 mmio_write_32(DBSC_DBTR(23), 0x00000000); 2176 } 2177 2178 /* DBTR22.ZQLAT : */ 2179 data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */ 2180 data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20); 2181 mmio_write_32(DBSC_DBTR(22), data_l); 2182 2183 /* DBTR25 : do not use in LPDDR4 */ 2184 mmio_write_32(DBSC_DBTR(25), 0); 2185 2186 /* DBRNK : */ 2187 /* 2188 * DBSC_DBRNK2 rkrr 2189 * DBSC_DBRNK3 rkrw 2190 * DBSC_DBRNK4 rkwr 2191 * DBSC_DBRNK5 rkww 2192 */ 2193 #define _par_DBRNK_VAL (0x7007) 2194 2195 for (i = 0; i < 4; i++) { 2196 data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; 2197 if ((prr_product == PRR_PRODUCT_H3) && 2198 (prr_cut > PRR_PRODUCT_11) && (i == 0)) { 2199 data_l += 1; 2200 } 2201 data_l2 = 0; 2202 foreach_vch(ch) { 2203 data_l2 = data_l2 | (data_l << (4 * ch)); 2204 } 2205 mmio_write_32(DBSC_DBRNK(2 + i), data_l2); 2206 } 2207 mmio_write_32(DBSC_DBADJ0, 0x00000000); 2208 2209 /* timing registers for Scheduler */ 2210 /* SCFCTST0 */ 2211 /* SCFCTST0 ACT-ACT */ 2212 tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; 2213 /* SCFCTST0 RDA-ACT */ 2214 tmp[2] = 2215 1UL * ((16 / 2) + js2[js2_trtp] - 8 + 2216 js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps; 2217 /* SCFCTST0 WRA-ACT */ 2218 tmp[1] = 2219 1UL * (WL + 1 + (16 / 2) + 2220 js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps; 2221 /* SCFCTST0 PRE-ACT */ 2222 tmp[0] = 1UL * js2[js2_trppb]; 2223 mmio_write_32(DBSC_SCFCTST0, 2224 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2225 2226 /* SCFCTST1 */ 2227 /* SCFCTST1 RD-WR */ 2228 tmp[3] = 2229 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / 2230 ddr_mbps; 2231 /* SCFCTST1 WR-RD */ 2232 tmp[2] = 2233 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / 2234 ddr_mbps; 2235 /* SCFCTST1 ACT-RD/WR */ 2236 tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps; 2237 /* SCFCTST1 ASYNCOFS */ 2238 tmp[0] = 12; 2239 mmio_write_32(DBSC_SCFCTST1, 2240 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2241 2242 /* DBSCHRW1 */ 2243 /* DBSCHRW1 SCTRFCAB */ 2244 tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps; 2245 data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) 2246 + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2247 + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; 2248 if (tmp[0] < data_l) 2249 tmp[0] = data_l; 2250 2251 if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { 2252 mmio_write_32(DBSC_DBSCHRW1, tmp[0] 2253 + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2254 * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / 2255 ddr_mbps - 3); 2256 } else { 2257 mmio_write_32(DBSC_DBSCHRW1, tmp[0] 2258 + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2259 * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / 2260 ddr_mbps); 2261 } 2262 2263 /* QOS and CAM */ 2264 #ifdef ddr_qos_init_setting /* only for non qos_init */ 2265 /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ 2266 mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); 2267 /*0(fillunit),8(dirtymax),4(dirtymin) */ 2268 mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); 2269 /*stop_tolerance */ 2270 mmio_write_32(DBSC_DBSCHRW0, 0x22421111); 2271 /*rd-wr/wr-rd toggle priority */ 2272 mmio_write_32(DBSC_SCFCTST2, 0x012F1123); 2273 mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); 2274 mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); 2275 2276 /* QoS Settings */ 2277 mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); 2278 mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); 2279 mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); 2280 mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); 2281 mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); 2282 mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); 2283 mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); 2284 mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); 2285 mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); 2286 mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); 2287 mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); 2288 mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); 2289 mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); 2290 mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); 2291 mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); 2292 mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); 2293 mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); 2294 mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); 2295 mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); 2296 mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); 2297 mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); 2298 mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); 2299 mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); 2300 mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); 2301 mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); 2302 mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); 2303 mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); 2304 mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); 2305 2306 mmio_write_32(QOSCTRL_RAEN, 0x00000001U); 2307 #endif /* ddr_qos_init_setting */ 2308 /* H3 Ver.1.1 need to set monitor function */ 2309 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { 2310 mmio_write_32(DBSC_DBMONCONF4, 0x00700000); 2311 } 2312 2313 if (prr_product == PRR_PRODUCT_H3) { 2314 if (prr_cut == PRR_PRODUCT_10) { 2315 /* resrdis, simple mode, sc off */ 2316 mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); 2317 } else if (prr_cut == PRR_PRODUCT_11) { 2318 /* resrdis, simple mode */ 2319 mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); 2320 } else if (prr_cut < PRR_PRODUCT_30) { 2321 /* H3 Ver.2.0 */ 2322 /* resrdis */ 2323 mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); 2324 } else { /* H3 Ver.3.0(include H3N) */ 2325 /* exprespque */ 2326 mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); 2327 } 2328 } else { /* M3-W/M3-N/V3H */ 2329 /* resrdis */ 2330 mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); 2331 } 2332 } 2333 2334 static void dbsc_regset_post(void) 2335 { 2336 uint32_t ch, cs; 2337 uint32_t data_l; 2338 uint32_t slice, rdlat_max, rdlat_min; 2339 2340 rdlat_max = 0; 2341 rdlat_min = 0xffff; 2342 foreach_vch(ch) { 2343 for (cs = 0; cs < CS_CNT; cs++) { 2344 if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { 2345 for (slice = 0; slice < SLICE_CNT; slice++) { 2346 ddr_setval_s(ch, slice, 2347 _reg_PHY_PER_CS_TRAINING_INDEX, 2348 cs); 2349 data_l = ddr_getval_s(ch, slice, 2350 _reg_PHY_RDDQS_LATENCY_ADJUST); 2351 if (data_l > rdlat_max) 2352 rdlat_max = data_l; 2353 if (data_l < rdlat_min) 2354 rdlat_min = data_l; 2355 } 2356 } 2357 } 2358 } 2359 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) { 2360 #if RCAR_DRAM_SPLIT == 2 2361 if (board_cnf->phyvalid == 0x05) { 2362 mmio_write_32(DBSC_DBTR(24), 2363 (rdlat_max << 24) + (rdlat_min << 16) + 2364 mmio_read_32(DBSC_DBTR(24))); 2365 } else { 2366 mmio_write_32(DBSC_DBTR(24), 2367 ((rdlat_max * 2 - rdlat_min + 4) << 24) + 2368 ((rdlat_min + 2) << 16) + 2369 mmio_read_32(DBSC_DBTR(24))); 2370 } 2371 #else /*RCAR_DRAM_SPLIT == 2 */ 2372 mmio_write_32(DBSC_DBTR(24), 2373 ((rdlat_max * 2 - rdlat_min + 4) << 24) + 2374 ((rdlat_min + 2) << 16) + 2375 mmio_read_32(DBSC_DBTR(24))); 2376 #endif /*RCAR_DRAM_SPLIT == 2 */ 2377 } else { 2378 mmio_write_32(DBSC_DBTR(24), 2379 ((rdlat_max + 2) << 24) + 2380 ((rdlat_max + 2) << 16) + 2381 mmio_read_32(DBSC_DBTR(24))); 2382 } 2383 2384 /* set ddr density information */ 2385 foreach_ech(ch) { 2386 for (cs = 0; cs < CS_CNT; cs++) { 2387 if (ddr_density[ch][cs] == 0xff) { 2388 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); 2389 } else { 2390 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 2391 DBMEMCONF_REGD(ddr_density[ch] 2392 [cs])); 2393 } 2394 } 2395 mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); 2396 mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); 2397 } 2398 2399 mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); 2400 2401 /*set DBI */ 2402 if (board_cnf->dbi_en) 2403 mmio_write_32(DBSC_DBDBICNT, 0x00000003); 2404 2405 /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ 2406 if ((((prr_product == PRR_PRODUCT_H3) && 2407 (prr_cut > PRR_PRODUCT_11)) || 2408 (prr_product == PRR_PRODUCT_M3N) || 2409 (prr_product == PRR_PRODUCT_V3H)) && 2410 board_cnf->dbi_en) 2411 reg_ddrphy_write_a(0x00001010, 0x01000000); 2412 2413 /*set REFCYCLE */ 2414 data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; 2415 mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff)); 2416 mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); 2417 2418 #if RCAR_REWT_TRAINING != 0 2419 /* Periodic-WriteDQ Training seeting */ 2420 if (((prr_product == PRR_PRODUCT_H3) && 2421 (prr_cut <= PRR_PRODUCT_11)) || 2422 ((prr_product == PRR_PRODUCT_M3) && 2423 (prr_cut == PRR_PRODUCT_10))) { 2424 /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ 2425 } else { 2426 /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ 2427 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); 2428 2429 ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); 2430 ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); 2431 ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); 2432 ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); 2433 2434 ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, 2435 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2436 _reg_PI_WDQLVL_CS_MAP)); 2437 ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); 2438 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); 2439 ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); 2440 ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); 2441 ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); 2442 ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); 2443 2444 if (prr_product == PRR_PRODUCT_M3) { 2445 ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); 2446 } else { 2447 ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); 2448 } 2449 ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); 2450 2451 /* DFI_PHYMSTR_ACK , WTmode setting */ 2452 /* DFI_PHYMSTR_ACK: WTmode =b'01 */ 2453 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); 2454 } 2455 #endif /* RCAR_REWT_TRAINING */ 2456 /* periodic dram zqcal enable */ 2457 mmio_write_32(DBSC_DBCALCNF, 0x01000010); 2458 2459 /* periodic phy ctrl update enable */ 2460 if (((prr_product == PRR_PRODUCT_H3) && 2461 (prr_cut <= PRR_PRODUCT_11)) || 2462 ((prr_product == PRR_PRODUCT_M3) && 2463 (prr_cut < PRR_PRODUCT_30))) { 2464 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 2465 } else { 2466 #if RCAR_DRAM_SPLIT == 2 2467 if ((prr_product == PRR_PRODUCT_H3) && 2468 (board_cnf->phyvalid == 0x05)) 2469 mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); 2470 else 2471 mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); 2472 #else /* RCAR_DRAM_SPLIT == 2 */ 2473 mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); 2474 #endif /* RCAR_DRAM_SPLIT == 2 */ 2475 } 2476 2477 #ifdef DDR_BACKUPMODE 2478 /* SRX */ 2479 if (ddr_backup == DRAM_BOOT_STATUS_WARM) { 2480 #ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */ 2481 NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n"); 2482 send_dbcmd(0x0A040001); 2483 if (Prr_Product == PRR_PRODUCT_H3) 2484 send_dbcmd(0x0A140001); 2485 #else /* DDR_BACKUPMODE_HALF */ /* for All channels */ 2486 send_dbcmd(0x0A840001); 2487 #endif /* DDR_BACKUPMODE_HALF */ 2488 } 2489 #endif /* DDR_BACKUPMODE */ 2490 2491 /* set Auto Refresh */ 2492 mmio_write_32(DBSC_DBRFEN, 0x00000001); 2493 2494 #if RCAR_REWT_TRAINING != 0 2495 /* Periodic WriteDQ Traning */ 2496 if (((prr_product == PRR_PRODUCT_H3) && 2497 (prr_cut <= PRR_PRODUCT_11)) || 2498 ((prr_product == PRR_PRODUCT_M3) && 2499 (prr_cut == PRR_PRODUCT_10))) { 2500 /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ 2501 } else { 2502 /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ 2503 ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); 2504 } 2505 #endif /* RCAR_REWT_TRAINING */ 2506 2507 /* dram access enable */ 2508 mmio_write_32(DBSC_DBACEN, 0x00000001); 2509 2510 MSG_LF(__func__ "(done)"); 2511 } 2512 2513 /* DFI_INIT_START */ 2514 static uint32_t dfi_init_start(void) 2515 { 2516 uint32_t ch; 2517 uint32_t phytrainingok; 2518 uint32_t retry; 2519 uint32_t data_l; 2520 const uint32_t RETRY_MAX = 0x10000; 2521 2522 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2523 /* PLL3 Disable */ 2524 /* protect register interface */ 2525 ddrphy_regif_idle(); 2526 2527 pll3_control(0); 2528 2529 /* init start */ 2530 /* dbdficnt0: 2531 * dfi_dram_clk_disable=1 2532 * dfi_frequency = 0 2533 * freq_ratio = 01 (2:1) 2534 * init_start =0 2535 */ 2536 foreach_vch(ch) 2537 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); 2538 dsb_sev(); 2539 2540 /* dbdficnt0: 2541 * dfi_dram_clk_disable=1 2542 * dfi_frequency = 0 2543 * freq_ratio = 01 (2:1) 2544 * init_start =1 2545 */ 2546 foreach_vch(ch) 2547 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); 2548 dsb_sev(); 2549 2550 } else { 2551 ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); 2552 dsb_sev(); 2553 ddrphy_regif_idle(); 2554 } 2555 2556 /* dll_rst negate */ 2557 foreach_vch(ch) 2558 mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); 2559 dsb_sev(); 2560 2561 /* wait init_complete */ 2562 phytrainingok = 0; 2563 retry = 0; 2564 while (retry++ < RETRY_MAX) { 2565 foreach_vch(ch) { 2566 data_l = mmio_read_32(DBSC_DBDFISTAT(ch)); 2567 if (data_l & 0x00000001) 2568 phytrainingok |= (1U << ch); 2569 } 2570 dsb_sev(); 2571 if (phytrainingok == ddr_phyvalid) 2572 break; 2573 if (retry % 256 == 0) 2574 ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); 2575 } 2576 2577 /* all ch ok? */ 2578 if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) 2579 return 0xff; 2580 2581 /* dbdficnt0: 2582 * dfi_dram_clk_disable=0 2583 * dfi_frequency = 0 2584 * freq_ratio = 01 (2:1) 2585 * init_start =0 2586 */ 2587 foreach_vch(ch) 2588 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); 2589 dsb_sev(); 2590 2591 return 0; 2592 } 2593 2594 /* drivablity setting : CMOS MODE ON/OFF */ 2595 static void change_lpddr4_en(uint32_t mode) 2596 { 2597 uint32_t ch; 2598 uint32_t i; 2599 uint32_t data_l; 2600 const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { 2601 _reg_PHY_PAD_ADDR_DRIVE, 2602 _reg_PHY_PAD_CLK_DRIVE, 2603 _reg_PHY_PAD_CS_DRIVE 2604 }; 2605 2606 foreach_vch(ch) { 2607 for (i = 0; i < 3; i++) { 2608 data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); 2609 if (mode) { 2610 data_l |= (1U << 14); 2611 } else { 2612 data_l &= ~(1U << 14); 2613 } 2614 ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l); 2615 } 2616 } 2617 } 2618 2619 /* drivablity setting */ 2620 static uint32_t set_term_code(void) 2621 { 2622 int32_t i; 2623 uint32_t ch, index; 2624 uint32_t data_l; 2625 uint32_t chip_id[2]; 2626 uint32_t term_code; 2627 uint32_t override; 2628 uint32_t pvtr; 2629 uint32_t pvtp; 2630 uint32_t pvtn; 2631 2632 term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 2633 _reg_PHY_PAD_DATA_TERM); 2634 override = 0; 2635 for (i = 0; i < 2; i++) 2636 chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); 2637 2638 index = 0; 2639 while (1) { 2640 if (termcode_by_sample[index][0] == 0xffffffff) { 2641 break; 2642 } 2643 if ((termcode_by_sample[index][0] == chip_id[0]) && 2644 (termcode_by_sample[index][1] == chip_id[1])) { 2645 term_code = termcode_by_sample[index][2]; 2646 override = 1; 2647 break; 2648 } 2649 index++; 2650 } 2651 2652 if (override) { 2653 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { 2654 data_l = 2655 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 2656 _reg_PHY_PAD_TERM_X[index]); 2657 data_l = (data_l & 0xfffe0000) | term_code; 2658 ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); 2659 } 2660 } else if ((prr_product == PRR_PRODUCT_M3) && 2661 (prr_cut == PRR_PRODUCT_10)) { 2662 /* non */ 2663 } else { 2664 ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], 2665 (ddrtbl_getval 2666 (_cnf_DDR_PHY_ADR_G_REGSET, 2667 _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); 2668 ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); 2669 ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); 2670 foreach_vch(ch) { 2671 do { 2672 data_l = 2673 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); 2674 } while (!(data_l & 0x00800000)); 2675 } 2676 if ((prr_product == PRR_PRODUCT_H3) && 2677 (prr_cut <= PRR_PRODUCT_11)) { 2678 foreach_vch(ch) { 2679 data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); 2680 pvtr = (data_l >> 12) & 0x1f; 2681 pvtr += 8; 2682 if (pvtr > 0x1f) 2683 pvtr = 0x1f; 2684 data_l = 2685 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); 2686 pvtn = (data_l >> 6) & 0x03f; 2687 pvtp = (data_l >> 0) & 0x03f; 2688 2689 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; 2690 index++) { 2691 data_l = 2692 ddrtbl_getval 2693 (_cnf_DDR_PHY_ADR_G_REGSET, 2694 _reg_PHY_PAD_TERM_X[index]); 2695 data_l = (data_l & 0xfffe0000) 2696 | (pvtr << 12) 2697 | (pvtn << 6) 2698 | (pvtp); 2699 ddr_setval(ch, 2700 _reg_PHY_PAD_TERM_X[index], 2701 data_l); 2702 } 2703 } 2704 } else { 2705 /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ 2706 foreach_vch(ch) { 2707 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; 2708 index++) { 2709 data_l = 2710 ddr_getval(ch, 2711 _reg_PHY_PAD_TERM_X 2712 [index]); 2713 ddr_setval(ch, 2714 _reg_PHY_PAD_TERM_X[index], 2715 (data_l & 0xFFFE0FFF) | 2716 0x00015000); 2717 } 2718 } 2719 } 2720 } 2721 2722 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2723 /* non */ 2724 } else { 2725 ddr_padcal_tcompensate_getinit(override); 2726 } 2727 2728 return 0; 2729 } 2730 2731 /* DDR mode register setting */ 2732 static void ddr_register_set(void) 2733 { 2734 int32_t fspwp; 2735 uint32_t tmp; 2736 2737 for (fspwp = 1; fspwp >= 0; fspwp--) { 2738 /*MR13, fspwp */ 2739 send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); 2740 2741 tmp = 2742 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2743 reg_pi_mr1_data_fx_csx[fspwp][0]); 2744 send_dbcmd(0x0e840100 | tmp); 2745 2746 tmp = 2747 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2748 reg_pi_mr2_data_fx_csx[fspwp][0]); 2749 send_dbcmd(0x0e840200 | tmp); 2750 2751 tmp = 2752 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2753 reg_pi_mr3_data_fx_csx[fspwp][0]); 2754 send_dbcmd(0x0e840300 | tmp); 2755 2756 tmp = 2757 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2758 reg_pi_mr11_data_fx_csx[fspwp][0]); 2759 send_dbcmd(0x0e840b00 | tmp); 2760 2761 tmp = 2762 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2763 reg_pi_mr12_data_fx_csx[fspwp][0]); 2764 send_dbcmd(0x0e840c00 | tmp); 2765 2766 tmp = 2767 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2768 reg_pi_mr14_data_fx_csx[fspwp][0]); 2769 send_dbcmd(0x0e840e00 | tmp); 2770 /* MR22 */ 2771 send_dbcmd(0x0e841616); 2772 2773 /* ZQCAL start */ 2774 send_dbcmd(0x0d84004F); 2775 2776 /* ZQLAT */ 2777 send_dbcmd(0x0d840051); 2778 } 2779 2780 /* MR13, fspwp */ 2781 send_dbcmd(0x0e840d08); 2782 } 2783 2784 /* Training handshake functions */ 2785 static inline uint32_t wait_freqchgreq(uint32_t assert) 2786 { 2787 uint32_t data_l; 2788 uint32_t count; 2789 uint32_t ch; 2790 2791 count = 100000; 2792 2793 /* H3 Ver.1.x cannot see frqchg_req */ 2794 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2795 return 0; 2796 } 2797 2798 if (assert) { 2799 do { 2800 data_l = 1; 2801 foreach_vch(ch) { 2802 data_l &= mmio_read_32(DBSC_DBPDSTAT(ch)); 2803 } 2804 count = count - 1; 2805 } while (((data_l & 0x01) != 0x01) & (count != 0)); 2806 } else { 2807 do { 2808 data_l = 0; 2809 foreach_vch(ch) { 2810 data_l |= mmio_read_32(DBSC_DBPDSTAT(ch)); 2811 } 2812 count = count - 1; 2813 } while (((data_l & 0x01) != 0x00) & (count != 0)); 2814 } 2815 2816 return (count == 0); 2817 } 2818 2819 static inline void set_freqchgack(uint32_t assert) 2820 { 2821 uint32_t ch; 2822 uint32_t data_l; 2823 2824 if (assert) 2825 data_l = 0x0CF20000; 2826 else 2827 data_l = 0x00000000; 2828 2829 foreach_vch(ch) 2830 mmio_write_32(DBSC_DBPDCNT2(ch), data_l); 2831 } 2832 2833 static inline void set_dfifrequency(uint32_t freq) 2834 { 2835 uint32_t ch; 2836 2837 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2838 foreach_vch(ch) 2839 mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); 2840 } else { 2841 foreach_vch(ch) { 2842 mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, 2843 (freq << 24)); 2844 } 2845 } 2846 dsb_sev(); 2847 } 2848 2849 static uint32_t pll3_freq(uint32_t on) 2850 { 2851 uint32_t timeout; 2852 2853 timeout = wait_freqchgreq(1); 2854 2855 if (timeout) { 2856 return 1; 2857 } 2858 2859 pll3_control(on); 2860 set_dfifrequency(on); 2861 2862 set_freqchgack(1); 2863 timeout = wait_freqchgreq(0); 2864 set_freqchgack(0); 2865 2866 if (timeout) { 2867 FATAL_MSG("BL2: Time out[2]\n"); 2868 return 1; 2869 } 2870 return 0; 2871 } 2872 2873 /* update dly */ 2874 static void update_dly(void) 2875 { 2876 ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); 2877 ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); 2878 } 2879 2880 /* training by pi */ 2881 static uint32_t pi_training_go(void) 2882 { 2883 uint32_t flag; 2884 uint32_t data_l; 2885 uint32_t retry; 2886 const uint32_t RETRY_MAX = 4096 * 16; 2887 uint32_t ch; 2888 2889 uint32_t mst_ch; 2890 uint32_t cur_frq; 2891 uint32_t complete; 2892 uint32_t frqchg_req; 2893 2894 /* pi_start */ 2895 ddr_setval_ach(_reg_PI_START, 0x01); 2896 foreach_vch(ch) 2897 ddr_getval(ch, _reg_PI_INT_STATUS); 2898 2899 /* set dfi_phymstr_ack = 1 */ 2900 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); 2901 dsb_sev(); 2902 2903 /* wait pi_int_status[0] */ 2904 mst_ch = 0; 2905 flag = 0; 2906 complete = 0; 2907 cur_frq = 0; 2908 retry = RETRY_MAX; 2909 do { 2910 frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; 2911 2912 /* H3 Ver.1.x cannot see frqchg_req */ 2913 if ((prr_product == PRR_PRODUCT_H3) && 2914 (prr_cut <= PRR_PRODUCT_11)) { 2915 if ((retry % 4096) == 1) { 2916 frqchg_req = 1; 2917 } else { 2918 frqchg_req = 0; 2919 } 2920 } 2921 2922 if (frqchg_req) { 2923 if (cur_frq) { 2924 /* Low frequency */ 2925 flag = pll3_freq(0); 2926 cur_frq = 0; 2927 } else { 2928 /* High frequency */ 2929 flag = pll3_freq(1); 2930 cur_frq = 1; 2931 } 2932 if (flag) 2933 break; 2934 } else { 2935 if (cur_frq) { 2936 foreach_vch(ch) { 2937 if (complete & (1U << ch)) 2938 continue; 2939 data_l = 2940 ddr_getval(ch, _reg_PI_INT_STATUS); 2941 if (data_l & 0x01) { 2942 complete |= (1U << ch); 2943 } 2944 } 2945 if (complete == ddr_phyvalid) 2946 break; 2947 } 2948 } 2949 } while (--retry); 2950 foreach_vch(ch) { 2951 /* dummy read */ 2952 data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); 2953 data_l = ddr_getval(ch, _reg_PI_INT_STATUS); 2954 ddr_setval(ch, _reg_PI_INT_ACK, data_l); 2955 } 2956 if (ddrphy_regif_chk()) { 2957 return 0xfd; 2958 } 2959 return complete; 2960 } 2961 2962 /* Initialize DDR */ 2963 static uint32_t init_ddr(void) 2964 { 2965 int32_t i; 2966 uint32_t data_l; 2967 uint32_t phytrainingok; 2968 uint32_t ch, slice; 2969 uint32_t err; 2970 int16_t adj; 2971 2972 MSG_LF(__func__ ":0\n"); 2973 2974 #ifdef DDR_BACKUPMODE 2975 rcar_dram_get_boot_status(&ddr_backup); 2976 #endif 2977 2978 /* unlock phy */ 2979 /* Unlock DDRPHY register(AGAIN) */ 2980 foreach_vch(ch) 2981 mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); 2982 dsb_sev(); 2983 2984 if ((((prr_product == PRR_PRODUCT_H3) && 2985 (prr_cut > PRR_PRODUCT_11)) || 2986 (prr_product == PRR_PRODUCT_M3N) || 2987 (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en) 2988 reg_ddrphy_write_a(0x00001010, 0x01000001); 2989 else 2990 reg_ddrphy_write_a(0x00001010, 0x00000001); 2991 /* DBSC register pre-setting */ 2992 dbsc_regset_pre(); 2993 2994 /* load ddrphy registers */ 2995 2996 ddrtbl_load(); 2997 2998 /* configure ddrphy registers */ 2999 ddr_config(); 3000 3001 /* dfi_reset assert */ 3002 foreach_vch(ch) 3003 mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); 3004 dsb_sev(); 3005 3006 /* dbsc register set */ 3007 dbsc_regset(); 3008 MSG_LF(__func__ ":1\n"); 3009 3010 /* dfi_reset negate */ 3011 foreach_vch(ch) 3012 mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); 3013 dsb_sev(); 3014 3015 /* dfi_init_start (start ddrphy) */ 3016 err = dfi_init_start(); 3017 if (err) { 3018 return INITDRAM_ERR_I; 3019 } 3020 MSG_LF(__func__ ":2\n"); 3021 3022 /* ddr backupmode end */ 3023 #ifdef DDR_BACKUPMODE 3024 if (ddr_backup) { 3025 NOTICE("BL2: [WARM_BOOT]\n"); 3026 } else { 3027 NOTICE("BL2: [COLD_BOOT]\n"); 3028 } 3029 err = rcar_dram_update_boot_status(ddr_backup); 3030 if (err) { 3031 NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); 3032 return INITDRAM_ERR_I; 3033 } 3034 #endif 3035 MSG_LF(__func__ ":3\n"); 3036 3037 /* override term code after dfi_init_complete */ 3038 err = set_term_code(); 3039 if (err) { 3040 return INITDRAM_ERR_I; 3041 } 3042 MSG_LF(__func__ ":4\n"); 3043 3044 /* rx offset calibration */ 3045 if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || 3046 (prr_product == PRR_PRODUCT_V3H)) { 3047 err = rx_offset_cal_hw(); 3048 } else { 3049 err = rx_offset_cal(); 3050 } 3051 if (err) 3052 return INITDRAM_ERR_O; 3053 MSG_LF(__func__ ":5\n"); 3054 3055 /* Dummy PDE */ 3056 send_dbcmd(0x08840000); 3057 3058 /* PDX */ 3059 send_dbcmd(0x08840001); 3060 3061 /* check register i/f is alive */ 3062 err = ddrphy_regif_chk(); 3063 if (err) { 3064 return INITDRAM_ERR_O; 3065 } 3066 MSG_LF(__func__ ":6\n"); 3067 3068 /* phy initialize end */ 3069 3070 /* setup DDR mode registers */ 3071 /* CMOS MODE */ 3072 change_lpddr4_en(0); 3073 3074 /* MRS */ 3075 ddr_register_set(); 3076 3077 /* Thermal sensor setting */ 3078 /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ 3079 data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; 3080 mmio_write_32(THS1_THCTR, data_l); 3081 3082 /* LPDDR4 MODE */ 3083 change_lpddr4_en(1); 3084 3085 MSG_LF(__func__ ":7\n"); 3086 3087 /* mask CS_MAP if RANKx is not found */ 3088 foreach_vch(ch) { 3089 data_l = ddr_getval(ch, _reg_PI_CS_MAP); 3090 if (!(ch_have_this_cs[1] & (1U << ch))) 3091 data_l = data_l & 0x05; 3092 ddr_setval(ch, _reg_PI_CS_MAP, data_l); 3093 } 3094 3095 /* exec pi_training */ 3096 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 3097 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 3098 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); 3099 3100 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3101 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); 3102 } else { 3103 foreach_vch(ch) { 3104 for (slice = 0; slice < SLICE_CNT; slice++) { 3105 ddr_setval_s(ch, slice, 3106 _reg_PHY_PER_CS_TRAINING_EN, 3107 ((ch_have_this_cs[1]) >> ch) 3108 & 0x01); 3109 } 3110 } 3111 } 3112 3113 phytrainingok = pi_training_go(); 3114 3115 if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { 3116 return INITDRAM_ERR_T | phytrainingok; 3117 } 3118 3119 MSG_LF(__func__ ":8\n"); 3120 3121 /* CACS DLY ADJUST */ 3122 data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); 3123 foreach_vch(ch) { 3124 for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { 3125 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 3126 ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 3127 data_l + adj); 3128 } 3129 3130 if (ddr_phycaslice == 1) { 3131 for (i = 0; i < 6; i++) { 3132 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj 3133 [i + 3134 _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); 3135 ddr_setval_s(ch, 2, 3136 _reg_PHY_CLK_CACS_SLAVE_DELAY_X 3137 [i], 3138 data_l + adj 3139 ); 3140 } 3141 } 3142 } 3143 3144 update_dly(); 3145 MSG_LF(__func__ ":9\n"); 3146 3147 /* H3 fix rd latency to avoid bug in elasitic buffer */ 3148 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) 3149 adjust_rddqs_latency(); 3150 3151 /* Adjust Write path latency */ 3152 if (ddrtbl_getval 3153 (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) 3154 adjust_wpath_latency(); 3155 3156 /* RDQLVL Training */ 3157 if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) 3158 ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); 3159 3160 err = rdqdm_man(); 3161 3162 if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) 3163 ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); 3164 3165 if (err) { 3166 return INITDRAM_ERR_T; 3167 } 3168 update_dly(); 3169 MSG_LF(__func__ ":10\n"); 3170 3171 /* WDQLVL Training */ 3172 err = wdqdm_man(); 3173 if (err) { 3174 return INITDRAM_ERR_T; 3175 } 3176 update_dly(); 3177 MSG_LF(__func__ ":11\n"); 3178 3179 /* training complete, setup DBSC */ 3180 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 3181 (prr_product == PRR_PRODUCT_M3N) || 3182 (prr_product == PRR_PRODUCT_V3H)) { 3183 ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); 3184 ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); 3185 } 3186 3187 dbsc_regset_post(); 3188 MSG_LF(__func__ ":12\n"); 3189 3190 return phytrainingok; 3191 } 3192 3193 /* SW LEVELING COMMON */ 3194 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) 3195 { 3196 uint32_t ch; 3197 uint32_t data_l; 3198 uint32_t retry; 3199 uint32_t waiting; 3200 uint32_t err; 3201 3202 const uint32_t RETRY_MAX = 0x1000; 3203 3204 err = 0; 3205 /* set EXIT -> OP_DONE is cleared */ 3206 ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); 3207 3208 /* kick */ 3209 foreach_vch(ch) { 3210 if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) { 3211 ddr_setval(ch, reg_cs, ddr_csn); 3212 ddr_setval(ch, reg_kick, 0x01); 3213 } 3214 } 3215 foreach_vch(ch) { 3216 /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */ 3217 ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); 3218 } 3219 waiting = ch_have_this_cs[ddr_csn % 2]; 3220 dsb_sev(); 3221 retry = RETRY_MAX; 3222 do { 3223 foreach_vch(ch) { 3224 if (!(waiting & (1U << ch))) 3225 continue; 3226 data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); 3227 if (data_l & 0x01) 3228 waiting &= ~(1U << ch); 3229 } 3230 retry--; 3231 } while (waiting && (retry > 0)); 3232 if (retry == 0) { 3233 err = 1; 3234 } 3235 3236 dsb_sev(); 3237 /* set EXIT -> OP_DONE is cleared */ 3238 ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); 3239 dsb_sev(); 3240 3241 return err; 3242 } 3243 3244 /* WDQ TRAINING */ 3245 #ifndef DDR_FAST_INIT 3246 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) 3247 { 3248 int32_t i, k; 3249 uint32_t cs, slice; 3250 uint32_t data_l; 3251 3252 /* clr of training results buffer */ 3253 cs = ddr_csn % 2; 3254 data_l = board_cnf->dqdm_dly_w; 3255 for (slice = 0; slice < SLICE_CNT; slice++) { 3256 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3257 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3258 continue; 3259 3260 for (i = 0; i <= 8; i++) { 3261 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) 3262 wdqdm_dly[ch][cs][slice][i] = 3263 wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; 3264 else 3265 wdqdm_dly[ch][cs][slice][i] = data_l; 3266 wdqdm_le[ch][cs][slice][i] = 0; 3267 wdqdm_te[ch][cs][slice][i] = 0; 3268 } 3269 wdqdm_st[ch][cs][slice] = 0; 3270 wdqdm_win[ch][cs][slice] = 0; 3271 } 3272 } 3273 3274 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) 3275 { 3276 int32_t i, k; 3277 uint32_t cs, slice; 3278 uint32_t data_l; 3279 uint32_t err; 3280 const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; 3281 3282 int32_t min_win; 3283 int32_t win; 3284 int8_t _adj; 3285 int16_t adj; 3286 uint32_t dq; 3287 3288 /* analysis of training results */ 3289 err = 0; 3290 for (slice = 0; slice < SLICE_CNT; slice += 1) { 3291 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3292 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3293 continue; 3294 3295 cs = ddr_csn % 2; 3296 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); 3297 for (i = 0; i < 9; i++) { 3298 dq = slice * 8 + i; 3299 if (i == 8) 3300 _adj = board_cnf->ch[ch].dm_adj_w[slice]; 3301 else 3302 _adj = board_cnf->ch[ch].dq_adj_w[dq]; 3303 adj = _f_scale_adj(_adj); 3304 3305 data_l = 3306 ddr_getval_s(ch, slice, 3307 _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; 3308 ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], 3309 data_l); 3310 wdqdm_dly[ch][cs][slice][i] = data_l; 3311 } 3312 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); 3313 data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); 3314 wdqdm_st[ch][cs][slice] = data_l; 3315 min_win = INT_LEAST32_MAX; 3316 for (i = 0; i <= 8; i++) { 3317 ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, 3318 i); 3319 3320 data_l = 3321 ddr_getval_s(ch, slice, 3322 _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); 3323 wdqdm_te[ch][cs][slice][i] = data_l; 3324 data_l = 3325 ddr_getval_s(ch, slice, 3326 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); 3327 wdqdm_le[ch][cs][slice][i] = data_l; 3328 win = 3329 (int32_t)wdqdm_te[ch][cs][slice][i] - 3330 wdqdm_le[ch][cs][slice][i]; 3331 if (min_win > win) 3332 min_win = win; 3333 if (data_l >= _par_WDQLVL_RETRY_THRES) 3334 err = 2; 3335 } 3336 wdqdm_win[ch][cs][slice] = min_win; 3337 if ((prr_product == PRR_PRODUCT_H3) && 3338 (prr_cut <= PRR_PRODUCT_11)) { 3339 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 3340 0x01); 3341 } else { 3342 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 3343 ((ch_have_this_cs[1]) >> ch) & 0x01); 3344 } 3345 } 3346 return err; 3347 } 3348 #endif/* DDR_FAST_INIT */ 3349 3350 static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) 3351 { 3352 uint32_t i; 3353 uint32_t ch, slice; 3354 uint32_t tgt_cs, src_cs; 3355 uint32_t tmp_r; 3356 3357 /* copy of training results */ 3358 foreach_vch(ch) { 3359 for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { 3360 for (slice = 0; slice < SLICE_CNT; slice++) { 3361 ddr_setval_s(ch, slice, 3362 _reg_PHY_PER_CS_TRAINING_INDEX, 3363 tgt_cs); 3364 src_cs = ddr_csn % 2; 3365 if (!(ch_have_this_cs[1] & (1U << ch))) 3366 src_cs = 0; 3367 for (i = 0; i <= 4; i += 4) { 3368 if (restore) 3369 tmp_r = 3370 rdqdm_dly[ch][tgt_cs][slice] 3371 [i]; 3372 else 3373 tmp_r = 3374 rdqdm_dly[ch][src_cs][slice] 3375 [i]; 3376 3377 ddr_setval_s(ch, slice, 3378 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 3379 [i], tmp_r); 3380 } 3381 } 3382 } 3383 } 3384 } 3385 3386 static uint32_t wdqdm_man1(void) 3387 { 3388 int32_t k; 3389 uint32_t ch, cs, slice; 3390 uint32_t ddr_csn; 3391 uint32_t data_l; 3392 uint32_t err; 3393 uint32_t high_dq[DRAM_CH_CNT]; 3394 uint32_t mr14_csab0_bak[DRAM_CH_CNT]; 3395 #ifndef DDR_FAST_INIT 3396 uint32_t err_flg; 3397 #endif/* DDR_FAST_INIT */ 3398 3399 /* manual execution of training */ 3400 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3401 foreach_vch(ch) { 3402 high_dq[ch] = 0; 3403 for (slice = 0; slice < SLICE_CNT; slice++) { 3404 k = (board_cnf->ch[ch].dqs_swap >> 3405 (4 * slice)) & 0x0f; 3406 if (k >= 2) 3407 high_dq[ch] |= (1U << slice); 3408 } 3409 ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00); 3410 } 3411 } 3412 err = 0; 3413 /* CLEAR PREV RESULT */ 3414 for (cs = 0; cs < CS_CNT; cs++) { 3415 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); 3416 if (((prr_product == PRR_PRODUCT_H3) && 3417 (prr_cut > PRR_PRODUCT_11)) || 3418 (prr_product == PRR_PRODUCT_M3N) || 3419 (prr_product == PRR_PRODUCT_V3H)) { 3420 ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 3421 0x01); 3422 } else { 3423 ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 3424 0x01); 3425 } 3426 } 3427 ddrphy_regif_idle(); 3428 3429 #ifndef DDR_FAST_INIT 3430 err_flg = 0; 3431 #endif/* DDR_FAST_INIT */ 3432 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3433 if ((prr_product == PRR_PRODUCT_H3) && 3434 (prr_cut <= PRR_PRODUCT_11)) { 3435 foreach_vch(ch) { 3436 data_l = mmio_read_32(DBSC_DBDFICNT(ch)); 3437 data_l &= ~(0x00ffU << 16); 3438 3439 if (ddr_csn >= 2) 3440 k = (high_dq[ch] ^ 0x0f); 3441 else 3442 k = high_dq[ch]; 3443 data_l |= (k << 16); 3444 mmio_write_32(DBSC_DBDFICNT(ch), data_l); 3445 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); 3446 } 3447 } 3448 if (((prr_product == PRR_PRODUCT_H3) && 3449 (prr_cut <= PRR_PRODUCT_11)) || 3450 ((prr_product == PRR_PRODUCT_M3) && 3451 (prr_cut == PRR_PRODUCT_10))) { 3452 wdqdm_cp(ddr_csn, 0); 3453 } 3454 3455 foreach_vch(ch) { 3456 data_l = 3457 ddr_getval(ch, 3458 reg_pi_mr14_data_fx_csx[1][ddr_csn]); 3459 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l); 3460 } 3461 3462 /* KICK WDQLVL */ 3463 err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); 3464 if (err) 3465 goto err_exit; 3466 3467 if (ddr_csn == 0) 3468 foreach_vch(ch) { 3469 mr14_csab0_bak[ch] = 3470 ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]); 3471 } else 3472 foreach_vch(ch) { 3473 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], 3474 mr14_csab0_bak[ch]); 3475 } 3476 #ifndef DDR_FAST_INIT 3477 foreach_vch(ch) { 3478 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { 3479 wdqdm_clr1(ch, ddr_csn); 3480 continue; 3481 } 3482 err = wdqdm_ana1(ch, ddr_csn); 3483 if (err) 3484 err_flg |= (1U << (ddr_csn * 4 + ch)); 3485 ddrphy_regif_idle(); 3486 } 3487 #endif/* DDR_FAST_INIT */ 3488 } 3489 err_exit: 3490 #ifndef DDR_FAST_INIT 3491 err |= err_flg; 3492 #endif/* DDR_FAST_INIT */ 3493 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3494 ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); 3495 foreach_vch(ch) { 3496 data_l = mmio_read_32(DBSC_DBDFICNT(ch)); 3497 data_l &= ~(0x00ffU << 16); 3498 mmio_write_32(DBSC_DBDFICNT(ch), data_l); 3499 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); 3500 } 3501 } 3502 return err; 3503 } 3504 3505 static uint32_t wdqdm_man(void) 3506 { 3507 uint32_t err, retry_cnt; 3508 const uint32_t retry_max = 0x10; 3509 uint32_t datal, ch, ddr_csn, mr14_bkup[4][4]; 3510 3511 datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19; 3512 if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal) 3513 datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF; 3514 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal); 3515 3516 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 3517 (prr_product == PRR_PRODUCT_M3N) || 3518 (prr_product == PRR_PRODUCT_V3H)) { 3519 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, 3520 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3521 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, 3522 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3523 } else { 3524 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, 3525 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3526 } 3527 ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); 3528 ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); 3529 3530 retry_cnt = 0; 3531 err = 0; 3532 do { 3533 if ((prr_product == PRR_PRODUCT_H3) && 3534 (prr_cut <= PRR_PRODUCT_11)) { 3535 err = wdqdm_man1(); 3536 } else { 3537 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); 3538 ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 3539 0x01); 3540 if ((prr_product == PRR_PRODUCT_M3N) || 3541 (prr_product == PRR_PRODUCT_V3H)) { 3542 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3543 0x0C); 3544 } else { 3545 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); 3546 } 3547 dsb_sev(); 3548 err = wdqdm_man1(); 3549 foreach_vch(ch) { 3550 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3551 mr14_bkup[ch][ddr_csn] = 3552 ddr_getval(ch, 3553 reg_pi_mr14_data_fx_csx 3554 [1][ddr_csn]); 3555 dsb_sev(); 3556 } 3557 } 3558 3559 if ((prr_product == PRR_PRODUCT_M3N) || 3560 (prr_product == PRR_PRODUCT_V3H)) { 3561 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3562 0x04); 3563 } else { 3564 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); 3565 } 3566 pvtcode_update(); 3567 err = wdqdm_man1(); 3568 foreach_vch(ch) { 3569 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3570 mr14_bkup[ch][ddr_csn] = 3571 (mr14_bkup[ch][ddr_csn] + 3572 ddr_getval(ch, 3573 reg_pi_mr14_data_fx_csx 3574 [1][ddr_csn])) / 2; 3575 ddr_setval(ch, 3576 reg_pi_mr14_data_fx_csx[1] 3577 [ddr_csn], 3578 mr14_bkup[ch][ddr_csn]); 3579 } 3580 } 3581 3582 ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 3583 0x00); 3584 if ((prr_product == PRR_PRODUCT_M3N) || 3585 (prr_product == PRR_PRODUCT_V3H)) { 3586 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3587 0x00); 3588 ddr_setval_ach 3589 (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, 3590 0x00); 3591 ddr_setval_ach 3592 (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, 3593 0x00); 3594 } else { 3595 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); 3596 ddr_setval_ach 3597 (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 3598 0x00); 3599 ddr_setval_ach 3600 (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 3601 0x00); 3602 } 3603 ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 3604 0x00); 3605 3606 pvtcode_update2(); 3607 err = wdqdm_man1(); 3608 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); 3609 } 3610 } while (err && (++retry_cnt < retry_max)); 3611 3612 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 3613 ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { 3614 wdqdm_cp(0, 1); 3615 } 3616 3617 return (retry_cnt >= retry_max); 3618 } 3619 3620 /* RDQ TRAINING */ 3621 #ifndef DDR_FAST_INIT 3622 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) 3623 { 3624 int32_t i, k; 3625 uint32_t cs, slice; 3626 uint32_t data_l; 3627 3628 /* clr of training results buffer */ 3629 cs = ddr_csn % 2; 3630 data_l = board_cnf->dqdm_dly_r; 3631 for (slice = 0; slice < SLICE_CNT; slice++) { 3632 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3633 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3634 continue; 3635 3636 for (i = 0; i <= 8; i++) { 3637 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) { 3638 rdqdm_dly[ch][cs][slice][i] = 3639 rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; 3640 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = 3641 rdqdm_dly[ch][CS_CNT - 1 - cs][slice + 3642 SLICE_CNT] 3643 [i]; 3644 } else { 3645 rdqdm_dly[ch][cs][slice][i] = data_l; 3646 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = 3647 data_l; 3648 } 3649 rdqdm_le[ch][cs][slice][i] = 0; 3650 rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; 3651 rdqdm_te[ch][cs][slice][i] = 0; 3652 rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; 3653 rdqdm_nw[ch][cs][slice][i] = 0; 3654 rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; 3655 } 3656 rdqdm_st[ch][cs][slice] = 0; 3657 rdqdm_win[ch][cs][slice] = 0; 3658 } 3659 } 3660 3661 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) 3662 { 3663 int32_t i, k; 3664 uint32_t cs, slice; 3665 uint32_t data_l; 3666 uint32_t err; 3667 int8_t _adj; 3668 int16_t adj; 3669 uint32_t dq; 3670 int32_t min_win; 3671 int32_t win; 3672 uint32_t rdq_status_obs_select; 3673 3674 /* analysis of training results */ 3675 err = 0; 3676 for (slice = 0; slice < SLICE_CNT; slice++) { 3677 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3678 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3679 continue; 3680 3681 cs = ddr_csn % 2; 3682 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); 3683 ddrphy_regif_idle(); 3684 3685 ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); 3686 ddrphy_regif_idle(); 3687 3688 for (i = 0; i <= 8; i++) { 3689 dq = slice * 8 + i; 3690 if (i == 8) 3691 _adj = board_cnf->ch[ch].dm_adj_r[slice]; 3692 else 3693 _adj = board_cnf->ch[ch].dq_adj_r[dq]; 3694 3695 adj = _f_scale_adj(_adj); 3696 3697 data_l = 3698 ddr_getval_s(ch, slice, 3699 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + 3700 adj; 3701 ddr_setval_s(ch, slice, 3702 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], 3703 data_l); 3704 rdqdm_dly[ch][cs][slice][i] = data_l; 3705 3706 data_l = 3707 ddr_getval_s(ch, slice, 3708 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + 3709 adj; 3710 ddr_setval_s(ch, slice, 3711 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], 3712 data_l); 3713 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; 3714 } 3715 min_win = INT_LEAST32_MAX; 3716 for (i = 0; i <= 8; i++) { 3717 data_l = 3718 ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); 3719 rdqdm_st[ch][cs][slice] = data_l; 3720 rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l; 3721 /* k : rise/fall */ 3722 for (k = 0; k < 2; k++) { 3723 if (i == 8) { 3724 rdq_status_obs_select = 16 + 8 * k; 3725 } else { 3726 rdq_status_obs_select = i + k * 8; 3727 } 3728 ddr_setval_s(ch, slice, 3729 _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, 3730 rdq_status_obs_select); 3731 3732 data_l = 3733 ddr_getval_s(ch, slice, 3734 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); 3735 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = 3736 data_l; 3737 3738 data_l = 3739 ddr_getval_s(ch, slice, 3740 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); 3741 rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = 3742 data_l; 3743 3744 data_l = 3745 ddr_getval_s(ch, slice, 3746 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); 3747 rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = 3748 data_l; 3749 3750 win = 3751 (int32_t)rdqdm_te[ch][cs][slice + 3752 SLICE_CNT * 3753 k][i] - 3754 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; 3755 if (i != 8) { 3756 if (min_win > win) 3757 min_win = win; 3758 } 3759 } 3760 } 3761 rdqdm_win[ch][cs][slice] = min_win; 3762 if (min_win <= 0) { 3763 err = 2; 3764 } 3765 } 3766 return err; 3767 } 3768 #endif/* DDR_FAST_INIT */ 3769 3770 static uint32_t rdqdm_man1(void) 3771 { 3772 uint32_t ch; 3773 uint32_t ddr_csn; 3774 #ifdef DDR_FAST_INIT 3775 uint32_t slice; 3776 uint32_t i, adj, data_l; 3777 #endif/* DDR_FAST_INIT */ 3778 uint32_t err; 3779 3780 /* manual execution of training */ 3781 err = 0; 3782 3783 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3784 /* KICK RDQLVL */ 3785 err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); 3786 if (err) 3787 goto err_exit; 3788 #ifndef DDR_FAST_INIT 3789 foreach_vch(ch) { 3790 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { 3791 rdqdm_clr1(ch, ddr_csn); 3792 ddrphy_regif_idle(); 3793 continue; 3794 } 3795 err = rdqdm_ana1(ch, ddr_csn); 3796 ddrphy_regif_idle(); 3797 if (err) 3798 goto err_exit; 3799 } 3800 #else/* DDR_FAST_INIT */ 3801 foreach_vch(ch) { 3802 if (ch_have_this_cs[ddr_csn] & (1U << ch)) { 3803 for (slice = 0; slice < SLICE_CNT; slice++) { 3804 if (ddr_getval_s(ch, slice, 3805 _reg_PHY_RDLVL_STATUS_OBS) != 3806 0x0D00FFFF) { 3807 err = (1U << ch) | 3808 (0x10U << slice); 3809 goto err_exit; 3810 } 3811 } 3812 } 3813 if (((prr_product == PRR_PRODUCT_H3) && 3814 (prr_cut <= PRR_PRODUCT_11)) || 3815 ((prr_product == PRR_PRODUCT_M3) && 3816 (prr_cut <= PRR_PRODUCT_10))) { 3817 for (slice = 0; slice < SLICE_CNT; slice++) { 3818 for (i = 0; i <= 8; i++) { 3819 if (i == 8) 3820 adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]); 3821 else 3822 adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]); 3823 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); 3824 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; 3825 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l); 3826 rdqdm_dly[ch][ddr_csn][slice][i] = data_l; 3827 rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l; 3828 3829 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; 3830 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l); 3831 rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l; 3832 rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l; 3833 } 3834 } 3835 } 3836 } 3837 ddrphy_regif_idle(); 3838 3839 #endif/* DDR_FAST_INIT */ 3840 } 3841 3842 err_exit: 3843 return err; 3844 } 3845 3846 static uint32_t rdqdm_man(void) 3847 { 3848 uint32_t err, retry_cnt; 3849 const uint32_t retry_max = 0x01; 3850 3851 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, 3852 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3853 _reg_PHY_DQ_TSEL_ENABLE)); 3854 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, 3855 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3856 _reg_PHY_DQS_TSEL_ENABLE)); 3857 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, 3858 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3859 _reg_PHY_DQ_TSEL_SELECT)); 3860 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, 3861 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3862 _reg_PHY_DQS_TSEL_SELECT)); 3863 3864 retry_cnt = 0; 3865 do { 3866 err = rdqdm_man1(); 3867 ddrphy_regif_idle(); 3868 } while (err && (++retry_cnt < retry_max)); 3869 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, 3870 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3871 _reg_PHY_DQ_TSEL_ENABLE)); 3872 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, 3873 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3874 _reg_PHY_DQS_TSEL_ENABLE)); 3875 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, 3876 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3877 _reg_PHY_DQ_TSEL_SELECT)); 3878 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, 3879 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3880 _reg_PHY_DQS_TSEL_SELECT)); 3881 3882 return (retry_cnt >= retry_max); 3883 } 3884 3885 /* rx offset calibration */ 3886 static int32_t _find_change(uint64_t val, uint32_t dir) 3887 { 3888 int32_t i; 3889 uint32_t startval; 3890 uint32_t curval; 3891 const int32_t VAL_END = 0x3f; 3892 3893 if (dir == 0) { 3894 startval = (val & 0x01); 3895 for (i = 1; i <= VAL_END; i++) { 3896 curval = (val >> i) & 0x01; 3897 if (curval != startval) 3898 return i; 3899 } 3900 return VAL_END; 3901 } 3902 3903 startval = (val >> dir) & 0x01; 3904 for (i = dir - 1; i >= 0; i--) { 3905 curval = (val >> i) & 0x01; 3906 if (curval != startval) 3907 return i; 3908 } 3909 return 0; 3910 } 3911 3912 static uint32_t _rx_offset_cal_updn(uint32_t code) 3913 { 3914 const uint32_t CODE_MAX = 0x40; 3915 uint32_t tmp; 3916 3917 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3918 if (code == 0) 3919 tmp = (1U << 6) | (CODE_MAX - 1); 3920 else if (code <= 0x20) 3921 tmp = 3922 ((CODE_MAX - 1 - 3923 (0x20 - code) * 2) << 6) | (CODE_MAX - 1); 3924 else 3925 tmp = 3926 ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 - 3927 (code - 0x20) * 2); 3928 } else { 3929 if (code == 0) 3930 tmp = (1U << 6) | (CODE_MAX - 1); 3931 else 3932 tmp = (code << 6) | (CODE_MAX - code); 3933 } 3934 return tmp; 3935 } 3936 3937 static uint32_t rx_offset_cal(void) 3938 { 3939 uint32_t index; 3940 uint32_t code; 3941 const uint32_t CODE_MAX = 0x40; 3942 const uint32_t CODE_STEP = 2; 3943 uint32_t ch, slice; 3944 uint32_t tmp; 3945 uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; 3946 uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; 3947 uint64_t tmpval; 3948 int32_t lsb, msb; 3949 3950 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); 3951 foreach_vch(ch) { 3952 for (slice = 0; slice < SLICE_CNT; slice++) { 3953 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) 3954 val[ch][slice][index] = 0; 3955 } 3956 } 3957 3958 for (code = 0; code < CODE_MAX / CODE_STEP; code++) { 3959 tmp = _rx_offset_cal_updn(code * CODE_STEP); 3960 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { 3961 ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); 3962 } 3963 dsb_sev(); 3964 ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); 3965 3966 foreach_vch(ch) { 3967 for (slice = 0; slice < SLICE_CNT; slice++) { 3968 tmp = tmp_ach_as[ch][slice]; 3969 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; 3970 index++) { 3971 if (tmp & (1U << index)) { 3972 val[ch][slice][index] |= 3973 (1ULL << code); 3974 } else { 3975 val[ch][slice][index] &= 3976 ~(1ULL << code); 3977 } 3978 } 3979 } 3980 } 3981 } 3982 foreach_vch(ch) { 3983 for (slice = 0; slice < SLICE_CNT; slice++) { 3984 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; 3985 index++) { 3986 tmpval = val[ch][slice][index]; 3987 lsb = _find_change(tmpval, 0); 3988 msb = 3989 _find_change(tmpval, 3990 (CODE_MAX / CODE_STEP) - 1); 3991 tmp = (lsb + msb) >> 1; 3992 3993 tmp = _rx_offset_cal_updn(tmp * CODE_STEP); 3994 ddr_setval_s(ch, slice, 3995 _reg_PHY_RX_CAL_X[index], tmp); 3996 } 3997 } 3998 } 3999 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); 4000 4001 return 0; 4002 } 4003 4004 static uint32_t rx_offset_cal_hw(void) 4005 { 4006 uint32_t ch, slice; 4007 uint32_t retry; 4008 uint32_t complete; 4009 uint32_t tmp; 4010 uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; 4011 4012 ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); 4013 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); 4014 ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); 4015 4016 retry = 0; 4017 while (retry < 4096) { 4018 if ((retry & 0xff) == 0) { 4019 ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); 4020 } 4021 foreach_vch(ch) 4022 for (slice = 0; slice < SLICE_CNT; slice++) 4023 tmp_ach_as[ch][slice] = 4024 ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); 4025 4026 complete = 1; 4027 foreach_vch(ch) { 4028 for (slice = 0; slice < SLICE_CNT; slice++) { 4029 tmp = tmp_ach_as[ch][slice]; 4030 tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); 4031 if (((prr_product == PRR_PRODUCT_H3) && 4032 (prr_cut > PRR_PRODUCT_11)) || 4033 (prr_product == PRR_PRODUCT_M3N) || 4034 (prr_product == PRR_PRODUCT_V3H)) { 4035 if (tmp != 0x3E) 4036 complete = 0; 4037 } else { 4038 if (tmp != 0x40) 4039 complete = 0; 4040 } 4041 } 4042 } 4043 if (complete) 4044 break; 4045 4046 retry++; 4047 } 4048 4049 return (complete == 0); 4050 } 4051 4052 /* adjust rddqs latency */ 4053 static void adjust_rddqs_latency(void) 4054 { 4055 uint32_t ch, slice; 4056 uint32_t dly; 4057 uint32_t maxlatx2; 4058 uint32_t tmp; 4059 uint32_t rdlat_adjx2[SLICE_CNT]; 4060 4061 foreach_vch(ch) { 4062 maxlatx2 = 0; 4063 for (slice = 0; slice < SLICE_CNT; slice++) { 4064 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, 4065 0x00); 4066 4067 dly = 4068 ddr_getval_s(ch, slice, 4069 _reg_PHY_RDDQS_GATE_SLAVE_DELAY); 4070 tmp = 4071 ddr_getval_s(ch, slice, 4072 _reg_PHY_RDDQS_LATENCY_ADJUST); 4073 /* note gate_slave_delay[9] is always 0 */ 4074 tmp = (tmp << 1) + (dly >> 8); 4075 rdlat_adjx2[slice] = tmp; 4076 if (maxlatx2 < tmp) 4077 maxlatx2 = tmp; 4078 } 4079 maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; 4080 for (slice = 0; slice < SLICE_CNT; slice++) { 4081 tmp = maxlatx2 - rdlat_adjx2[slice]; 4082 tmp = (tmp >> 1); 4083 if (tmp) { 4084 ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, 4085 ddr_getval_s(ch, slice, 4086 _reg_PHY_RPTR_UPDATE) 4087 + 1); 4088 } 4089 } 4090 } 4091 } 4092 4093 /* adjust wpath latency */ 4094 static void adjust_wpath_latency(void) 4095 { 4096 uint32_t ch, cs, slice; 4097 uint32_t dly; 4098 uint32_t wpath_add; 4099 const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; 4100 4101 foreach_vch(ch) { 4102 for (slice = 0; slice < SLICE_CNT; slice += 1) { 4103 for (cs = 0; cs < CS_CNT; cs++) { 4104 ddr_setval_s(ch, slice, 4105 _reg_PHY_PER_CS_TRAINING_INDEX, 4106 cs); 4107 ddr_getval_s(ch, slice, 4108 _reg_PHY_PER_CS_TRAINING_INDEX); 4109 dly = 4110 ddr_getval_s(ch, slice, 4111 _reg_PHY_CLK_WRDQS_SLAVE_DELAY); 4112 if (dly <= _par_EARLY_THRESHOLD_VAL) 4113 continue; 4114 4115 wpath_add = 4116 ddr_getval_s(ch, slice, 4117 _reg_PHY_WRITE_PATH_LAT_ADD); 4118 ddr_setval_s(ch, slice, 4119 _reg_PHY_WRITE_PATH_LAT_ADD, 4120 wpath_add - 1); 4121 } 4122 } 4123 } 4124 } 4125 4126 /* DDR Initialize entry */ 4127 int32_t rcar_dram_init(void) 4128 { 4129 uint32_t ch, cs; 4130 uint32_t data_l; 4131 uint32_t bus_mbps, bus_mbpsdiv; 4132 uint32_t tmp_tccd; 4133 uint32_t failcount; 4134 uint32_t cnf_boardtype; 4135 4136 /* Thermal sensor setting */ 4137 data_l = mmio_read_32(CPG_MSTPSR5); 4138 if (data_l & BIT(22)) { /* case THS/TSC Standby */ 4139 data_l &= ~BIT(22); 4140 cpg_write_32(CPG_SMSTPCR5, data_l); 4141 while (mmio_read_32(CPG_MSTPSR5) & BIT(22)) 4142 ; /* wait bit=0 */ 4143 } 4144 4145 /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ 4146 data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; 4147 mmio_write_32(THS1_THCTR, data_l); 4148 4149 /* Judge product and cut */ 4150 #ifdef RCAR_DDR_FIXED_LSI_TYPE 4151 #if (RCAR_LSI == RCAR_AUTO) 4152 prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; 4153 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4154 #else /* RCAR_LSI */ 4155 #ifndef RCAR_LSI_CUT 4156 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4157 #endif /* RCAR_LSI_CUT */ 4158 #endif /* RCAR_LSI */ 4159 #else /* RCAR_DDR_FIXED_LSI_TYPE */ 4160 prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; 4161 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4162 #endif /* RCAR_DDR_FIXED_LSI_TYPE */ 4163 4164 if (prr_product == PRR_PRODUCT_H3) { 4165 if (prr_cut <= PRR_PRODUCT_11) { 4166 p_ddr_regdef_tbl = 4167 (const uint32_t *)&DDR_REGDEF_TBL[0][0]; 4168 } else { 4169 p_ddr_regdef_tbl = 4170 (const uint32_t *)&DDR_REGDEF_TBL[2][0]; 4171 } 4172 } else if (prr_product == PRR_PRODUCT_M3) { 4173 p_ddr_regdef_tbl = 4174 (const uint32_t *)&DDR_REGDEF_TBL[1][0]; 4175 } else if ((prr_product == PRR_PRODUCT_M3N) || 4176 (prr_product == PRR_PRODUCT_V3H)) { 4177 p_ddr_regdef_tbl = 4178 (const uint32_t *)&DDR_REGDEF_TBL[3][0]; 4179 } else { 4180 FATAL_MSG("BL2: DDR:Unknown Product\n"); 4181 return 0xff; 4182 } 4183 4184 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 4185 ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { 4186 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 4187 } else { 4188 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); 4189 } 4190 4191 /* Judge board type */ 4192 cnf_boardtype = boardcnf_get_brd_type(); 4193 if (cnf_boardtype >= BOARDNUM) { 4194 FATAL_MSG("BL2: DDR:Unknown Board\n"); 4195 return 0xff; 4196 } 4197 board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype]; 4198 4199 /* RCAR_DRAM_SPLIT_2CH (2U) */ 4200 #if RCAR_DRAM_SPLIT == 2 4201 /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */ 4202 if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { 4203 mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); 4204 ddr_phyvalid = 0x03; 4205 } else { 4206 ddr_phyvalid = board_cnf->phyvalid; 4207 } 4208 #else /* RCAR_DRAM_SPLIT_2CH */ 4209 ddr_phyvalid = board_cnf->phyvalid; 4210 #endif /* RCAR_DRAM_SPLIT_2CH */ 4211 4212 max_density = 0; 4213 4214 for (cs = 0; cs < CS_CNT; cs++) { 4215 ch_have_this_cs[cs] = 0; 4216 } 4217 4218 foreach_ech(ch) 4219 for (cs = 0; cs < CS_CNT; cs++) 4220 ddr_density[ch][cs] = 0xff; 4221 4222 foreach_vch(ch) { 4223 for (cs = 0; cs < CS_CNT; cs++) { 4224 data_l = board_cnf->ch[ch].ddr_density[cs]; 4225 ddr_density[ch][cs] = data_l; 4226 4227 if (data_l == 0xff) 4228 continue; 4229 if (data_l > max_density) 4230 max_density = data_l; 4231 if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) && 4232 (prr_cut <= PRR_PRODUCT_11)) 4233 continue; 4234 ch_have_this_cs[cs] |= (1U << ch); 4235 } 4236 } 4237 4238 /* Judge board clock frequency (in MHz) */ 4239 boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); 4240 if ((brd_clk / brd_clkdiv) > 25) { 4241 brd_clkdiva = 1; 4242 } else { 4243 brd_clkdiva = 0; 4244 } 4245 4246 /* Judge ddr operating frequency clock(in Mbps) */ 4247 boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); 4248 4249 ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); 4250 4251 ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, 4252 brd_clkdiv * (brd_clkdiva + 1)); 4253 4254 /* Adjust tccd */ 4255 data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; 4256 bus_mbps = 0; 4257 bus_mbpsdiv = 0; 4258 switch (data_l) { 4259 case 0: 4260 bus_mbps = brd_clk * 0x60 * 2; 4261 bus_mbpsdiv = brd_clkdiv * 1; 4262 break; 4263 case 1: 4264 bus_mbps = brd_clk * 0x50 * 2; 4265 bus_mbpsdiv = brd_clkdiv * 1; 4266 break; 4267 case 2: 4268 bus_mbps = brd_clk * 0x40 * 2; 4269 bus_mbpsdiv = brd_clkdiv * 1; 4270 break; 4271 case 3: 4272 bus_mbps = brd_clk * 0x60 * 2; 4273 bus_mbpsdiv = brd_clkdiv * 2; 4274 break; 4275 default: 4276 bus_mbps = brd_clk * 0x60 * 2; 4277 bus_mbpsdiv = brd_clkdiv * 2; 4278 break; 4279 } 4280 tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); 4281 if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) 4282 tmp_tccd = tmp_tccd + 1; 4283 4284 if (tmp_tccd < 8) 4285 ddr_tccd = 8; 4286 else 4287 ddr_tccd = tmp_tccd; 4288 4289 NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); 4290 4291 MSG_LF("Start\n"); 4292 4293 /* PLL Setting */ 4294 pll3_control(1); 4295 4296 /* initialize DDR */ 4297 data_l = init_ddr(); 4298 if (data_l == ddr_phyvalid) { 4299 failcount = 0; 4300 } else { 4301 failcount = 1; 4302 } 4303 4304 foreach_vch(ch) 4305 mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); 4306 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 4307 ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { 4308 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 4309 } else { 4310 mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); 4311 } 4312 4313 if (failcount == 0) { 4314 return INITDRAM_OK; 4315 } else { 4316 return INITDRAM_NG; 4317 } 4318 } 4319 4320 void pvtcode_update(void) 4321 { 4322 uint32_t ch; 4323 uint32_t data_l; 4324 uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; 4325 int32_t pvtp_tmp, pvtn_tmp; 4326 4327 foreach_vch(ch) { 4328 pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; 4329 pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; 4330 4331 if (8912 * pvtp_init > 44230) { 4332 pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; 4333 } else { 4334 pvtp_tmp = 4335 -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); 4336 } 4337 pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; 4338 4339 pvtn[ch] = pvtn_tmp + pvtn_init; 4340 pvtp[ch] = pvtp_tmp + pvtp_init; 4341 4342 if (pvtn[ch] > 63) { 4343 pvtn[ch] = 63; 4344 pvtp[ch] = 4345 (pvtp_tmp) * (63 - 6 * pvtn_tmp - 4346 pvtn_init) / (pvtn_tmp) + 4347 6 * pvtp_tmp + pvtp_init; 4348 } 4349 if ((prr_product == PRR_PRODUCT_H3) && 4350 (prr_cut <= PRR_PRODUCT_11)) { 4351 data_l = pvtp[ch] | (pvtn[ch] << 6) | 4352 (tcal.tcomp_cal[ch] & 0xfffff000); 4353 reg_ddrphy_write(ch, 4354 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4355 data_l | 0x00020000); 4356 reg_ddrphy_write(ch, 4357 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4358 data_l); 4359 reg_ddrphy_write(ch, 4360 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4361 data_l); 4362 reg_ddrphy_write(ch, 4363 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4364 data_l); 4365 reg_ddrphy_write(ch, 4366 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4367 data_l); 4368 } else { 4369 data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; 4370 reg_ddrphy_write(ch, 4371 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4372 data_l | 0x00020000); 4373 reg_ddrphy_write(ch, 4374 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4375 data_l); 4376 reg_ddrphy_write(ch, 4377 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4378 data_l); 4379 reg_ddrphy_write(ch, 4380 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4381 data_l); 4382 reg_ddrphy_write(ch, 4383 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4384 data_l); 4385 } 4386 } 4387 } 4388 4389 void pvtcode_update2(void) 4390 { 4391 uint32_t ch; 4392 4393 foreach_vch(ch) { 4394 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4395 tcal.init_cal[ch] | 0x00020000); 4396 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4397 tcal.init_cal[ch]); 4398 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4399 tcal.init_cal[ch]); 4400 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4401 tcal.init_cal[ch]); 4402 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4403 tcal.init_cal[ch]); 4404 } 4405 } 4406 4407 void ddr_padcal_tcompensate_getinit(uint32_t override) 4408 { 4409 uint32_t ch; 4410 uint32_t data_l; 4411 uint32_t pvtp, pvtn; 4412 4413 tcal.init_temp = 0; 4414 for (ch = 0; ch < 4; ch++) { 4415 tcal.init_cal[ch] = 0; 4416 tcal.tcomp_cal[ch] = 0; 4417 } 4418 4419 foreach_vch(ch) { 4420 tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); 4421 tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); 4422 } 4423 4424 if (!override) { 4425 data_l = mmio_read_32(THS1_TEMP); 4426 if (data_l < 2800) { 4427 tcal.init_temp = 4428 (143 * (int32_t)data_l - 359000) / 1000; 4429 } else { 4430 tcal.init_temp = 4431 (121 * (int32_t)data_l - 296300) / 1000; 4432 } 4433 4434 foreach_vch(ch) { 4435 pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; 4436 pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; 4437 if ((int32_t)pvtp > 4438 ((tcal.init_temp * 29 - 3625) / 1000)) 4439 pvtp = 4440 (int32_t)pvtp + 4441 ((3625 - tcal.init_temp * 29) / 1000); 4442 else 4443 pvtp = 0; 4444 4445 if ((int32_t)pvtn > 4446 ((tcal.init_temp * 54 - 6750) / 1000)) 4447 pvtn = 4448 (int32_t)pvtn + 4449 ((6750 - tcal.init_temp * 54) / 1000); 4450 else 4451 pvtn = 0; 4452 4453 if ((prr_product == PRR_PRODUCT_H3) && 4454 (prr_cut <= PRR_PRODUCT_11)) { 4455 tcal.init_cal[ch] = 4456 (tcal.init_cal[ch] & 0xfffff000) | 4457 (pvtn << 6) | 4458 pvtp; 4459 } else { 4460 tcal.init_cal[ch] = 4461 0x00015000 | (pvtn << 6) | pvtp; 4462 } 4463 } 4464 tcal.init_temp = 125; 4465 } 4466 } 4467 4468 #ifndef ddr_qos_init_setting 4469 /* For QoS init */ 4470 uint8_t get_boardcnf_phyvalid(void) 4471 { 4472 return ddr_phyvalid; 4473 } 4474 #endif /* ddr_qos_init_setting */ 4475