1 /* 2 * Copyright (c) 2015 - 2021, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/bl_common.h> 10 #include <common/debug.h> 11 #include <cortex_a72.h> 12 #include <drivers/arm/sp805.h> 13 #include <drivers/console.h> 14 #include <drivers/delay_timer.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/mmio.h> 17 #include <lib/utils_def.h> 18 #include <plat/common/common_def.h> 19 #include <plat/common/platform.h> 20 21 #include <bl33_info.h> 22 #include <chimp.h> 23 #include <cmn_plat_util.h> 24 #include <dmu.h> 25 #include <fsx.h> 26 #include <iommu.h> 27 #include <ncsi.h> 28 #include <paxb.h> 29 #include <paxc.h> 30 #include <platform_def.h> 31 #ifdef USE_USB 32 #include <platform_usb.h> 33 #endif 34 #include <sdio.h> 35 #include <sr_utils.h> 36 #include <timer_sync.h> 37 38 /******************************************************************************* 39 * Perform any BL3-1 platform setup common to ARM standard platforms 40 ******************************************************************************/ 41 42 static void brcm_stingray_gain_qspi_control(void) 43 { 44 if (boot_source_get() != BOOT_SOURCE_QSPI) { 45 if (bcm_chimp_is_nic_mode() && 46 (!bcm_chimp_handshake_done())) { 47 /* 48 * Last chance to wait for ChiMP firmware to report 49 * "I am done" before grabbing the QSPI 50 */ 51 WARN("ChiMP still not booted\n"); 52 #ifndef CHIMP_ALWAYS_NEEDS_QSPI 53 WARN("ChiMP is given the last chance to boot (%d s)\n", 54 CHIMP_HANDSHAKE_TIMEOUT_MS / 1000); 55 56 if (!bcm_chimp_wait_handshake()) { 57 ERROR("ChiMP failed to boot\n"); 58 } else { 59 INFO("ChiMP booted successfully\n"); 60 } 61 #endif 62 } 63 64 #ifndef CHIMP_ALWAYS_NEEDS_QSPI 65 INFO("AP grabs QSPI\n"); 66 /* 67 * For QSPI boot sbl/bl1 has already taken care. 68 * For other boot sources QSPI needs to be muxed to 69 * AP for exclusive use 70 */ 71 brcm_stingray_set_qspi_mux(1); 72 INFO("AP (bl31) gained control over QSPI\n"); 73 #endif 74 } 75 } 76 77 static void brcm_stingray_dma_pl330_init(void) 78 { 79 unsigned int val; 80 81 VERBOSE("dma pl330 init start\n"); 82 83 /* Set DMAC boot_manager_ns = 0x1 */ 84 VERBOSE(" - configure boot security state\n"); 85 mmio_setbits_32(DMAC_M0_IDM_IO_CONTROL_DIRECT, BOOT_MANAGER_NS); 86 /* Set boot_peripheral_ns[n:0] = 0xffffffff */ 87 mmio_write_32(ICFG_DMAC_CONFIG_2, BOOT_PERIPHERAL_NS); 88 /* Set boot_irq_ns[n:0] = 0x0000ffff */ 89 mmio_write_32(ICFG_DMAC_CONFIG_3, BOOT_IRQ_NS); 90 91 /* Set DMAC stream_id */ 92 VERBOSE(" - configure stream_id = 0x6000\n"); 93 val = (DMAC_STREAM_ID << DMAC_SID_SHIFT); 94 mmio_write_32(ICFG_DMAC_SID_ARADDR_CONTROL, val); 95 mmio_write_32(ICFG_DMAC_SID_AWADDR_CONTROL, val); 96 97 /* Reset DMAC */ 98 VERBOSE(" - reset dma pl330\n"); 99 100 mmio_setbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1); 101 udelay(500); 102 103 mmio_clrbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1); 104 udelay(500); 105 106 INFO("dma pl330 init done\n"); 107 } 108 109 static void brcm_stingray_spi_pl022_init(uintptr_t idm_reset_control) 110 { 111 VERBOSE("spi pl022 init start\n"); 112 113 /* Reset APB SPI bridge */ 114 VERBOSE(" - reset apb spi bridge\n"); 115 mmio_setbits_32(idm_reset_control, 0x1); 116 udelay(500); 117 118 mmio_clrbits_32(idm_reset_control, 0x1); 119 udelay(500); 120 121 INFO("spi pl022 init done\n"); 122 } 123 124 #define CDRU_SATA_RESET_N \ 125 BIT(CDRU_MISC_RESET_CONTROL__CDRU_SATA_RESET_N_R) 126 #define CDRU_MISC_CLK_SATA \ 127 BIT(CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SATA_CLK_EN_R) 128 #define CCN_CONFIG_CLK_ENABLE (1 << 2) 129 #define MMU_CONFIG_CLK_ENABLE (0x3F << 16) 130 131 #define SATA_SATA_TOP_CTRL_BUS_CTRL (SATA_BASE + 0x2044) 132 #define DMA_BIT_CTRL_MASK 0x003 133 #define DMA_DESCR_ENDIAN_CTRL (DMA_BIT_CTRL_MASK << 0x002) 134 #define DMA_DATA_ENDIAN_CTRL (DMA_BIT_CTRL_MASK << 0x004) 135 136 #define SATA_PORT_SATA3_PCB_REG8 (SATA_BASE + 0x2320) 137 #define SATA_PORT_SATA3_PCB_REG11 (SATA_BASE + 0x232c) 138 #define SATA_PORT_SATA3_PCB_BLOCK_ADDR (SATA_BASE + 0x233c) 139 140 #define SATA3_AFE_TXRX_ACTRL 0x1d0 141 /* TXDriver swing setting is 800mV */ 142 #define DFS_SWINGNOPE_VALUE (0x0 << 6) 143 #define DFS_SWINGNOPE_MASK (0x3 << 6) 144 145 #define DFS_SWINGPE_VALUE (0x1 << 4) 146 #define DFS_SWINGPE_MASK (0x3 << 4) 147 148 #define DFS_INJSTRENGTH_VALUE (0x0 << 4) 149 #define DFS_INJSTRENGTH_MASK (0x3 << 4) 150 151 #define DFS_INJEN (0x1 << 3) 152 153 #define SATA_CORE_MEM_CTRL (SATA_BASE + 0x3a08) 154 #define SATA_CORE_MEM_CTRL_ISO BIT(0) 155 #define SATA_CORE_MEM_CTRL_ARRPOWEROKIN BIT(1) 156 #define SATA_CORE_MEM_CTRL_ARRPOWERONIN BIT(2) 157 #define SATA_CORE_MEM_CTRL_POWEROKIN BIT(3) 158 #define SATA_CORE_MEM_CTRL_POWERONIN BIT(4) 159 160 #define SATA0_IDM_RESET_CONTROL (SATA_BASE + 0x500800) 161 #define SATA_APBT0_IDM_IO_CONTROL_DIRECT (SATA_BASE + 0x51a408) 162 #define IO_CONTROL_DIRECT_CLK_ENABLE BIT(0) 163 #define SATA_APBT0_IDM_RESET_CONTROL (SATA_BASE + 0x51a800) 164 #define IDM_RESET_CONTROL_RESET BIT(0) 165 166 #define NIC400_SATA_NOC_SECURITY1 0x6830000c 167 #define SATA_NOC_SECURITY1_FIELD 0xf 168 #define NIC400_SATA_NOC_SECURITY2 0x68300010 169 #define SATA_NOC_SECURITY2_FIELD 0xf 170 #define NIC400_SATA_NOC_SECURITY3 0x68300014 171 #define SATA_NOC_SECURITY3_FIELD 0x1 172 #define NIC400_SATA_NOC_SECURITY4 0x68300018 173 #define SATA_NOC_SECURITY4_FIELD 0x1 174 #define NIC400_SATA_NOC_SECURITY5 0x6830001c 175 #define SATA_NOC_SECURITY5_FIELD 0xf 176 #define NIC400_SATA_NOC_SECURITY6 0x68300020 177 #define SATA_NOC_SECURITY6_FIELD 0x1 178 #define NIC400_SATA_NOC_SECURITY7 0x68300024 179 #define SATA_NOC_SECURITY7_FIELD 0xf 180 #define NIC400_SATA_NOC_SECURITY8 0x68300028 181 #define SATA_NOC_SECURITY8_FIELD 0xf 182 #define NIC400_SATA_NOC_SECURITY9 0x6830002c 183 #define SATA_NOC_SECURITY9_FIELD 0x1 184 185 #define SATA_APBT_IDM_PORT_REG(port, reg) \ 186 (((port/4) << 12) + reg) 187 188 #define SATA_IDM_PORT_REG(port, reg) ((port << 12) + reg) 189 190 #define SATA_PORT_REG(port, reg) \ 191 (((port%4) << 16) + ((port/4) << 20) + reg) 192 193 #define MAX_SATA_PORTS 8 194 #define USE_SATA_PORTS 8 195 196 #ifdef USE_SATA 197 static const uint8_t sr_b0_sata_port[MAX_SATA_PORTS] = { 198 0, 1, 2, 3, 4, 5, 6, 7 199 }; 200 201 static uint32_t brcm_stingray_get_sata_port(unsigned int port) 202 { 203 return sr_b0_sata_port[port]; 204 } 205 206 static void brcm_stingray_sata_init(void) 207 { 208 unsigned int port = 0; 209 uint32_t sata_port; 210 211 mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL, 212 CDRU_MISC_CLK_SATA); 213 214 mmio_clrbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N); 215 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N); 216 217 for (port = 0; port < USE_SATA_PORTS; port++) { 218 219 sata_port = brcm_stingray_get_sata_port(port); 220 mmio_write_32(SATA_APBT_IDM_PORT_REG(sata_port, 221 SATA_APBT0_IDM_RESET_CONTROL), 222 0x0); 223 mmio_setbits_32(SATA_APBT_IDM_PORT_REG(sata_port, 224 SATA_APBT0_IDM_IO_CONTROL_DIRECT), 225 IO_CONTROL_DIRECT_CLK_ENABLE); 226 mmio_write_32(SATA_IDM_PORT_REG(sata_port, 227 SATA0_IDM_RESET_CONTROL), 228 0x0); 229 230 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), 231 SATA_CORE_MEM_CTRL_ARRPOWERONIN); 232 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), 233 SATA_CORE_MEM_CTRL_ARRPOWEROKIN); 234 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), 235 SATA_CORE_MEM_CTRL_POWERONIN); 236 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), 237 SATA_CORE_MEM_CTRL_POWEROKIN); 238 mmio_clrbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), 239 SATA_CORE_MEM_CTRL_ISO); 240 241 mmio_clrbits_32(SATA_PORT_REG(sata_port, 242 SATA_SATA_TOP_CTRL_BUS_CTRL), 243 (DMA_DESCR_ENDIAN_CTRL | DMA_DATA_ENDIAN_CTRL)); 244 } 245 246 mmio_setbits_32(NIC400_SATA_NOC_SECURITY1, SATA_NOC_SECURITY1_FIELD); 247 mmio_setbits_32(NIC400_SATA_NOC_SECURITY2, SATA_NOC_SECURITY2_FIELD); 248 mmio_setbits_32(NIC400_SATA_NOC_SECURITY3, SATA_NOC_SECURITY3_FIELD); 249 mmio_setbits_32(NIC400_SATA_NOC_SECURITY4, SATA_NOC_SECURITY4_FIELD); 250 mmio_setbits_32(NIC400_SATA_NOC_SECURITY5, SATA_NOC_SECURITY5_FIELD); 251 mmio_setbits_32(NIC400_SATA_NOC_SECURITY6, SATA_NOC_SECURITY6_FIELD); 252 mmio_setbits_32(NIC400_SATA_NOC_SECURITY7, SATA_NOC_SECURITY7_FIELD); 253 mmio_setbits_32(NIC400_SATA_NOC_SECURITY8, SATA_NOC_SECURITY8_FIELD); 254 mmio_setbits_32(NIC400_SATA_NOC_SECURITY9, SATA_NOC_SECURITY9_FIELD); 255 256 INFO("sata init done\n"); 257 } 258 #else 259 static void poweroff_sata_pll(void) 260 { 261 /* 262 * SATA subsystem is clocked by LCPLL0 which is enabled by 263 * default by bootrom. Poweroff the PLL if SATA is not used 264 */ 265 266 /* enable isolation */ 267 mmio_setbits_32(CRMU_AON_CTRL1, 268 BIT(CRMU_AON_CTRL1__LCPLL0_ISO_IN)); 269 270 /* Power off the SATA PLL/LDO */ 271 mmio_clrbits_32(CRMU_AON_CTRL1, 272 (BIT(CRMU_AON_CTRL1__LCPLL0_PWRON_LDO) | 273 BIT(CRMU_AON_CTRL1__LCPLL0_PWR_ON))); 274 } 275 #endif 276 277 #ifdef USE_AMAC 278 #ifdef EMULATION_SETUP 279 #define ICFG_AMAC_STRAP_CONFIG (HSLS_ICFG_REGS_BASE + 0xa5c) 280 #define ICFG_AMAC_STRAP_DLL_BYPASS (1 << 2) 281 #endif 282 #define ICFG_AMAC_MAC_CTRL_REG (HSLS_ICFG_REGS_BASE + 0xa6c) 283 #define ICFG_AMAC_MAC_FULL_DUPLEX (1 << 1) 284 #define ICFG_AMAC_RGMII_PHY_CONFIG (HSLS_ICFG_REGS_BASE + 0xa60) 285 #define ICFG_AMAC_SID_CONTROL (HSLS_ICFG_REGS_BASE + 0xb10) 286 #define ICFG_AMAC_SID_SHIFT 5 287 #define ICFG_AMAC_SID_AWADDR_OFFSET 0x0 288 #define ICFG_AMAC_SID_ARADDR_OFFSET 0x4 289 #define AMAC_RPHY_1000_DATARATE (1 << 20) 290 #define AMAC_RPHY_FULL_DUPLEX (1 << 5) 291 #define AMAC_RPHY_SPEED_OFFSET 2 292 #define AMAC_RPHY_SPEED_MASK (7 << AMAC_RPHY_SPEED_OFFSET) 293 #define AMAC_RPHY_1G_SPEED (2 << AMAC_RPHY_SPEED_OFFSET) 294 #define ICFG_AMAC_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xa68) 295 #define AMAC_ISO BIT(9) 296 #define AMAC_STDBY BIT(8) 297 #define AMAC_ARRPOWEROKIN BIT(7) 298 #define AMAC_ARRPOWERONIN BIT(6) 299 #define AMAC_POWEROKIN BIT(5) 300 #define AMAC_POWERONIN BIT(4) 301 302 #define AMAC_IDM0_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x4408) 303 #define AMAC_IDM0_ARCACHE_OFFSET 16 304 #define AMAC_IDM0_AWCACHE_OFFSET 7 305 #define AMAC_IDM0_ARCACHE_MASK (0xF << AMAC_IDM0_ARCACHE_OFFSET) 306 #define AMAC_IDM0_AWCACHE_MASK (0xF << AMAC_IDM0_AWCACHE_OFFSET) 307 /* ARCACHE - AWCACHE is 0xB7 for write-back no allocate */ 308 #define AMAC_IDM0_ARCACHE_VAL (0xb << AMAC_IDM0_ARCACHE_OFFSET) 309 #define AMAC_IDM0_AWCACHE_VAL (0x7 << AMAC_IDM0_AWCACHE_OFFSET) 310 311 static void brcm_stingray_amac_init(void) 312 { 313 unsigned int val; 314 uintptr_t icfg_amac_sid = ICFG_AMAC_SID_CONTROL; 315 316 VERBOSE("amac init start\n"); 317 318 val = SR_SID_VAL(0x3, 0x0, 0x4) << ICFG_AMAC_SID_SHIFT; 319 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_AWADDR_OFFSET, val); 320 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_ARADDR_OFFSET, val); 321 322 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_ARRPOWEROKIN); 323 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_ARRPOWERONIN); 324 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_POWEROKIN); 325 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_POWERONIN); 326 mmio_clrbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_ISO); 327 mmio_write_32(APBR_IDM_RESET_CONTROL, 0x0); 328 mmio_clrsetbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_SPEED_MASK, 329 AMAC_RPHY_1G_SPEED); /*1 Gbps line rate*/ 330 /* 1000 datarate set */ 331 mmio_setbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_1000_DATARATE); 332 /* full duplex */ 333 mmio_setbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_FULL_DUPLEX); 334 #ifdef EMULATION_SETUP 335 /* DLL bypass */ 336 mmio_setbits_32(ICFG_AMAC_STRAP_CONFIG, ICFG_AMAC_STRAP_DLL_BYPASS); 337 #endif 338 /* serdes full duplex */ 339 mmio_setbits_32(ICFG_AMAC_MAC_CTRL_REG, ICFG_AMAC_MAC_FULL_DUPLEX); 340 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_ARCACHE_MASK, 341 AMAC_IDM0_ARCACHE_VAL); 342 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_AWCACHE_MASK, 343 AMAC_IDM0_AWCACHE_VAL); 344 INFO("amac init done\n"); 345 } 346 #endif /* USE_AMAC */ 347 348 static void brcm_stingray_pka_meminit(void) 349 { 350 uintptr_t icfg_mem_ctrl = ICFG_PKA_MEM_PWR_CTRL; 351 352 VERBOSE("pka meminit start\n"); 353 354 VERBOSE(" - arrpoweron\n"); 355 mmio_setbits_32(icfg_mem_ctrl, 356 ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONIN); 357 while (!(mmio_read_32(icfg_mem_ctrl) & 358 ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONOUT)) 359 ; 360 361 VERBOSE(" - arrpowerok\n"); 362 mmio_setbits_32(icfg_mem_ctrl, 363 ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKIN); 364 while (!(mmio_read_32(icfg_mem_ctrl) & 365 ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKOUT)) 366 ; 367 368 VERBOSE(" - poweron\n"); 369 mmio_setbits_32(icfg_mem_ctrl, 370 ICFG_PKA_MEM_PWR_CTRL__POWERONIN); 371 while (!(mmio_read_32(icfg_mem_ctrl) & 372 ICFG_PKA_MEM_PWR_CTRL__POWERONOUT)) 373 ; 374 375 VERBOSE(" - powerok\n"); 376 mmio_setbits_32(icfg_mem_ctrl, 377 ICFG_PKA_MEM_PWR_CTRL__POWEROKIN); 378 while (!(mmio_read_32(icfg_mem_ctrl) & 379 ICFG_PKA_MEM_PWR_CTRL__POWEROKOUT)) 380 ; 381 382 /* Wait sometime */ 383 mdelay(1); 384 385 VERBOSE(" - remove isolation\n"); 386 mmio_clrbits_32(icfg_mem_ctrl, ICFG_PKA_MEM_PWR_CTRL__ISO); 387 388 INFO("pka meminit done\n"); 389 } 390 391 static void brcm_stingray_smmu_init(void) 392 { 393 unsigned int val; 394 uintptr_t smmu_base = SMMU_BASE; 395 396 VERBOSE("smmu init start\n"); 397 398 /* Configure SCR0 */ 399 VERBOSE(" - configure scr0\n"); 400 val = mmio_read_32(smmu_base + 0x0); 401 val |= (0x1 << 12); 402 mmio_write_32(smmu_base + 0x0, val); 403 404 /* Reserve context banks for secure masters */ 405 arm_smmu_reserve_secure_cntxt(); 406 407 /* Print configuration */ 408 VERBOSE(" - scr0=0x%x scr1=0x%x scr2=0x%x\n", 409 mmio_read_32(smmu_base + 0x0), 410 mmio_read_32(smmu_base + 0x4), 411 mmio_read_32(smmu_base + 0x8)); 412 413 VERBOSE(" - idr0=0x%x idr1=0x%x idr2=0x%x\n", 414 mmio_read_32(smmu_base + 0x20), 415 mmio_read_32(smmu_base + 0x24), 416 mmio_read_32(smmu_base + 0x28)); 417 418 VERBOSE(" - idr3=0x%x idr4=0x%x idr5=0x%x\n", 419 mmio_read_32(smmu_base + 0x2c), 420 mmio_read_32(smmu_base + 0x30), 421 mmio_read_32(smmu_base + 0x34)); 422 423 VERBOSE(" - idr6=0x%x idr7=0x%x\n", 424 mmio_read_32(smmu_base + 0x38), 425 mmio_read_32(smmu_base + 0x3c)); 426 427 INFO("smmu init done\n"); 428 } 429 430 static void brcm_stingray_dma_pl330_meminit(void) 431 { 432 uintptr_t icfg_mem_ctrl = ICFG_DMAC_MEM_PWR_CTRL; 433 434 VERBOSE("dmac meminit start\n"); 435 436 VERBOSE(" - arrpoweron\n"); 437 mmio_setbits_32(icfg_mem_ctrl, 438 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONIN); 439 while (!(mmio_read_32(icfg_mem_ctrl) & 440 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONOUT)) 441 ; 442 443 VERBOSE(" - arrpowerok\n"); 444 mmio_setbits_32(icfg_mem_ctrl, 445 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKIN); 446 while (!(mmio_read_32(icfg_mem_ctrl) & 447 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKOUT)) 448 ; 449 450 VERBOSE(" - poweron\n"); 451 mmio_setbits_32(icfg_mem_ctrl, 452 ICFG_DMAC_MEM_PWR_CTRL__POWERONIN); 453 while (!(mmio_read_32(icfg_mem_ctrl) & 454 ICFG_DMAC_MEM_PWR_CTRL__POWERONOUT)) 455 ; 456 457 VERBOSE(" - powerok\n"); 458 mmio_setbits_32(icfg_mem_ctrl, 459 ICFG_DMAC_MEM_PWR_CTRL__POWEROKIN); 460 while (!(mmio_read_32(icfg_mem_ctrl) & 461 ICFG_DMAC_MEM_PWR_CTRL__POWEROKOUT)) 462 ; 463 464 /* Wait sometime */ 465 mdelay(1); 466 467 VERBOSE(" - remove isolation\n"); 468 mmio_clrbits_32(icfg_mem_ctrl, ICFG_DMAC_MEM_PWR_CTRL__ISO); 469 470 INFO("dmac meminit done\n"); 471 } 472 473 /* program the crmu access ranges for allowing non sec access*/ 474 static void brcm_stingray_crmu_access_init(void) 475 { 476 /* Enable 0x6641c001 - 0x6641c701 for non secure access */ 477 mmio_write_32(CRMU_CORE_ADDR_RANGE0_LOW, 0x6641c001); 478 mmio_write_32(CRMU_CORE_ADDR_RANGE0_LOW + 0x4, 0x6641c701); 479 480 /* Enable 0x6641d001 - 0x66424b01 for non secure access */ 481 mmio_write_32(CRMU_CORE_ADDR_RANGE1_LOW, 0x6641d001); 482 mmio_write_32(CRMU_CORE_ADDR_RANGE1_LOW + 0x4, 0x66424b01); 483 484 /* Enable 0x66425001 - 0x66425f01 for non secure access */ 485 mmio_write_32(CRMU_CORE_ADDR_RANGE2_LOW, 0x66425001); 486 mmio_write_32(CRMU_CORE_ADDR_RANGE2_LOW + 0x4, 0x66425f01); 487 488 INFO("crmu access init done\n"); 489 } 490 491 static void brcm_stingray_scr_init(void) 492 { 493 unsigned int val; 494 uintptr_t scr_base = SCR_BASE; 495 unsigned int clr_mask = SCR_AXCACHE_CONFIG_MASK; 496 unsigned int set_mask = SCR_TBUX_AXCACHE_CONFIG; 497 498 VERBOSE("scr init start\n"); 499 500 /* awdomain=0x1 and ardomain=0x1 */ 501 mmio_clrsetbits_32(scr_base + 0x0, clr_mask, set_mask); 502 val = mmio_read_32(scr_base + 0x0); 503 VERBOSE(" - set tbu0_config=0x%x\n", val); 504 505 /* awdomain=0x1 and ardomain=0x1 */ 506 mmio_clrsetbits_32(scr_base + 0x4, clr_mask, set_mask); 507 val = mmio_read_32(scr_base + 0x4); 508 VERBOSE(" - set tbu1_config=0x%x\n", val); 509 510 /* awdomain=0x1 and ardomain=0x1 */ 511 mmio_clrsetbits_32(scr_base + 0x8, clr_mask, set_mask); 512 val = mmio_read_32(scr_base + 0x8); 513 VERBOSE(" - set tbu2_config=0x%x\n", val); 514 515 /* awdomain=0x1 and ardomain=0x1 */ 516 mmio_clrsetbits_32(scr_base + 0xc, clr_mask, set_mask); 517 val = mmio_read_32(scr_base + 0xc); 518 VERBOSE(" - set tbu3_config=0x%x\n", val); 519 520 /* awdomain=0x1 and ardomain=0x1 */ 521 mmio_clrsetbits_32(scr_base + 0x10, clr_mask, set_mask); 522 val = mmio_read_32(scr_base + 0x10); 523 VERBOSE(" - set tbu4_config=0x%x\n", val); 524 525 /* awdomain=0x0 and ardomain=0x0 */ 526 mmio_clrbits_32(scr_base + 0x14, clr_mask); 527 val = mmio_read_32(scr_base + 0x14); 528 VERBOSE(" - set gic_config=0x%x\n", val); 529 530 INFO("scr init done\n"); 531 } 532 533 static void brcm_stingray_hsls_tzpcprot_init(void) 534 { 535 unsigned int val; 536 uintptr_t tzpcdecprot_base = HSLS_TZPC_BASE; 537 538 VERBOSE("hsls tzpcprot init start\n"); 539 540 /* Treat third-party masters as non-secured */ 541 val = 0; 542 val |= BIT(6); /* SDIO1 */ 543 val |= BIT(5); /* SDIO0 */ 544 val |= BIT(0); /* AMAC */ 545 mmio_write_32(tzpcdecprot_base + 0x810, val); 546 547 /* Print TZPC decode status registers */ 548 VERBOSE(" - tzpcdecprot0=0x%x\n", 549 mmio_read_32(tzpcdecprot_base + 0x800)); 550 551 VERBOSE(" - tzpcdecprot1=0x%x\n", 552 mmio_read_32(tzpcdecprot_base + 0x80c)); 553 554 INFO("hsls tzpcprot init done\n"); 555 } 556 557 #ifdef USE_I2S 558 #define ICFG_AUDIO_POWER_CTRL (HSLS_ICFG_REGS_BASE + 0xaa8) 559 #define ICFG_AUDIO_POWER_CTRL__POWERONIN BIT(0) 560 #define ICFG_AUDIO_POWER_CTRL__POWEROKIN BIT(1) 561 #define ICFG_AUDIO_POWER_CTRL__ARRPOWERONIN BIT(2) 562 #define ICFG_AUDIO_POWER_CTRL__ARRPOWEROKIN BIT(3) 563 #define ICFG_AUDIO_POWER_CTRL__POWERONOUT BIT(4) 564 #define ICFG_AUDIO_POWER_CTRL__POWEROKOUT BIT(5) 565 #define ICFG_AUDIO_POWER_CTRL__ARRPOWERONOUT BIT(6) 566 #define ICFG_AUDIO_POWER_CTRL__ARRPOWEROKOUT BIT(7) 567 #define ICFG_AUDIO_POWER_CTRL__ISO BIT(8) 568 #define ICFG_AUDIO_SID_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf8) 569 #define ICFG_AUDIO_SID_SHIFT 5 570 #define ICFG_AUDIO_SID_AWADDR_OFFSET 0x0 571 #define ICFG_AUDIO_SID_ARADDR_OFFSET 0x4 572 573 #define I2S_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x1800) 574 #define I2S_IDM_IO_CONTROL (HSLS_IDM_REGS_BASE + 0x1408) 575 #define IO_CONTROL_CLK_ENABLE BIT(0) 576 #define I2S_IDM0_ARCACHE_OFFSET 16 577 #define I2S_IDM0_AWCACHE_OFFSET 20 578 #define I2S_IDM0_ARCACHE_MASK (0xF << I2S_IDM0_ARCACHE_OFFSET) 579 #define I2S_IDM0_AWCACHE_MASK (0xF << I2S_IDM0_AWCACHE_OFFSET) 580 /* ARCACHE - AWCACHE is 0x22 Normal Non-cacheable Non-bufferable. */ 581 #define I2S_IDM0_ARCACHE_VAL (0x2 << I2S_IDM0_ARCACHE_OFFSET) 582 #define I2S_IDM0_AWCACHE_VAL (0x2 << I2S_IDM0_AWCACHE_OFFSET) 583 584 static void brcm_stingray_audio_init(void) 585 { 586 unsigned int val; 587 uintptr_t icfg_mem_ctrl = ICFG_AUDIO_POWER_CTRL; 588 uintptr_t icfg_audio_sid = ICFG_AUDIO_SID_CONTROL; 589 590 mmio_write_32(I2S_RESET_CONTROL, 0x0); 591 592 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_ARCACHE_MASK, 593 I2S_IDM0_ARCACHE_VAL); 594 595 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_AWCACHE_MASK, 596 I2S_IDM0_AWCACHE_VAL); 597 598 mmio_setbits_32(I2S_IDM_IO_CONTROL, IO_CONTROL_CLK_ENABLE); 599 600 VERBOSE("audio meminit start\n"); 601 602 VERBOSE(" - configure stream_id = 0x6001\n"); 603 val = SR_SID_VAL(0x3, 0x0, 0x1) << ICFG_AUDIO_SID_SHIFT; 604 mmio_write_32(icfg_audio_sid + ICFG_AUDIO_SID_AWADDR_OFFSET, val); 605 mmio_write_32(icfg_audio_sid + ICFG_AUDIO_SID_ARADDR_OFFSET, val); 606 607 VERBOSE(" - arrpoweron\n"); 608 mmio_setbits_32(icfg_mem_ctrl, 609 ICFG_AUDIO_POWER_CTRL__ARRPOWERONIN); 610 while (!(mmio_read_32(icfg_mem_ctrl) & 611 ICFG_AUDIO_POWER_CTRL__ARRPOWERONOUT)) 612 ; 613 614 VERBOSE(" - arrpowerok\n"); 615 mmio_setbits_32(icfg_mem_ctrl, 616 ICFG_AUDIO_POWER_CTRL__ARRPOWEROKIN); 617 while (!(mmio_read_32(icfg_mem_ctrl) & 618 ICFG_AUDIO_POWER_CTRL__ARRPOWEROKOUT)) 619 ; 620 621 VERBOSE(" - poweron\n"); 622 mmio_setbits_32(icfg_mem_ctrl, 623 ICFG_AUDIO_POWER_CTRL__POWERONIN); 624 while (!(mmio_read_32(icfg_mem_ctrl) & 625 ICFG_AUDIO_POWER_CTRL__POWERONOUT)) 626 ; 627 628 VERBOSE(" - powerok\n"); 629 mmio_setbits_32(icfg_mem_ctrl, 630 ICFG_AUDIO_POWER_CTRL__POWEROKIN); 631 while (!(mmio_read_32(icfg_mem_ctrl) & 632 ICFG_AUDIO_POWER_CTRL__POWEROKOUT)) 633 ; 634 635 /* Wait sometime */ 636 mdelay(1); 637 638 VERBOSE(" - remove isolation\n"); 639 mmio_clrbits_32(icfg_mem_ctrl, ICFG_AUDIO_POWER_CTRL__ISO); 640 641 INFO("audio meminit done\n"); 642 } 643 #endif /* USE_I2S */ 644 645 /* 646 * These defines do not match the regfile but they are renamed in a way such 647 * that they are much more readible 648 */ 649 650 #define SCR_GPV_SMMU_NS (SCR_GPV_BASE + 0x28) 651 #define SCR_GPV_GIC500_NS (SCR_GPV_BASE + 0x34) 652 #define HSLS_GPV_NOR_S0_NS (HSLS_GPV_BASE + 0x14) 653 #define HSLS_GPV_IDM1_NS (HSLS_GPV_BASE + 0x18) 654 #define HSLS_GPV_IDM2_NS (HSLS_GPV_BASE + 0x1c) 655 #define HSLS_SDIO0_SLAVE_NS (HSLS_GPV_BASE + 0x20) 656 #define HSLS_SDIO1_SLAVE_NS (HSLS_GPV_BASE + 0x24) 657 #define HSLS_GPV_APBY_NS (HSLS_GPV_BASE + 0x2c) 658 #define HSLS_GPV_APBZ_NS (HSLS_GPV_BASE + 0x30) 659 #define HSLS_GPV_APBX_NS (HSLS_GPV_BASE + 0x34) 660 #define HSLS_GPV_APBS_NS (HSLS_GPV_BASE + 0x38) 661 #define HSLS_GPV_QSPI_S0_NS (HSLS_GPV_BASE + 0x68) 662 #define HSLS_GPV_APBR_NS (HSLS_GPV_BASE + 0x6c) 663 #define FS4_CRYPTO_GPV_RM_SLAVE_NS (FS4_CRYPTO_GPV_BASE + 0x8) 664 #define FS4_CRYPTO_GPV_APB_SWITCH_NS (FS4_CRYPTO_GPV_BASE + 0xc) 665 #define FS4_RAID_GPV_RM_SLAVE_NS (FS4_RAID_GPV_BASE + 0x8) 666 #define FS4_RAID_GPV_APB_SWITCH_NS (FS4_RAID_GPV_BASE + 0xc) 667 #define FS4_CRYPTO_IDM_NS (NIC400_FS_NOC_ROOT + 0x1c) 668 #define FS4_RAID_IDM_NS (NIC400_FS_NOC_ROOT + 0x28) 669 670 #define FS4_CRYPTO_RING_COUNT 32 671 #define FS4_CRYPTO_DME_COUNT 10 672 #define FS4_CRYPTO_AE_COUNT 10 673 #define FS4_CRYPTO_START_STREAM_ID 0x4000 674 #define FS4_CRYPTO_MSI_DEVICE_ID 0x4100 675 676 #define FS4_RAID_RING_COUNT 32 677 #define FS4_RAID_DME_COUNT 8 678 #define FS4_RAID_AE_COUNT 8 679 #define FS4_RAID_START_STREAM_ID 0x4200 680 #define FS4_RAID_MSI_DEVICE_ID 0x4300 681 682 #define FS6_PKI_AXI_SLAVE_NS \ 683 (NIC400_FS_NOC_ROOT + NIC400_FS_NOC_SECURITY2_OFFSET) 684 685 #define FS6_PKI_AE_DME_APB_NS \ 686 (NIC400_FS_NOC_ROOT + NIC400_FS_NOC_SECURITY7_OFFSET) 687 #define FS6_PKI_IDM_IO_CONTROL_DIRECT 0x0 688 #define FS6_PKI_IDM_RESET_CONTROL 0x0 689 #define FS6_PKI_RING_COUNT 32 690 #define FS6_PKI_DME_COUNT 1 691 #define FS6_PKI_AE_COUNT 4 692 #define FS6_PKI_START_STREAM_ID 0x4000 693 #define FS6_PKI_MSI_DEVICE_ID 0x4100 694 695 static void brcm_stingray_security_init(void) 696 { 697 unsigned int val; 698 699 val = mmio_read_32(SCR_GPV_SMMU_NS); 700 val |= BIT(0); /* SMMU NS = 1 */ 701 mmio_write_32(SCR_GPV_SMMU_NS, val); 702 703 val = mmio_read_32(SCR_GPV_GIC500_NS); 704 val |= BIT(0); /* GIC-500 NS = 1 */ 705 mmio_write_32(SCR_GPV_GIC500_NS, val); 706 707 val = mmio_read_32(HSLS_GPV_NOR_S0_NS); 708 val |= BIT(0); /* NOR SLAVE NS = 1 */ 709 mmio_write_32(HSLS_GPV_NOR_S0_NS, val); 710 711 val = mmio_read_32(HSLS_GPV_IDM1_NS); 712 val |= BIT(0); /* DMA IDM NS = 1 */ 713 val |= BIT(1); /* I2S IDM NS = 1 */ 714 val |= BIT(2); /* AMAC IDM NS = 1 */ 715 val |= BIT(3); /* SDIO0 IDM NS = 1 */ 716 val |= BIT(4); /* SDIO1 IDM NS = 1 */ 717 val |= BIT(5); /* DS_3 IDM NS = 1 */ 718 mmio_write_32(HSLS_GPV_IDM1_NS, val); 719 720 val = mmio_read_32(HSLS_GPV_IDM2_NS); 721 val |= BIT(2); /* QSPI IDM NS = 1 */ 722 val |= BIT(1); /* NOR IDM NS = 1 */ 723 val |= BIT(0); /* NAND IDM NS = 1 */ 724 mmio_write_32(HSLS_GPV_IDM2_NS, val); 725 726 val = mmio_read_32(HSLS_GPV_APBY_NS); 727 val |= BIT(10); /* I2S NS = 1 */ 728 val |= BIT(4); /* IOPAD NS = 1 */ 729 val |= 0xf; /* UARTx NS = 1 */ 730 mmio_write_32(HSLS_GPV_APBY_NS, val); 731 732 val = mmio_read_32(HSLS_GPV_APBZ_NS); 733 val |= BIT(2); /* RNG NS = 1 */ 734 mmio_write_32(HSLS_GPV_APBZ_NS, val); 735 736 val = mmio_read_32(HSLS_GPV_APBS_NS); 737 val |= 0x3; /* SPIx NS = 1 */ 738 mmio_write_32(HSLS_GPV_APBS_NS, val); 739 740 val = mmio_read_32(HSLS_GPV_APBR_NS); 741 val |= BIT(7); /* QSPI APB NS = 1 */ 742 val |= BIT(6); /* NAND APB NS = 1 */ 743 val |= BIT(5); /* NOR APB NS = 1 */ 744 val |= BIT(4); /* AMAC APB NS = 1 */ 745 val |= BIT(1); /* DMA S1 APB NS = 1 */ 746 mmio_write_32(HSLS_GPV_APBR_NS, val); 747 748 val = mmio_read_32(HSLS_SDIO0_SLAVE_NS); 749 val |= BIT(0); /* SDIO0 NS = 1 */ 750 mmio_write_32(HSLS_SDIO0_SLAVE_NS, val); 751 752 val = mmio_read_32(HSLS_SDIO1_SLAVE_NS); 753 val |= BIT(0); /* SDIO1 NS = 1 */ 754 mmio_write_32(HSLS_SDIO1_SLAVE_NS, val); 755 756 val = mmio_read_32(HSLS_GPV_APBX_NS); 757 val |= BIT(14); /* SMBUS1 NS = 1 */ 758 val |= BIT(13); /* GPIO NS = 1 */ 759 val |= BIT(12); /* WDT NS = 1 */ 760 val |= BIT(11); /* SMBUS0 NS = 1 */ 761 val |= BIT(10); /* Timer7 NS = 1 */ 762 val |= BIT(9); /* Timer6 NS = 1 */ 763 val |= BIT(8); /* Timer5 NS = 1 */ 764 val |= BIT(7); /* Timer4 NS = 1 */ 765 val |= BIT(6); /* Timer3 NS = 1 */ 766 val |= BIT(5); /* Timer2 NS = 1 */ 767 val |= BIT(4); /* Timer1 NS = 1 */ 768 val |= BIT(3); /* Timer0 NS = 1 */ 769 val |= BIT(2); /* MDIO NS = 1 */ 770 val |= BIT(1); /* PWM NS = 1 */ 771 mmio_write_32(HSLS_GPV_APBX_NS, val); 772 773 val = mmio_read_32(HSLS_GPV_QSPI_S0_NS); 774 val |= BIT(0); /* QSPI NS = 1 */ 775 mmio_write_32(HSLS_GPV_QSPI_S0_NS, val); 776 777 #ifdef USE_FS4 778 val = 0x1; /* FS4 Crypto rm_slave */ 779 mmio_write_32(FS4_CRYPTO_GPV_RM_SLAVE_NS, val); 780 val = 0x1; /* FS4 Crypto apb_switch */ 781 mmio_write_32(FS4_CRYPTO_GPV_APB_SWITCH_NS, val); 782 783 val = 0x1; /* FS4 Raid rm_slave */ 784 mmio_write_32(FS4_RAID_GPV_RM_SLAVE_NS, val); 785 val = 0x1; /* FS4 Raid apb_switch */ 786 mmio_write_32(FS4_RAID_GPV_APB_SWITCH_NS, val); 787 788 val = 0x1; /* FS4 Crypto IDM */ 789 mmio_write_32(FS4_CRYPTO_IDM_NS, val); 790 val = 0x1; /* FS4 RAID IDM */ 791 mmio_write_32(FS4_RAID_IDM_NS, val); 792 #endif 793 794 #ifdef BL31_CCN_NONSECURE 795 /* Enable non-secure access to CCN registers */ 796 mmio_write_32(OLY_MN_REGISTERS_NODE0_SECURE_ACCESS, 0x1); 797 #endif 798 799 #ifdef DDR_CTRL_PHY_NONSECURE 800 mmio_write_32(SCR_NOC_DDR_REGISTER_ACCESS, 0x1); 801 #endif 802 803 paxc_mhb_ns_init(); 804 805 /* unlock scr idm for non secure access */ 806 mmio_write_32(SCR_NOC_SECURITY0, 0xffffffff); 807 808 INFO("security init done\r\n"); 809 } 810 811 void brcm_gpio_pad_ns_init(void) 812 { 813 /* configure all GPIO pads for non secure world access*/ 814 mmio_write_32(GPIO_S_CNTRL_REG, 0xffffffff); /* 128-140 gpio pads */ 815 mmio_write_32(GPIO_S_CNTRL_REG + 0x4, 0xffffffff); /* 96-127 gpio pad */ 816 mmio_write_32(GPIO_S_CNTRL_REG + 0x8, 0xffffffff); /* 64-95 gpio pad */ 817 mmio_write_32(GPIO_S_CNTRL_REG + 0xc, 0xffffffff); /* 32-63 gpio pad */ 818 mmio_write_32(GPIO_S_CNTRL_REG + 0x10, 0xffffffff); /* 0-31 gpio pad */ 819 } 820 821 #ifndef USE_DDR 822 static void brcm_stingray_sram_ns_init(void) 823 { 824 uintptr_t sram_root = TZC400_FS_SRAM_ROOT; 825 uintptr_t noc_root = NIC400_FS_NOC_ROOT; 826 827 mmio_write_32(sram_root + GATE_KEEPER_OFFSET, 1); 828 mmio_write_32(sram_root + REGION_ATTRIBUTES_0_OFFSET, 0xc0000000); 829 mmio_write_32(sram_root + REGION_ID_ACCESS_0_OFFSET, 0x00010001); 830 mmio_write_32(noc_root + NIC400_FS_NOC_SECURITY4_OFFSET, 0x1); 831 INFO(" stingray sram ns init done.\n"); 832 } 833 #endif 834 835 static void ccn_pre_init(void) 836 { 837 /* 838 * Set WFC bit of RN-I nodes where FS4 is connected. 839 * This is required inorder to wait for read/write requests 840 * completion acknowledgment. Otherwise FS4 Ring Manager is 841 * getting stale data because of re-ordering of read/write 842 * requests at CCN level 843 */ 844 mmio_setbits_32(OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL, 845 OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WFC); 846 } 847 848 static void ccn_post_init(void) 849 { 850 mmio_setbits_32(OLY_HNI_REGISTERS_NODE0_PCIERC_RNI_NODEID_LIST, 851 SRP_RNI_PCIE_CONNECTED); 852 mmio_setbits_32(OLY_HNI_REGISTERS_NODE0_SA_AUX_CTL, 853 SA_AUX_CTL_SER_DEVNE_WR); 854 855 mmio_clrbits_32(OLY_HNI_REGISTERS_NODE0_POS_CONTROL, 856 POS_CONTROL_HNI_POS_EN); 857 mmio_clrbits_32(OLY_HNI_REGISTERS_NODE0_SA_AUX_CTL, 858 SA_AUX_CTL_POS_EARLY_WR_COMP_EN); 859 } 860 861 #ifndef BL31_BOOT_PRELOADED_SCP 862 static void crmu_init(void) 863 { 864 /* 865 * Configure CRMU for using SMMU 866 */ 867 868 /*Program CRMU Stream ID */ 869 mmio_write_32(CRMU_MASTER_AXI_ARUSER_CONFIG, 870 (CRMU_STREAM_ID << CRMU_SID_SHIFT)); 871 mmio_write_32(CRMU_MASTER_AXI_AWUSER_CONFIG, 872 (CRMU_STREAM_ID << CRMU_SID_SHIFT)); 873 874 /* Create Identity mapping */ 875 arm_smmu_create_identity_map(DOMAIN_CRMU); 876 877 /* Enable Client Port for Secure Masters*/ 878 arm_smmu_enable_secure_client_port(); 879 } 880 #endif 881 882 static void brcm_fsx_init(void) 883 { 884 #if defined(USE_FS4) && defined(USE_FS6) 885 #error "USE_FS4 and USE_FS6 should not be used together" 886 #endif 887 888 #ifdef USE_FS4 889 fsx_init(eFS4_CRYPTO, FS4_CRYPTO_RING_COUNT, FS4_CRYPTO_DME_COUNT, 890 FS4_CRYPTO_AE_COUNT, FS4_CRYPTO_START_STREAM_ID, 891 FS4_CRYPTO_MSI_DEVICE_ID, FS4_CRYPTO_IDM_IO_CONTROL_DIRECT, 892 FS4_CRYPTO_IDM_RESET_CONTROL, FS4_CRYPTO_BASE, 893 FS4_CRYPTO_DME_BASE); 894 895 fsx_init(eFS4_RAID, FS4_RAID_RING_COUNT, FS4_RAID_DME_COUNT, 896 FS4_RAID_AE_COUNT, FS4_RAID_START_STREAM_ID, 897 FS4_RAID_MSI_DEVICE_ID, FS4_RAID_IDM_IO_CONTROL_DIRECT, 898 FS4_RAID_IDM_RESET_CONTROL, FS4_RAID_BASE, 899 FS4_RAID_DME_BASE); 900 901 fsx_meminit("raid", 902 FS4_RAID_IDM_IO_CONTROL_DIRECT, 903 FS4_RAID_IDM_IO_STATUS); 904 #endif 905 } 906 907 static void bcm_bl33_pass_info(void) 908 { 909 struct bl33_info *info = (struct bl33_info *)BL33_SHARED_DDR_BASE; 910 911 if (sizeof(*info) > BL33_SHARED_DDR_SIZE) 912 WARN("bl33 shared area not reserved\n"); 913 914 info->version = BL33_INFO_VERSION; 915 info->chip.chip_id = PLAT_CHIP_ID_GET; 916 info->chip.rev_id = PLAT_CHIP_REV_GET; 917 } 918 919 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A72_L2CTLR_EL1) 920 921 void plat_bcm_bl31_early_platform_setup(void *from_bl2, 922 bl_params_t *plat_params_from_bl2) 923 { 924 #ifdef BL31_BOOT_PRELOADED_SCP 925 image_info_t scp_image_info; 926 927 scp_image_info.image_base = PRELOADED_SCP_BASE; 928 scp_image_info.image_size = PRELOADED_SCP_SIZE; 929 plat_bcm_bl2_plat_handle_scp_bl2(&scp_image_info); 930 #endif 931 /* 932 * In BL31, logs are saved to DDR and we have much larger space to 933 * store logs. We can now afford to save all logs >= the 'INFO' level 934 */ 935 bcm_elog_init((void *)BCM_ELOG_BL31_BASE, BCM_ELOG_BL31_SIZE, 936 LOG_LEVEL_INFO); 937 938 INFO("L2CTLR = 0x%lx\n", read_l2ctlr_el1()); 939 940 brcm_timer_sync_init(); 941 942 brcm_stingray_dma_pl330_init(); 943 944 brcm_stingray_dma_pl330_meminit(); 945 946 brcm_stingray_spi_pl022_init(APBS_IDM_IDM_RESET_CONTROL); 947 948 #ifdef USE_AMAC 949 brcm_stingray_amac_init(); 950 #endif 951 952 brcm_stingray_sdio_init(); 953 954 #ifdef NCSI_IO_DRIVE_STRENGTH_MA 955 brcm_stingray_ncsi_init(); 956 #endif 957 958 #ifdef USE_USB 959 xhci_phy_init(); 960 #endif 961 962 #ifdef USE_SATA 963 brcm_stingray_sata_init(); 964 #else 965 poweroff_sata_pll(); 966 #endif 967 968 ccn_pre_init(); 969 970 brcm_fsx_init(); 971 972 brcm_stingray_smmu_init(); 973 974 brcm_stingray_pka_meminit(); 975 976 brcm_stingray_crmu_access_init(); 977 978 brcm_stingray_scr_init(); 979 980 brcm_stingray_hsls_tzpcprot_init(); 981 982 #ifdef USE_I2S 983 brcm_stingray_audio_init(); 984 #endif 985 986 ccn_post_init(); 987 988 paxb_init(); 989 990 paxc_init(); 991 992 #ifndef BL31_BOOT_PRELOADED_SCP 993 crmu_init(); 994 #endif 995 996 /* Note: this should be last thing because 997 * FS4 GPV registers only work after FS4 block 998 * (i.e. crypto,raid,cop) is out of reset. 999 */ 1000 brcm_stingray_security_init(); 1001 1002 brcm_gpio_pad_ns_init(); 1003 1004 #ifndef USE_DDR 1005 brcm_stingray_sram_ns_init(); 1006 #endif 1007 1008 #ifdef BL31_FORCE_CPU_FULL_FREQ 1009 bcm_set_ihost_pll_freq(0x0, PLL_FREQ_FULL); 1010 #endif 1011 1012 brcm_stingray_gain_qspi_control(); 1013 1014 #ifdef USE_PAXC 1015 /* 1016 * Check that the handshake has occurred and report ChiMP status. 1017 * This is required. Otherwise (especially on Palladium) 1018 * Linux might have booted to the pcie stage whereas 1019 * ChiMP has not yet booted. Note that nic_mode case has already 1020 * been considered above. 1021 */ 1022 if ((boot_source_get() != BOOT_SOURCE_QSPI) && 1023 (!bcm_chimp_is_nic_mode()) && 1024 (!bcm_chimp_wait_handshake()) 1025 ) { 1026 /* Does ChiMP report an error ? */ 1027 uint32_t err; 1028 1029 err = bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_STAT_REG); 1030 if ((err & CHIMP_ERROR_MASK) == 0) 1031 /* ChiMP has not booted yet, but no error reported */ 1032 WARN("ChiMP not booted yet, but no error reported.\n"); 1033 } 1034 1035 #if DEBUG 1036 if (boot_source_get() != BOOT_SOURCE_QSPI) 1037 INFO("Current ChiMP Status: 0x%x; bpe_mod reg: 0x%x\n" 1038 "fastboot register: 0x%x; handshake register 0x%x\n", 1039 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_STAT_REG), 1040 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_MODE_REG), 1041 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_FSTBOOT_PTR_REG), 1042 bcm_chimp_read(CHIMP_REG_ECO_RESERVED)); 1043 #endif /* DEBUG */ 1044 #endif 1045 1046 #ifdef FS4_DISABLE_CLOCK 1047 flush_dcache_range( 1048 PLAT_BRCM_TRUSTED_SRAM_BASE, 1049 PLAT_BRCM_TRUSTED_SRAM_SIZE); 1050 fs4_disable_clocks(true, true, true); 1051 #endif 1052 1053 /* pass information to BL33 through shared DDR region */ 1054 bcm_bl33_pass_info(); 1055 1056 /* 1057 * We are not yet at the end of BL31, but we can stop log here so we do 1058 * not need to add 'bcm_elog_exit' to the standard BL31 code. The 1059 * benefit of capturing BL31 logs after this is very minimal in a 1060 * production system 1061 */ 1062 bcm_elog_exit(); 1063 1064 #if !BRCM_DISABLE_TRUSTED_WDOG 1065 /* 1066 * Secure watchdog was started earlier in BL2, now it's time to stop 1067 * it 1068 */ 1069 sp805_stop(ARM_SP805_TWDG_BASE); 1070 #endif 1071 } 1072