1 /* 2 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <arch_helpers.h> 10 #include <bl1/bl1.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/console.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_storage.h> 17 #include <libfdt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_defs.h> 20 #include <platform_def.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "board.h" 25 #include "boot_init_dram.h" 26 #include "cpg_registers.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 #include "io_common.h" 31 #include "io_rcar.h" 32 #include "qos_init.h" 33 #include "rcar_def.h" 34 #include "rcar_private.h" 35 #include "rcar_version.h" 36 #include "rom_api.h" 37 38 #define MAX_DRAM_CHANNELS 4 39 /* 40 * DDR ch0 has a shadow area mapped in 32bit address space. 41 * Physical address 0x4_0000_0000 - 0x4_7fff_ffff in 64bit space 42 * is mapped to 0x4000_0000 - 0xbfff_ffff in 32bit space. 43 */ 44 #define MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE 0x80000000ULL 45 46 #if RCAR_BL2_DCACHE == 1 47 /* 48 * Following symbols are only used during plat_arch_setup() only 49 * when RCAR_BL2_DCACHE is enabled. 50 */ 51 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 52 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 53 54 #if USE_COHERENT_MEM 55 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 56 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 57 #endif /* USE_COHERENT_MEM */ 58 59 #endif /* RCAR_BL2_DCACHE */ 60 61 extern void plat_rcar_gic_driver_init(void); 62 extern void plat_rcar_gic_init(void); 63 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 64 extern void bl2_system_cpg_init(void); 65 extern void bl2_secure_setting(void); 66 extern void bl2_cpg_init(void); 67 extern void rcar_io_emmc_setup(void); 68 extern void rcar_io_setup(void); 69 extern void rcar_swdt_release(void); 70 extern void rcar_swdt_init(void); 71 extern void rcar_rpc_init(void); 72 extern void rcar_dma_init(void); 73 extern void rzg_pfc_init(void); 74 75 static void bl2_init_generic_timer(void); 76 77 /* RZ/G2 product check */ 78 #if RCAR_LSI == RZ_G2M 79 #define TARGET_PRODUCT PRR_PRODUCT_M3 80 #define TARGET_NAME "RZ/G2M" 81 #elif RCAR_LSI == RZ_G2H 82 #define TARGET_PRODUCT PRR_PRODUCT_H3 83 #define TARGET_NAME "RZ/G2H" 84 #elif RCAR_LSI == RZ_G2N 85 #define TARGET_PRODUCT PRR_PRODUCT_M3N 86 #define TARGET_NAME "RZ/G2N" 87 #elif RCAR_LSI == RCAR_AUTO 88 #define TARGET_NAME "RZ/G2M" 89 #endif /* RCAR_LSI == RZ_G2M */ 90 91 #define GPIO_INDT (GPIO_INDT1) 92 #define GPIO_BKUP_TRG_SHIFT (1U << 8U) 93 94 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 95 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 96 assert_bl31_params_do_not_fit_in_shared_memory); 97 98 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 99 100 /* FDT with DRAM configuration */ 101 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 102 static void *fdt = (void *)fdt_blob; 103 104 static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string) 105 { 106 /* Just need enough space to store 64 bit decimal integer */ 107 char num_buf[20]; 108 int i = 0; 109 unsigned int rem; 110 111 do { 112 rem = unum % radix; 113 if (rem < 0xaU) { 114 num_buf[i] = '0' + rem; 115 } else { 116 num_buf[i] = 'a' + (rem - 0xaU); 117 } 118 i++; 119 unum /= radix; 120 } while (unum > 0U); 121 122 while (--i >= 0) { 123 *string++ = num_buf[i]; 124 } 125 *string = 0; 126 } 127 128 #if RCAR_LOSSY_ENABLE == 1 129 typedef struct bl2_lossy_info { 130 uint32_t magic; 131 uint32_t a0; 132 uint32_t b0; 133 } bl2_lossy_info_t; 134 135 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 136 uint64_t end_addr, uint32_t format, 137 uint32_t enable, int fcnlnode) 138 { 139 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 140 char nodename[40] = { 0 }; 141 int ret, node; 142 143 /* Ignore undefined addresses */ 144 if (start_addr == 0UL && end_addr == 0UL) { 145 return; 146 } 147 148 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 149 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 150 151 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 152 if (ret < 0) { 153 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 154 panic(); 155 } 156 157 ret = fdt_setprop_string(fdt, node, "compatible", 158 "renesas,lossy-decompression"); 159 if (ret < 0) { 160 NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n", 161 "renesas,lossy-decompression", ret); 162 panic(); 163 } 164 165 ret = fdt_appendprop_string(fdt, node, "compatible", 166 "shared-dma-pool"); 167 if (ret < 0) { 168 NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n", 169 "shared-dma-pool", ret); 170 panic(); 171 } 172 173 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 174 if (ret < 0) { 175 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 176 panic(); 177 } 178 179 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 180 if (ret < 0) { 181 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 182 panic(); 183 } 184 185 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 186 if (ret < 0) { 187 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 188 panic(); 189 } 190 191 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 192 if (ret < 0) { 193 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 194 panic(); 195 } 196 } 197 198 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 199 uint64_t end_addr, uint32_t format, 200 uint32_t enable, int fcnlnode) 201 { 202 bl2_lossy_info_t info; 203 uint32_t reg; 204 205 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 206 207 reg = format | (start_addr >> 20); 208 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); 209 mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20); 210 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); 211 212 info.magic = 0x12345678U; 213 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no); 214 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no); 215 216 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 217 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0); 218 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0); 219 220 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 221 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no), 222 mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no)); 223 } 224 #endif /* RCAR_LOSSY_ENABLE == 1 */ 225 226 void bl2_plat_flush_bl31_params(void) 227 { 228 uint32_t product_cut, product, cut; 229 uint32_t boot_dev, boot_cpu; 230 uint32_t reg; 231 232 reg = mmio_read_32(RCAR_MODEMR); 233 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 234 235 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 236 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 237 emmc_terminate(); 238 } 239 240 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) { 241 bl2_secure_setting(); 242 } 243 244 reg = mmio_read_32(RCAR_PRR); 245 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 246 product = reg & PRR_PRODUCT_MASK; 247 cut = reg & PRR_CUT_MASK; 248 249 if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) || 250 (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) { 251 /* Disable MFIS write protection */ 252 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U); 253 } 254 255 reg = mmio_read_32(RCAR_MODEMR); 256 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 257 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 258 boot_cpu == MODEMR_BOOT_CPU_CA53) { 259 if (product_cut == PRR_PRODUCT_H3_CUT20) { 260 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 261 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 262 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 263 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 264 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 265 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 266 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 267 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 268 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 269 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 270 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 271 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 272 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 273 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 274 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 275 } 276 277 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 278 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 279 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 280 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 281 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 282 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 283 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 284 285 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 286 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 287 } 288 } 289 290 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 291 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 292 293 rcar_swdt_release(); 294 bl2_system_cpg_init(); 295 296 #if RCAR_BL2_DCACHE == 1 297 /* Disable data cache (clean and invalidate) */ 298 disable_mmu_el3(); 299 #endif /* RCAR_BL2_DCACHE == 1 */ 300 } 301 302 static uint32_t is_ddr_backup_mode(void) 303 { 304 #if RCAR_SYSTEM_SUSPEND 305 static uint32_t reason = RCAR_COLD_BOOT; 306 static uint32_t once; 307 308 if (once != 0U) { 309 return reason; 310 } 311 312 once = 1; 313 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) { 314 return reason; 315 } 316 317 reason = RCAR_WARM_BOOT; 318 return reason; 319 #else /* RCAR_SYSTEM_SUSPEND */ 320 return RCAR_COLD_BOOT; 321 #endif /* RCAR_SYSTEM_SUSPEND */ 322 } 323 324 int bl2_plat_handle_pre_image_load(unsigned int image_id) 325 { 326 u_register_t *boot_kind = (void *)BOOT_KIND_BASE; 327 bl_mem_params_node_t *bl_mem_params; 328 329 if (image_id != BL31_IMAGE_ID) { 330 return 0; 331 } 332 333 bl_mem_params = get_bl_mem_params_node(image_id); 334 335 if (is_ddr_backup_mode() != RCAR_COLD_BOOT) { 336 *boot_kind = RCAR_WARM_BOOT; 337 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 338 339 console_flush(); 340 bl2_plat_flush_bl31_params(); 341 342 /* will not return */ 343 bl2_enter_bl31(&bl_mem_params->ep_info); 344 } 345 346 *boot_kind = RCAR_COLD_BOOT; 347 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 348 349 return 0; 350 } 351 352 static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 353 { 354 uint32_t cert, len; 355 int err; 356 357 err = rcar_get_certificate(certid, &cert); 358 if (err != 0) { 359 ERROR("%s : cert file load error", __func__); 360 return 1U; 361 } 362 363 rcar_read_certificate((uint64_t)cert, &len, dest); 364 365 return 0U; 366 } 367 368 int bl2_plat_handle_post_image_load(unsigned int image_id) 369 { 370 static bl2_to_bl31_params_mem_t *params; 371 bl_mem_params_node_t *bl_mem_params; 372 uintptr_t dest; 373 uint64_t ret; 374 375 if (params == NULL) { 376 params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 377 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 378 } 379 380 bl_mem_params = get_bl_mem_params_node(image_id); 381 382 switch (image_id) { 383 case BL31_IMAGE_ID: 384 ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 385 &dest); 386 if (ret == 0U) { 387 bl_mem_params->image_info.image_base = dest; 388 } 389 break; 390 case BL32_IMAGE_ID: 391 ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 392 &dest); 393 if (ret == 0U) { 394 bl_mem_params->image_info.image_base = dest; 395 } 396 397 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 398 sizeof(entry_point_info_t)); 399 break; 400 case BL33_IMAGE_ID: 401 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 402 sizeof(entry_point_info_t)); 403 break; 404 default: 405 break; 406 } 407 408 return 0; 409 } 410 411 struct meminfo *bl2_plat_sec_mem_layout(void) 412 { 413 return &bl2_tzram_layout; 414 } 415 416 static void bl2_populate_compatible_string(void *dt) 417 { 418 uint32_t board_type; 419 uint32_t board_rev; 420 uint32_t reg; 421 int ret; 422 423 fdt_setprop_u32(dt, 0, "#address-cells", 2); 424 fdt_setprop_u32(dt, 0, "#size-cells", 2); 425 426 /* Populate compatible string */ 427 rzg_get_board_type(&board_type, &board_rev); 428 switch (board_type) { 429 case BOARD_HIHOPE_RZ_G2M: 430 ret = fdt_setprop_string(dt, 0, "compatible", 431 "hoperun,hihope-rzg2m"); 432 break; 433 case BOARD_HIHOPE_RZ_G2H: 434 ret = fdt_setprop_string(dt, 0, "compatible", 435 "hoperun,hihope-rzg2h"); 436 break; 437 case BOARD_HIHOPE_RZ_G2N: 438 ret = fdt_setprop_string(dt, 0, "compatible", 439 "hoperun,hihope-rzg2n"); 440 break; 441 default: 442 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 443 panic(); 444 break; 445 } 446 447 if (ret < 0) { 448 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 449 panic(); 450 } 451 452 reg = mmio_read_32(RCAR_PRR); 453 switch (reg & PRR_PRODUCT_MASK) { 454 case PRR_PRODUCT_M3: 455 ret = fdt_appendprop_string(dt, 0, "compatible", 456 "renesas,r8a774a1"); 457 break; 458 case PRR_PRODUCT_H3: 459 ret = fdt_appendprop_string(dt, 0, "compatible", 460 "renesas,r8a774e1"); 461 break; 462 case PRR_PRODUCT_M3N: 463 ret = fdt_appendprop_string(dt, 0, "compatible", 464 "renesas,r8a774b1"); 465 break; 466 default: 467 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 468 panic(); 469 break; 470 } 471 472 if (ret < 0) { 473 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 474 panic(); 475 } 476 } 477 478 static int bl2_add_memory_node(uint64_t start, uint64_t size) 479 { 480 char nodename[32] = { 0 }; 481 uint64_t fdtsize; 482 int ret, node; 483 484 fdtsize = cpu_to_fdt64(size); 485 486 snprintf(nodename, sizeof(nodename), "memory@"); 487 unsigned_num_print(start, 16, nodename + strlen(nodename)); 488 node = ret = fdt_add_subnode(fdt, 0, nodename); 489 if (ret < 0) { 490 return ret; 491 } 492 493 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 494 if (ret < 0) { 495 return ret; 496 } 497 498 ret = fdt_setprop_u64(fdt, node, "reg", start); 499 if (ret < 0) { 500 return ret; 501 } 502 503 return fdt_appendprop(fdt, node, "reg", &fdtsize, sizeof(fdtsize)); 504 } 505 506 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 507 { 508 uint64_t start, size; 509 int ret, chan; 510 511 for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) { 512 start = dram_config[2 * chan]; 513 size = dram_config[2 * chan + 1]; 514 if (size == 0U) { 515 continue; 516 } 517 518 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 519 chan, start, start + size - 1U, 520 (size >> 30) ? : size >> 20, 521 (size >> 30) ? "G" : "M"); 522 } 523 524 /* 525 * We add the DT nodes in reverse order here. The fdt_add_subnode() 526 * adds the DT node before the first existing DT node, so we have 527 * to add them in reverse order to get nodes sorted by address in 528 * the resulting DT. 529 */ 530 for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) { 531 start = dram_config[2 * chan]; 532 size = dram_config[2 * chan + 1]; 533 if (size == 0U) { 534 continue; 535 } 536 537 /* 538 * Channel 0 is mapped in 32bit space and the first 539 * 128 MiB are reserved 540 */ 541 if (chan == 0) { 542 /* 543 * Maximum DDR size in Channel 0 for 32 bit space is 2GB, Add DT node 544 * for remaining region in 64 bit address space 545 */ 546 if (size > MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE) { 547 start = dram_config[chan] + MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 548 size -= MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 549 ret = bl2_add_memory_node(start, size); 550 if (ret < 0) { 551 goto err; 552 } 553 } 554 start = 0x48000000U; 555 size -= 0x8000000U; 556 } 557 558 ret = bl2_add_memory_node(start, size); 559 if (ret < 0) { 560 goto err; 561 } 562 } 563 564 return; 565 err: 566 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 567 panic(); 568 } 569 570 static void bl2_advertise_dram_size(uint32_t product) 571 { 572 uint64_t dram_config[8] = { 573 [0] = 0x400000000ULL, 574 [2] = 0x500000000ULL, 575 [4] = 0x600000000ULL, 576 [6] = 0x700000000ULL, 577 }; 578 579 switch (product) { 580 case PRR_PRODUCT_M3: 581 /* 4GB(2GBx2 2ch split) */ 582 dram_config[1] = 0x80000000ULL; 583 dram_config[5] = 0x80000000ULL; 584 break; 585 case PRR_PRODUCT_H3: 586 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 587 /* 4GB(1GBx4) */ 588 dram_config[1] = 0x40000000ULL; 589 dram_config[3] = 0x40000000ULL; 590 dram_config[5] = 0x40000000ULL; 591 dram_config[7] = 0x40000000ULL; 592 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \ 593 (RCAR_DRAM_SPLIT == 2) 594 /* 4GB(2GBx2 2ch split) */ 595 dram_config[1] = 0x80000000ULL; 596 dram_config[3] = 0x80000000ULL; 597 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 598 /* 8GB(2GBx4: default) */ 599 dram_config[1] = 0x80000000ULL; 600 dram_config[3] = 0x80000000ULL; 601 dram_config[5] = 0x80000000ULL; 602 dram_config[7] = 0x80000000ULL; 603 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 604 break; 605 case PRR_PRODUCT_M3N: 606 /* 4GB(4GBx1) */ 607 dram_config[1] = 0x100000000ULL; 608 break; 609 default: 610 NOTICE("BL2: Detected invalid DRAM entries\n"); 611 break; 612 } 613 614 bl2_advertise_dram_entries(dram_config); 615 } 616 617 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 618 u_register_t arg3, u_register_t arg4) 619 { 620 uint32_t reg, midr, boot_dev, boot_cpu, type, rev; 621 uint32_t product, product_cut, major, minor; 622 int32_t ret; 623 const char *str; 624 const char *unknown = "unknown"; 625 const char *cpu_ca57 = "CA57"; 626 const char *cpu_ca53 = "CA53"; 627 const char *product_g2h = "G2H"; 628 const char *product_g2m = "G2M"; 629 const char *product_g2n = "G2N"; 630 const char *boot_hyper80 = "HyperFlash(80MHz)"; 631 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 632 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 633 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 634 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 635 const char *boot_hyper160 = "HyperFlash(160MHz)"; 636 #if RZG_LCS_STATE_DETECTION_ENABLE 637 uint32_t lcs; 638 const char *lcs_secure = "SE"; 639 const char *lcs_cm = "CM"; 640 const char *lcs_dm = "DM"; 641 const char *lcs_sd = "SD"; 642 const char *lcs_fa = "FA"; 643 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 644 645 #if (RCAR_LOSSY_ENABLE == 1) 646 int fcnlnode; 647 #endif /* (RCAR_LOSSY_ENABLE == 1) */ 648 649 bl2_init_generic_timer(); 650 651 reg = mmio_read_32(RCAR_MODEMR); 652 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 653 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 654 655 bl2_cpg_init(); 656 657 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 658 boot_cpu == MODEMR_BOOT_CPU_CA53) { 659 rzg_pfc_init(); 660 rcar_console_boot_init(); 661 } 662 663 plat_rcar_gic_driver_init(); 664 plat_rcar_gic_init(); 665 rcar_swdt_init(); 666 667 /* FIQ interrupts are taken to EL3 */ 668 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 669 670 write_daifclr(DAIF_FIQ_BIT); 671 672 reg = read_midr(); 673 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 674 switch (midr) { 675 case MIDR_CA57: 676 str = cpu_ca57; 677 break; 678 case MIDR_CA53: 679 str = cpu_ca53; 680 break; 681 default: 682 str = unknown; 683 break; 684 } 685 686 NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str, 687 version_of_renesas); 688 689 reg = mmio_read_32(RCAR_PRR); 690 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 691 product = reg & PRR_PRODUCT_MASK; 692 693 switch (product) { 694 case PRR_PRODUCT_M3: 695 str = product_g2m; 696 break; 697 case PRR_PRODUCT_H3: 698 str = product_g2h; 699 break; 700 case PRR_PRODUCT_M3N: 701 str = product_g2n; 702 break; 703 default: 704 str = unknown; 705 break; 706 } 707 708 if ((product == PRR_PRODUCT_M3) && 709 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) { 710 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) { 711 /* M3 Ver.1.1 or Ver.1.2 */ 712 NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str); 713 } else { 714 NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str, 715 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 716 } 717 } else { 718 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 719 major = major + RCAR_MAJOR_OFFSET; 720 minor = reg & RCAR_MINOR_MASK; 721 NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor); 722 } 723 724 rzg_get_board_type(&type, &rev); 725 726 switch (type) { 727 case BOARD_HIHOPE_RZ_G2M: 728 case BOARD_HIHOPE_RZ_G2H: 729 case BOARD_HIHOPE_RZ_G2N: 730 break; 731 default: 732 type = BOARD_UNKNOWN; 733 break; 734 } 735 736 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) { 737 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 738 } else { 739 NOTICE("BL2: Board is %s Rev.%d.%d\n", 740 GET_BOARD_NAME(type), 741 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 742 } 743 744 #if RCAR_LSI != RCAR_AUTO 745 if (product != TARGET_PRODUCT) { 746 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 747 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 748 panic(); 749 } 750 #endif /* RCAR_LSI != RCAR_AUTO */ 751 rcar_avs_init(); 752 rcar_avs_setting(); 753 754 switch (boot_dev) { 755 case MODEMR_BOOT_DEV_HYPERFLASH160: 756 str = boot_hyper160; 757 break; 758 case MODEMR_BOOT_DEV_HYPERFLASH80: 759 str = boot_hyper80; 760 break; 761 case MODEMR_BOOT_DEV_QSPI_FLASH40: 762 str = boot_qspi40; 763 break; 764 case MODEMR_BOOT_DEV_QSPI_FLASH80: 765 str = boot_qspi80; 766 break; 767 case MODEMR_BOOT_DEV_EMMC_25X1: 768 str = boot_emmc25x1; 769 break; 770 case MODEMR_BOOT_DEV_EMMC_50X8: 771 str = boot_emmc50x8; 772 break; 773 default: 774 str = unknown; 775 break; 776 } 777 NOTICE("BL2: Boot device is %s\n", str); 778 779 rcar_avs_setting(); 780 781 #if RZG_LCS_STATE_DETECTION_ENABLE 782 reg = rcar_rom_get_lcs(&lcs); 783 if (reg != 0U) { 784 str = unknown; 785 goto lcm_state; 786 } 787 788 switch (lcs) { 789 case LCS_CM: 790 str = lcs_cm; 791 break; 792 case LCS_DM: 793 str = lcs_dm; 794 break; 795 case LCS_SD: 796 str = lcs_sd; 797 break; 798 case LCS_SE: 799 str = lcs_secure; 800 break; 801 case LCS_FA: 802 str = lcs_fa; 803 break; 804 default: 805 str = unknown; 806 break; 807 } 808 809 lcm_state: 810 NOTICE("BL2: LCM state is %s\n", str); 811 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 812 813 rcar_avs_end(); 814 is_ddr_backup_mode(); 815 816 bl2_tzram_layout.total_base = BL31_BASE; 817 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 818 819 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 820 boot_cpu == MODEMR_BOOT_CPU_CA53) { 821 ret = rcar_dram_init(); 822 if (ret != 0) { 823 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 824 panic(); 825 } 826 rzg_qos_init(); 827 } 828 829 /* Set up FDT */ 830 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 831 if (ret != 0) { 832 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 833 panic(); 834 } 835 836 /* Add platform compatible string */ 837 bl2_populate_compatible_string(fdt); 838 839 /* Print DRAM layout */ 840 bl2_advertise_dram_size(product); 841 842 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 843 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 844 if (rcar_emmc_init() != EMMC_SUCCESS) { 845 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 846 panic(); 847 } 848 rcar_emmc_memcard_power(EMMC_POWER_ON); 849 if (rcar_emmc_mount() != EMMC_SUCCESS) { 850 NOTICE("BL2: Failed to eMMC mount operation.\n"); 851 panic(); 852 } 853 } else { 854 rcar_rpc_init(); 855 rcar_dma_init(); 856 } 857 858 reg = mmio_read_32(RST_WDTRSTCR); 859 reg &= ~WDTRSTCR_RWDT_RSTMSK; 860 reg |= WDTRSTCR_PASSWORD; 861 mmio_write_32(RST_WDTRSTCR, reg); 862 863 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 864 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 865 866 reg = mmio_read_32(RCAR_PRR); 867 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) { 868 mmio_write_32(CPG_CA57DBGRCR, 869 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 870 } 871 872 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) { 873 mmio_write_32(CPG_CA53DBGRCR, 874 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 875 } 876 877 if (product_cut == PRR_PRODUCT_H3_CUT10) { 878 reg = mmio_read_32(CPG_PLL2CR); 879 reg &= ~((uint32_t)1 << 5); 880 mmio_write_32(CPG_PLL2CR, reg); 881 882 reg = mmio_read_32(CPG_PLL4CR); 883 reg &= ~((uint32_t)1 << 5); 884 mmio_write_32(CPG_PLL4CR, reg); 885 886 reg = mmio_read_32(CPG_PLL0CR); 887 reg &= ~((uint32_t)1 << 12); 888 mmio_write_32(CPG_PLL0CR, reg); 889 } 890 #if (RCAR_LOSSY_ENABLE == 1) 891 NOTICE("BL2: Lossy Decomp areas\n"); 892 893 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 894 if (fcnlnode < 0) { 895 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 896 fcnlnode); 897 panic(); 898 } 899 900 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 901 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 902 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 903 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 904 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 905 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 906 #endif /* RCAR_LOSSY_ENABLE */ 907 908 fdt_pack(fdt); 909 NOTICE("BL2: FDT at %p\n", fdt); 910 911 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 912 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 913 rcar_io_emmc_setup(); 914 } else { 915 rcar_io_setup(); 916 } 917 } 918 919 void bl2_el3_plat_arch_setup(void) 920 { 921 #if RCAR_BL2_DCACHE == 1 922 NOTICE("BL2: D-Cache enable\n"); 923 rcar_configure_mmu_el3(BL2_BASE, 924 BL2_END - BL2_BASE, 925 BL2_RO_BASE, BL2_RO_LIMIT 926 #if USE_COHERENT_MEM 927 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 928 #endif /* USE_COHERENT_MEM */ 929 ); 930 #endif /* RCAR_BL2_DCACHE == 1 */ 931 } 932 933 void bl2_platform_setup(void) 934 { 935 /* 936 * Place holder for performing any platform initialization specific 937 * to BL2. 938 */ 939 } 940 941 static void bl2_init_generic_timer(void) 942 { 943 uint32_t reg_cntfid; 944 uint32_t modemr; 945 uint32_t modemr_pll; 946 uint32_t pll_table[] = { 947 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 948 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 949 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 950 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 951 }; 952 953 modemr = mmio_read_32(RCAR_MODEMR); 954 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 955 956 /* Set frequency data in CNTFID0 */ 957 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 958 959 /* Update memory mapped and register based frequency */ 960 write_cntfrq_el0((u_register_t)reg_cntfid); 961 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 962 /* Enable counter */ 963 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 964 (uint32_t)CNTCR_EN); 965 } 966