1 /* 2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <stdint.h> 9 #include <string.h> 10 #include <stdio.h> 11 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 15 #include "ddr_regdef.h" 16 #include "init_dram_tbl_h3.h" 17 #include "init_dram_tbl_m3.h" 18 #include "init_dram_tbl_h3ver2.h" 19 #include "init_dram_tbl_m3n.h" 20 #include "boot_init_dram_regdef.h" 21 #include "boot_init_dram.h" 22 #include "dram_sub_func.h" 23 #include "micro_delay.h" 24 #include "rcar_def.h" 25 26 #define DDR_BACKUPMODE 27 #define FATAL_MSG(x) NOTICE(x) 28 29 /* variables */ 30 #ifdef RCAR_DDR_FIXED_LSI_TYPE 31 #ifndef RCAR_AUTO 32 #define RCAR_AUTO 99 33 #define RCAR_H3 0 34 #define RCAR_M3 1 35 #define RCAR_M3N 2 36 #define RCAR_E3 3 /* NON */ 37 #define RCAR_H3N 4 38 39 #define RZ_G2M 100U 40 #define RZ_G2H 101U 41 42 #define RCAR_CUT_10 0 43 #define RCAR_CUT_11 1 44 #define RCAR_CUT_20 10 45 #define RCAR_CUT_30 20 46 #endif 47 #ifndef RCAR_LSI 48 #define RCAR_LSI RCAR_AUTO 49 #endif 50 51 #if (RCAR_LSI == RCAR_AUTO) 52 static uint32_t prr_product; 53 static uint32_t prr_cut; 54 #else 55 #if (RCAR_LSI == RCAR_H3) 56 static const uint32_t prr_product = PRR_PRODUCT_H3; 57 #elif(RCAR_LSI == RCAR_M3 || RCAR_LSI == RZ_G2M) 58 static const uint32_t prr_product = PRR_PRODUCT_M3; 59 #elif(RCAR_LSI == RCAR_M3N) 60 static const uint32_t prr_product = PRR_PRODUCT_M3N; 61 #elif(RCAR_LSI == RCAR_H3N || RCAR_LSI == RZ_G2H) 62 static const uint32_t prr_product = PRR_PRODUCT_H3; 63 #endif /* RCAR_LSI */ 64 65 #ifndef RCAR_LSI_CUT 66 static uint32_t prr_cut; 67 #else /* RCAR_LSI_CUT */ 68 #if (RCAR_LSI_CUT == RCAR_CUT_10) 69 static const uint32_t prr_cut = PRR_PRODUCT_10; 70 #elif(RCAR_LSI_CUT == RCAR_CUT_11) 71 static const uint32_t prr_cut = PRR_PRODUCT_11; 72 #elif(RCAR_LSI_CUT == RCAR_CUT_20) 73 static const uint32_t prr_cut = PRR_PRODUCT_20; 74 #elif(RCAR_LSI_CUT == RCAR_CUT_30) 75 static const uint32_t prr_cut = PRR_PRODUCT_30; 76 #endif /* RCAR_LSI_CUT */ 77 #endif /* RCAR_LSI_CUT */ 78 #endif /* RCAR_AUTO_NON */ 79 #else /* RCAR_DDR_FIXED_LSI_TYPE */ 80 static uint32_t prr_product; 81 static uint32_t prr_cut; 82 #endif /* RCAR_DDR_FIXED_LSI_TYPE */ 83 84 static const uint32_t *p_ddr_regdef_tbl; 85 static uint32_t brd_clk; 86 static uint32_t brd_clkdiv; 87 static uint32_t brd_clkdiva; 88 static uint32_t ddr_mbps; 89 static uint32_t ddr_mbpsdiv; 90 static uint32_t ddr_tccd; 91 static uint32_t ddr_phycaslice; 92 static const struct _boardcnf *board_cnf; 93 static uint32_t ddr_phyvalid; 94 static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; 95 static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); 96 static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9]; 97 static uint32_t max_density; 98 static uint32_t ddr0800_mul; 99 static uint32_t ddr_mul; 100 static uint32_t DDR_PHY_SLICE_REGSET_OFS; 101 static uint32_t DDR_PHY_ADR_V_REGSET_OFS; 102 static uint32_t DDR_PHY_ADR_I_REGSET_OFS; 103 static uint32_t DDR_PHY_ADR_G_REGSET_OFS; 104 static uint32_t DDR_PI_REGSET_OFS; 105 static uint32_t DDR_PHY_SLICE_REGSET_SIZE; 106 static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; 107 static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; 108 static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; 109 static uint32_t DDR_PI_REGSET_SIZE; 110 static uint32_t DDR_PHY_SLICE_REGSET_NUM; 111 static uint32_t DDR_PHY_ADR_V_REGSET_NUM; 112 static uint32_t DDR_PHY_ADR_I_REGSET_NUM; 113 static uint32_t DDR_PHY_ADR_G_REGSET_NUM; 114 static uint32_t DDR_PI_REGSET_NUM; 115 static uint32_t DDR_PHY_ADR_I_NUM; 116 #define DDR_PHY_REGSET_MAX 128 117 #define DDR_PI_REGSET_MAX 320 118 static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; 119 static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; 120 static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; 121 static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; 122 static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; 123 static uint32_t pll3_mode; 124 static uint32_t loop_max; 125 #ifdef DDR_BACKUPMODE 126 uint32_t ddr_backup; 127 /* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ 128 #endif 129 130 #ifdef ddr_qos_init_setting /* only for non qos_init */ 131 #define OPERATING_FREQ (400U) /* Mhz */ 132 #define BASE_SUB_SLOT_NUM (0x6U) 133 #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ 134 #define QOSWT_WTSET0_CYCLE \ 135 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \ 136 OPERATING_FREQ) /* unit:ns */ 137 138 uint32_t get_refperiod(void) 139 { 140 return QOSWT_WTSET0_CYCLE; 141 } 142 #else /* ddr_qos_init_setting // only for non qos_init */ 143 extern uint32_t get_refperiod(void); 144 #endif /* ddr_qos_init_setting // only for non qos_init */ 145 146 #define _reg_PHY_RX_CAL_X_NUM 11 147 static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { 148 _reg_PHY_RX_CAL_DQ0, 149 _reg_PHY_RX_CAL_DQ1, 150 _reg_PHY_RX_CAL_DQ2, 151 _reg_PHY_RX_CAL_DQ3, 152 _reg_PHY_RX_CAL_DQ4, 153 _reg_PHY_RX_CAL_DQ5, 154 _reg_PHY_RX_CAL_DQ6, 155 _reg_PHY_RX_CAL_DQ7, 156 _reg_PHY_RX_CAL_DM, 157 _reg_PHY_RX_CAL_DQS, 158 _reg_PHY_RX_CAL_FDBK 159 }; 160 161 #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 162 static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY 163 [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { 164 _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, 165 _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, 166 _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, 167 _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, 168 _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, 169 _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, 170 _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, 171 _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, 172 _reg_PHY_CLK_WRDM_SLAVE_DELAY, 173 _reg_PHY_CLK_WRDQS_SLAVE_DELAY 174 }; 175 176 #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 177 static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY 178 [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { 179 _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, 180 _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, 181 _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, 182 _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, 183 _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, 184 _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, 185 _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, 186 _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, 187 _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 188 }; 189 190 #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 191 static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 192 [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { 193 _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, 194 _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, 195 _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, 196 _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, 197 _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, 198 _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, 199 _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, 200 _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, 201 _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 202 }; 203 204 #define _reg_PHY_PAD_TERM_X_NUM 8 205 static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { 206 _reg_PHY_PAD_FDBK_TERM, 207 _reg_PHY_PAD_DATA_TERM, 208 _reg_PHY_PAD_DQS_TERM, 209 _reg_PHY_PAD_ADDR_TERM, 210 _reg_PHY_PAD_CLK_TERM, 211 _reg_PHY_PAD_CKE_TERM, 212 _reg_PHY_PAD_RST_TERM, 213 _reg_PHY_PAD_CS_TERM 214 }; 215 216 #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 217 static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X 218 [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { 219 _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, 220 _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, 221 _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, 222 _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, 223 _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, 224 _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, 225 226 _reg_PHY_GRP_SLAVE_DELAY_0, 227 _reg_PHY_GRP_SLAVE_DELAY_1, 228 _reg_PHY_GRP_SLAVE_DELAY_2, 229 _reg_PHY_GRP_SLAVE_DELAY_3 230 }; 231 232 /* Prototypes */ 233 static inline uint32_t vch_nxt(uint32_t pos); 234 static void cpg_write_32(uint32_t a, uint32_t v); 235 static void pll3_control(uint32_t high); 236 static inline void dsb_sev(void); 237 static void wait_dbcmd(void); 238 static void send_dbcmd(uint32_t cmd); 239 static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); 240 static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); 241 static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); 242 static inline uint32_t ddr_regdef(uint32_t _regdef); 243 static inline uint32_t ddr_regdef_adr(uint32_t _regdef); 244 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); 245 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, 246 uint32_t val); 247 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); 248 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); 249 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); 250 static void ddr_setval_ach(uint32_t regdef, uint32_t val); 251 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); 252 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); 253 static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); 254 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); 255 static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); 256 static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); 257 static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); 258 static uint32_t ddrphy_regif_chk(void); 259 static inline void ddrphy_regif_idle(void); 260 static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, 261 uint16_t cyc); 262 static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, 263 uint16_t *_js2); 264 static int16_t _f_scale_adj(int16_t ps); 265 static void ddrtbl_load(void); 266 static void ddr_config_sub(void); 267 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); 268 static void ddr_config_sub_h3v1x(void); 269 static void ddr_config(void); 270 static void dbsc_regset(void); 271 static void dbsc_regset_post(void); 272 static uint32_t dfi_init_start(void); 273 static void change_lpddr4_en(uint32_t mode); 274 static uint32_t set_term_code(void); 275 static void ddr_register_set(void); 276 static inline uint32_t wait_freqchgreq(uint32_t assert); 277 static inline void set_freqchgack(uint32_t assert); 278 static inline void set_dfifrequency(uint32_t freq); 279 static uint32_t pll3_freq(uint32_t on); 280 static void update_dly(void); 281 static uint32_t pi_training_go(void); 282 static uint32_t init_ddr(void); 283 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); 284 static uint32_t wdqdm_man1(void); 285 static uint32_t wdqdm_man(void); 286 static uint32_t rdqdm_man1(void); 287 static uint32_t rdqdm_man(void); 288 289 static int32_t _find_change(uint64_t val, uint32_t dir); 290 static uint32_t _rx_offset_cal_updn(uint32_t code); 291 static uint32_t rx_offset_cal(void); 292 static uint32_t rx_offset_cal_hw(void); 293 static void adjust_rddqs_latency(void); 294 static void adjust_wpath_latency(void); 295 296 struct ddrt_data { 297 int32_t init_temp; /* Initial Temperature (do) */ 298 uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ 299 uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */ 300 }; 301 302 static struct ddrt_data tcal; 303 304 static void pvtcode_update(void); 305 static void pvtcode_update2(void); 306 static void ddr_padcal_tcompensate_getinit(uint32_t override); 307 308 /* load board configuration */ 309 #include "boot_init_dram_config.c" 310 311 #ifndef DDR_FAST_INIT 312 static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 313 static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 314 static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 315 static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 316 static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; 317 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); 318 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); 319 320 static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 321 static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 322 static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 323 static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 324 static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 325 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); 326 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); 327 #endif/* DDR_FAST_INIT */ 328 329 /* macro for channel selection loop */ 330 static inline uint32_t vch_nxt(uint32_t pos) 331 { 332 uint32_t posn; 333 334 for (posn = pos; posn < DRAM_CH_CNT; posn++) { 335 if (ddr_phyvalid & (1U << posn)) 336 break; 337 } 338 return posn; 339 } 340 341 #define foreach_vch(ch) \ 342 for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) 343 344 #define foreach_ech(ch) \ 345 for (ch = 0; ch < DRAM_CH_CNT; ch++) 346 347 /* Printing functions */ 348 #define MSG_LF(...) 349 350 /* clock settings, reset control */ 351 static void cpg_write_32(uint32_t a, uint32_t v) 352 { 353 mmio_write_32(CPG_CPGWPR, ~v); 354 mmio_write_32(a, v); 355 } 356 357 static void pll3_control(uint32_t high) 358 { 359 uint32_t data_l, data_div, data_mul, tmp_div; 360 361 if (high) { 362 tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / 363 (brd_clk * ddr_mul) / 2; 364 data_mul = ((ddr_mul * tmp_div) - 1) << 24; 365 pll3_mode = 1; 366 loop_max = 2; 367 } else { 368 tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / 369 (brd_clk * ddr0800_mul) / 2; 370 data_mul = ((ddr0800_mul * tmp_div) - 1) << 24; 371 pll3_mode = 0; 372 loop_max = 8; 373 } 374 375 switch (tmp_div) { 376 case 1: 377 data_div = 0; 378 break; 379 case 2: 380 case 3: 381 case 4: 382 data_div = tmp_div; 383 break; 384 default: 385 data_div = 6; 386 data_mul = (data_mul * tmp_div) / 3; 387 break; 388 } 389 data_mul = data_mul | (brd_clkdiva << 7); 390 391 /* PLL3 disable */ 392 data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; 393 cpg_write_32(CPG_PLLECR, data_l); 394 dsb_sev(); 395 396 if ((prr_product == PRR_PRODUCT_M3) || 397 ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) { 398 /* PLL3 DIV resetting(Lowest value:3) */ 399 data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); 400 cpg_write_32(CPG_FRQCRD, data_l); 401 dsb_sev(); 402 403 /* zb3 clk stop */ 404 data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); 405 cpg_write_32(CPG_ZB3CKCR, data_l); 406 dsb_sev(); 407 408 /* PLL3 enable */ 409 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); 410 cpg_write_32(CPG_PLLECR, data_l); 411 dsb_sev(); 412 413 do { 414 data_l = mmio_read_32(CPG_PLLECR); 415 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 416 dsb_sev(); 417 418 /* PLL3 DIV resetting (Highest value:0) */ 419 data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); 420 cpg_write_32(CPG_FRQCRD, data_l); 421 dsb_sev(); 422 423 /* DIV SET KICK */ 424 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 425 cpg_write_32(CPG_FRQCRB, data_l); 426 dsb_sev(); 427 428 /* PLL3 multiplie set */ 429 cpg_write_32(CPG_PLL3CR, data_mul); 430 dsb_sev(); 431 432 do { 433 data_l = mmio_read_32(CPG_PLLECR); 434 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 435 dsb_sev(); 436 437 /* PLL3 DIV resetting(Target value) */ 438 data_l = (data_div << 16) | data_div | 439 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); 440 cpg_write_32(CPG_FRQCRD, data_l); 441 dsb_sev(); 442 443 /* DIV SET KICK */ 444 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 445 cpg_write_32(CPG_FRQCRB, data_l); 446 dsb_sev(); 447 448 do { 449 data_l = mmio_read_32(CPG_PLLECR); 450 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 451 dsb_sev(); 452 453 /* zb3 clk start */ 454 data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); 455 cpg_write_32(CPG_ZB3CKCR, data_l); 456 dsb_sev(); 457 458 } else { /* H3Ver.3.0/M3N/V3H */ 459 460 /* PLL3 multiplie set */ 461 cpg_write_32(CPG_PLL3CR, data_mul); 462 dsb_sev(); 463 464 /* PLL3 DIV set(Target value) */ 465 data_l = (data_div << 16) | data_div | 466 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); 467 cpg_write_32(CPG_FRQCRD, data_l); 468 469 /* DIV SET KICK */ 470 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 471 cpg_write_32(CPG_FRQCRB, data_l); 472 dsb_sev(); 473 474 /* PLL3 enable */ 475 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); 476 cpg_write_32(CPG_PLLECR, data_l); 477 dsb_sev(); 478 479 do { 480 data_l = mmio_read_32(CPG_PLLECR); 481 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 482 dsb_sev(); 483 } 484 } 485 486 /* barrier */ 487 static inline void dsb_sev(void) 488 { 489 __asm__ __volatile__("dsb sy"); 490 } 491 492 /* DDR memory register access */ 493 static void wait_dbcmd(void) 494 { 495 uint32_t data_l; 496 /* dummy read */ 497 data_l = mmio_read_32(DBSC_DBCMD); 498 dsb_sev(); 499 while (1) { 500 /* wait DBCMD 1=busy, 0=ready */ 501 data_l = mmio_read_32(DBSC_DBWAIT); 502 dsb_sev(); 503 if ((data_l & 0x00000001) == 0x00) 504 break; 505 } 506 } 507 508 static void send_dbcmd(uint32_t cmd) 509 { 510 /* dummy read */ 511 wait_dbcmd(); 512 mmio_write_32(DBSC_DBCMD, cmd); 513 dsb_sev(); 514 } 515 516 static void dbwait_loop(uint32_t wait_loop) 517 { 518 uint32_t i; 519 520 for (i = 0; i < wait_loop; i++) 521 wait_dbcmd(); 522 } 523 524 /* DDRPHY register access (raw) */ 525 static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) 526 { 527 uint32_t val; 528 uint32_t loop; 529 530 val = 0; 531 if ((prr_product != PRR_PRODUCT_M3N) && 532 (prr_product != PRR_PRODUCT_V3H)) { 533 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 534 dsb_sev(); 535 536 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 537 dsb_sev(); 538 } 539 dsb_sev(); 540 541 for (loop = 0; loop < loop_max; loop++) { 542 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 543 dsb_sev(); 544 } 545 (void)val; 546 } else { 547 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); 548 dsb_sev(); 549 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != 550 (regadd | 0x0000C000)) { 551 dsb_sev(); 552 }; 553 val = mmio_read_32(DBSC_DBPDRGA(phyno)); 554 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 555 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 556 dsb_sev(); 557 }; 558 dsb_sev(); 559 560 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 561 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 562 dsb_sev(); 563 }; 564 565 dsb_sev(); 566 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 567 dsb_sev(); 568 (void)val; 569 } 570 return val; 571 } 572 573 static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) 574 { 575 uint32_t val; 576 uint32_t loop; 577 578 if ((prr_product != PRR_PRODUCT_M3N) && 579 (prr_product != PRR_PRODUCT_V3H)) { 580 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 581 dsb_sev(); 582 for (loop = 0; loop < loop_max; loop++) { 583 val = mmio_read_32(DBSC_DBPDRGA(phyno)); 584 dsb_sev(); 585 } 586 mmio_write_32(DBSC_DBPDRGD(phyno), regdata); 587 dsb_sev(); 588 589 for (loop = 0; loop < loop_max; loop++) { 590 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 591 dsb_sev(); 592 } 593 } else { 594 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 595 dsb_sev(); 596 597 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 598 dsb_sev(); 599 }; 600 dsb_sev(); 601 602 mmio_write_32(DBSC_DBPDRGD(phyno), regdata); 603 dsb_sev(); 604 605 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != 606 (regadd | 0x00008000)) { 607 dsb_sev(); 608 }; 609 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 610 611 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 612 dsb_sev(); 613 }; 614 dsb_sev(); 615 616 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 617 } 618 (void)val; 619 } 620 621 static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) 622 { 623 uint32_t ch; 624 uint32_t val; 625 uint32_t loop; 626 627 if ((prr_product != PRR_PRODUCT_M3N) && 628 (prr_product != PRR_PRODUCT_V3H)) { 629 foreach_vch(ch) { 630 mmio_write_32(DBSC_DBPDRGA(ch), regadd); 631 dsb_sev(); 632 } 633 634 foreach_vch(ch) { 635 mmio_write_32(DBSC_DBPDRGD(ch), regdata); 636 dsb_sev(); 637 } 638 639 for (loop = 0; loop < loop_max; loop++) { 640 val = mmio_read_32(DBSC_DBPDRGD(0)); 641 dsb_sev(); 642 } 643 (void)val; 644 } else { 645 foreach_vch(ch) { 646 reg_ddrphy_write(ch, regadd, regdata); 647 dsb_sev(); 648 } 649 } 650 } 651 652 static inline void ddrphy_regif_idle(void) 653 { 654 uint32_t val; 655 656 val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); 657 dsb_sev(); 658 (void)val; 659 } 660 661 /* DDRPHY register access (field modify) */ 662 static inline uint32_t ddr_regdef(uint32_t _regdef) 663 { 664 return p_ddr_regdef_tbl[_regdef]; 665 } 666 667 static inline uint32_t ddr_regdef_adr(uint32_t _regdef) 668 { 669 return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]); 670 } 671 672 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) 673 { 674 return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]); 675 } 676 677 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, 678 uint32_t val) 679 { 680 uint32_t adr; 681 uint32_t lsb; 682 uint32_t len; 683 uint32_t msk; 684 uint32_t tmp; 685 uint32_t regdef; 686 687 regdef = ddr_regdef(_regdef); 688 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; 689 len = DDR_REGDEF_LEN(regdef); 690 lsb = DDR_REGDEF_LSB(regdef); 691 if (len == 0x20) 692 msk = 0xffffffff; 693 else 694 msk = ((1U << len) - 1) << lsb; 695 696 tmp = reg_ddrphy_read(ch, adr); 697 tmp = (tmp & (~msk)) | ((val << lsb) & msk); 698 reg_ddrphy_write(ch, adr, tmp); 699 } 700 701 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) 702 { 703 uint32_t adr; 704 uint32_t lsb; 705 uint32_t len; 706 uint32_t msk; 707 uint32_t tmp; 708 uint32_t regdef; 709 710 regdef = ddr_regdef(_regdef); 711 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; 712 len = DDR_REGDEF_LEN(regdef); 713 lsb = DDR_REGDEF_LSB(regdef); 714 if (len == 0x20) 715 msk = 0xffffffff; 716 else 717 msk = ((1U << len) - 1); 718 719 tmp = reg_ddrphy_read(ch, adr); 720 tmp = (tmp >> lsb) & msk; 721 722 return tmp; 723 } 724 725 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) 726 { 727 ddr_setval_s(ch, 0, regdef, val); 728 } 729 730 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) 731 { 732 uint32_t ch; 733 734 foreach_vch(ch) 735 ddr_setval_s(ch, slice, regdef, val); 736 } 737 738 static void ddr_setval_ach(uint32_t regdef, uint32_t val) 739 { 740 ddr_setval_ach_s(0, regdef, val); 741 } 742 743 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) 744 { 745 uint32_t slice; 746 747 for (slice = 0; slice < SLICE_CNT; slice++) 748 ddr_setval_ach_s(slice, regdef, val); 749 } 750 751 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) 752 { 753 return ddr_getval_s(ch, 0, regdef); 754 } 755 756 static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p) 757 { 758 uint32_t ch; 759 760 foreach_vch(ch) 761 p[ch] = ddr_getval_s(ch, 0, regdef); 762 return p[0]; 763 } 764 765 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) 766 { 767 uint32_t ch, slice; 768 uint32_t *pp; 769 770 pp = p; 771 foreach_vch(ch) 772 for (slice = 0; slice < SLICE_CNT; slice++) 773 *pp++ = ddr_getval_s(ch, slice, regdef); 774 return p[0]; 775 } 776 777 /* handling functions for setteing ddrphy value table */ 778 static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) 779 { 780 uint32_t i; 781 782 for (i = 0; i < size; i++) { 783 to[i] = from[i]; 784 } 785 } 786 787 static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) 788 { 789 uint32_t adr; 790 uint32_t lsb; 791 uint32_t len; 792 uint32_t msk; 793 uint32_t tmp; 794 uint32_t adrmsk; 795 uint32_t regdef; 796 797 regdef = ddr_regdef(_regdef); 798 adr = DDR_REGDEF_ADR(regdef); 799 len = DDR_REGDEF_LEN(regdef); 800 lsb = DDR_REGDEF_LSB(regdef); 801 if (len == 0x20) 802 msk = 0xffffffff; 803 else 804 msk = ((1U << len) - 1) << lsb; 805 806 if (adr < 0x400) { 807 adrmsk = 0xff; 808 } else { 809 adrmsk = 0x7f; 810 } 811 812 tmp = tbl[adr & adrmsk]; 813 tmp = (tmp & (~msk)) | ((val << lsb) & msk); 814 tbl[adr & adrmsk] = tmp; 815 } 816 817 static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) 818 { 819 uint32_t adr; 820 uint32_t lsb; 821 uint32_t len; 822 uint32_t msk; 823 uint32_t tmp; 824 uint32_t adrmsk; 825 uint32_t regdef; 826 827 regdef = ddr_regdef(_regdef); 828 adr = DDR_REGDEF_ADR(regdef); 829 len = DDR_REGDEF_LEN(regdef); 830 lsb = DDR_REGDEF_LSB(regdef); 831 if (len == 0x20) 832 msk = 0xffffffff; 833 else 834 msk = ((1U << len) - 1); 835 836 if (adr < 0x400) { 837 adrmsk = 0xff; 838 } else { 839 adrmsk = 0x7f; 840 } 841 842 tmp = tbl[adr & adrmsk]; 843 tmp = (tmp >> lsb) & msk; 844 845 return tmp; 846 } 847 848 /* DDRPHY register access handling */ 849 static uint32_t ddrphy_regif_chk(void) 850 { 851 uint32_t tmp_ach[DRAM_CH_CNT]; 852 uint32_t ch; 853 uint32_t err; 854 uint32_t PI_VERSION_CODE; 855 856 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 857 (prr_product == PRR_PRODUCT_M3)) { 858 PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ 859 } else { 860 PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ 861 } 862 863 ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); 864 err = 0; 865 foreach_vch(ch) { 866 if (tmp_ach[ch] != PI_VERSION_CODE) 867 err = 1; 868 } 869 return err; 870 } 871 872 /* functions and parameters for timing setting */ 873 struct _jedec_spec1 { 874 uint16_t fx3; 875 uint8_t rlwodbi; 876 uint8_t rlwdbi; 877 uint8_t WL; 878 uint8_t nwr; 879 uint8_t nrtp; 880 uint8_t odtlon; 881 uint8_t MR1; 882 uint8_t MR2; 883 }; 884 885 #define JS1_USABLEC_SPEC_LO 2 886 #define JS1_USABLEC_SPEC_HI 5 887 #define JS1_FREQ_TBL_NUM 8 888 #define JS1_MR1(f) (0x04 | ((f) << 4)) 889 #define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) 890 const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { 891 /* 533.333Mbps */ 892 { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 }, 893 /* 1066.666Mbps */ 894 { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 }, 895 /* 1600.000Mbps */ 896 { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 }, 897 /* 2133.333Mbps */ 898 { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) }, 899 /* 2666.666Mbps */ 900 { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) }, 901 /* 3200.000Mbps */ 902 { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) }, 903 /* 3733.333Mbps */ 904 { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) }, 905 /* 4266.666Mbps */ 906 { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) } 907 }; 908 909 struct _jedec_spec2 { 910 uint16_t ps; 911 uint16_t cyc; 912 }; 913 914 #define js2_tsr 0 915 #define js2_txp 1 916 #define js2_trtp 2 917 #define js2_trcd 3 918 #define js2_trppb 4 919 #define js2_trpab 5 920 #define js2_tras 6 921 #define js2_twr 7 922 #define js2_twtr 8 923 #define js2_trrd 9 924 #define js2_tppd 10 925 #define js2_tfaw 11 926 #define js2_tdqsck 12 927 #define js2_tckehcmd 13 928 #define js2_tckelcmd 14 929 #define js2_tckelpd 15 930 #define js2_tmrr 16 931 #define js2_tmrw 17 932 #define js2_tmrd 18 933 #define js2_tzqcalns 19 934 #define js2_tzqlat 20 935 #define js2_tiedly 21 936 #define js2_tODTon_min 22 937 #define JS2_TBLCNT 23 938 939 #define js2_trcpb (JS2_TBLCNT) 940 #define js2_trcab (JS2_TBLCNT + 1) 941 #define js2_trfcab (JS2_TBLCNT + 2) 942 #define JS2_CNT (JS2_TBLCNT + 3) 943 944 #ifndef JS2_DERATE 945 #define JS2_DERATE 0 946 #endif 947 const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { 948 { 949 /*tSR */ {15000, 3}, 950 /*tXP */ {7500, 3}, 951 /*tRTP */ {7500, 8}, 952 /*tRCD */ {18000, 4}, 953 /*tRPpb */ {18000, 3}, 954 /*tRPab */ {21000, 3}, 955 /*tRAS */ {42000, 3}, 956 /*tWR */ {18000, 4}, 957 /*tWTR */ {10000, 8}, 958 /*tRRD */ {10000, 4}, 959 /*tPPD */ {0, 0}, 960 /*tFAW */ {40000, 0}, 961 /*tDQSCK*/ {3500, 0}, 962 /*tCKEHCMD*/ {7500, 3}, 963 /*tCKELCMD*/ {7500, 3}, 964 /*tCKELPD*/ {7500, 3}, 965 /*tMRR*/ {0, 8}, 966 /*tMRW*/ {10000, 10}, 967 /*tMRD*/ {14000, 10}, 968 /*tZQCALns*/ {1000 * 10, 0}, 969 /*tZQLAT*/ {30000, 10}, 970 /*tIEdly*/ {12500, 0}, 971 /*tODTon_min*/ {1500, 0} 972 }, { 973 /*tSR */ {15000, 3}, 974 /*tXP */ {7500, 3}, 975 /*tRTP */ {7500, 8}, 976 /*tRCD */ {19875, 4}, 977 /*tRPpb */ {19875, 3}, 978 /*tRPab */ {22875, 3}, 979 /*tRAS */ {43875, 3}, 980 /*tWR */ {18000, 4}, 981 /*tWTR */ {10000, 8}, 982 /*tRRD */ {11875, 4}, 983 /*tPPD */ {0, 0}, 984 /*tFAW */ {40000, 0}, 985 /*tDQSCK*/ {3600, 0}, 986 /*tCKEHCMD*/ {7500, 3}, 987 /*tCKELCMD*/ {7500, 3}, 988 /*tCKELPD*/ {7500, 3}, 989 /*tMRR*/ {0, 8}, 990 /*tMRW*/ {10000, 10}, 991 /*tMRD*/ {14000, 10}, 992 /*tZQCALns*/ {1000 * 10, 0}, 993 /*tZQLAT*/ {30000, 10}, 994 /*tIEdly*/ {12500, 0}, 995 /*tODTon_min*/ {1500, 0} 996 } 997 }; 998 999 const uint16_t jedec_spec2_trfc_ab[7] = { 1000 /* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ 1001 130, 180, 180, 280, 280, 560, 560 1002 }; 1003 1004 static uint32_t js1_ind; 1005 static uint16_t js2[JS2_CNT]; 1006 static uint8_t RL; 1007 static uint8_t WL; 1008 1009 static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, 1010 uint16_t cyc) 1011 { 1012 uint32_t tmp; 1013 uint32_t div; 1014 1015 tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps; 1016 div = tmp / (200000 * _ddr_mbpsdiv); 1017 if (tmp != (div * 200000 * _ddr_mbpsdiv)) 1018 div = div + 1; 1019 1020 if (div > cyc) 1021 return (uint16_t)div; 1022 return cyc; 1023 } 1024 1025 static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, 1026 uint16_t *_js2) 1027 { 1028 int i; 1029 1030 for (i = 0; i < JS2_TBLCNT; i++) { 1031 _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv, 1032 1UL * jedec_spec2[JS2_DERATE][i].ps, 1033 jedec_spec2[JS2_DERATE][i].cyc); 1034 } 1035 1036 _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb]; 1037 _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab]; 1038 } 1039 1040 /* scaler for DELAY value */ 1041 static int16_t _f_scale_adj(int16_t ps) 1042 { 1043 int32_t tmp; 1044 /* 1045 * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; 1046 * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 1047 * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 1048 */ 1049 tmp = 1050 (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / 1051 (int32_t)ddr_mbpsdiv; 1052 tmp = (int32_t)tmp / (int32_t)15625; 1053 1054 return (int16_t)tmp; 1055 } 1056 1057 static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = { 1058 { 1059 _reg_PI_MR1_DATA_F0_0, 1060 _reg_PI_MR1_DATA_F0_1, 1061 _reg_PI_MR1_DATA_F0_2, 1062 _reg_PI_MR1_DATA_F0_3}, 1063 { 1064 _reg_PI_MR1_DATA_F1_0, 1065 _reg_PI_MR1_DATA_F1_1, 1066 _reg_PI_MR1_DATA_F1_2, 1067 _reg_PI_MR1_DATA_F1_3} 1068 }; 1069 1070 static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = { 1071 { 1072 _reg_PI_MR2_DATA_F0_0, 1073 _reg_PI_MR2_DATA_F0_1, 1074 _reg_PI_MR2_DATA_F0_2, 1075 _reg_PI_MR2_DATA_F0_3}, 1076 { 1077 _reg_PI_MR2_DATA_F1_0, 1078 _reg_PI_MR2_DATA_F1_1, 1079 _reg_PI_MR2_DATA_F1_2, 1080 _reg_PI_MR2_DATA_F1_3} 1081 }; 1082 1083 static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = { 1084 { 1085 _reg_PI_MR3_DATA_F0_0, 1086 _reg_PI_MR3_DATA_F0_1, 1087 _reg_PI_MR3_DATA_F0_2, 1088 _reg_PI_MR3_DATA_F0_3}, 1089 { 1090 _reg_PI_MR3_DATA_F1_0, 1091 _reg_PI_MR3_DATA_F1_1, 1092 _reg_PI_MR3_DATA_F1_2, 1093 _reg_PI_MR3_DATA_F1_3} 1094 }; 1095 1096 const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = { 1097 { 1098 _reg_PI_MR11_DATA_F0_0, 1099 _reg_PI_MR11_DATA_F0_1, 1100 _reg_PI_MR11_DATA_F0_2, 1101 _reg_PI_MR11_DATA_F0_3}, 1102 { 1103 _reg_PI_MR11_DATA_F1_0, 1104 _reg_PI_MR11_DATA_F1_1, 1105 _reg_PI_MR11_DATA_F1_2, 1106 _reg_PI_MR11_DATA_F1_3} 1107 }; 1108 1109 const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = { 1110 { 1111 _reg_PI_MR12_DATA_F0_0, 1112 _reg_PI_MR12_DATA_F0_1, 1113 _reg_PI_MR12_DATA_F0_2, 1114 _reg_PI_MR12_DATA_F0_3}, 1115 { 1116 _reg_PI_MR12_DATA_F1_0, 1117 _reg_PI_MR12_DATA_F1_1, 1118 _reg_PI_MR12_DATA_F1_2, 1119 _reg_PI_MR12_DATA_F1_3} 1120 }; 1121 1122 const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { 1123 { 1124 _reg_PI_MR14_DATA_F0_0, 1125 _reg_PI_MR14_DATA_F0_1, 1126 _reg_PI_MR14_DATA_F0_2, 1127 _reg_PI_MR14_DATA_F0_3}, 1128 { 1129 _reg_PI_MR14_DATA_F1_0, 1130 _reg_PI_MR14_DATA_F1_1, 1131 _reg_PI_MR14_DATA_F1_2, 1132 _reg_PI_MR14_DATA_F1_3} 1133 }; 1134 1135 /* 1136 * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) 1137 */ 1138 static void regif_pll_wa(void) 1139 { 1140 uint32_t ch; 1141 1142 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1143 // PLL setting for PHY : H3 Ver.1.x 1144 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), 1145 (0x0064U << 1146 ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); 1147 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 1148 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1149 _reg_PHY_PLL_CTRL)); 1150 1151 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), 1152 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1153 _reg_PHY_LP4_BOOT_PLL_CTRL)); 1154 1155 } else { 1156 /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ 1157 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), 1158 (0x5064U << 1159 ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); 1160 1161 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 1162 (ddrtbl_getval 1163 (_cnf_DDR_PHY_ADR_G_REGSET, 1164 _reg_PHY_PLL_CTRL_TOP) << 16) | 1165 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1166 _reg_PHY_PLL_CTRL)); 1167 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 1168 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1169 _reg_PHY_PLL_CTRL_CA)); 1170 1171 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), 1172 (ddrtbl_getval 1173 (_cnf_DDR_PHY_ADR_G_REGSET, 1174 _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | 1175 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1176 _reg_PHY_LP4_BOOT_PLL_CTRL)); 1177 reg_ddrphy_write_a(ddr_regdef_adr 1178 (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), 1179 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1180 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 1181 )); 1182 } 1183 1184 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), 1185 _cnf_DDR_PHY_ADR_G_REGSET 1186 [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - 1187 DDR_PHY_ADR_G_REGSET_OFS]); 1188 1189 /* protect register interface */ 1190 ddrphy_regif_idle(); 1191 pll3_control(0); 1192 1193 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1194 /* non */ 1195 } else { 1196 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), 1197 (0x01U << 1198 ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); 1199 ddrphy_regif_idle(); 1200 } 1201 1202 /* init start */ 1203 /* dbdficnt0: 1204 * dfi_dram_clk_disable=1 1205 * dfi_frequency = 0 1206 * freq_ratio = 01 (2:1) 1207 * init_start =0 1208 */ 1209 foreach_vch(ch) 1210 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); 1211 dsb_sev(); 1212 1213 /* dbdficnt0: 1214 * dfi_dram_clk_disable=1 1215 * dfi_frequency = 0 1216 * freq_ratio = 01 (2:1) 1217 * init_start =1 1218 */ 1219 foreach_vch(ch) 1220 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); 1221 dsb_sev(); 1222 1223 foreach_ech(ch) 1224 if ((board_cnf->phyvalid) & BIT(ch)) 1225 while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) 1226 ; 1227 dsb_sev(); 1228 } 1229 1230 /* load table data into DDR registers */ 1231 static void ddrtbl_load(void) 1232 { 1233 uint32_t i; 1234 uint32_t slice; 1235 uint32_t csab; 1236 uint32_t adr; 1237 uint32_t data_l; 1238 uint32_t tmp[3]; 1239 uint16_t dataS; 1240 1241 /* TIMING REGISTERS */ 1242 /* search jedec_spec1 index */ 1243 for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { 1244 if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) 1245 break; 1246 } 1247 if (i > JS1_USABLEC_SPEC_HI) 1248 js1_ind = JS1_USABLEC_SPEC_HI; 1249 else 1250 js1_ind = i; 1251 1252 if (board_cnf->dbi_en) 1253 RL = js1[js1_ind].rlwdbi; 1254 else 1255 RL = js1[js1_ind].rlwodbi; 1256 1257 WL = js1[js1_ind].WL; 1258 1259 /* calculate jedec_spec2 */ 1260 _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); 1261 1262 /* PREPARE TBL */ 1263 if (prr_product == PRR_PRODUCT_H3) { 1264 if (prr_cut <= PRR_PRODUCT_11) { 1265 /* H3 Ver.1.x */ 1266 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1267 DDR_PHY_SLICE_REGSET_H3, 1268 DDR_PHY_SLICE_REGSET_NUM_H3); 1269 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1270 DDR_PHY_ADR_V_REGSET_H3, 1271 DDR_PHY_ADR_V_REGSET_NUM_H3); 1272 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, 1273 DDR_PHY_ADR_I_REGSET_H3, 1274 DDR_PHY_ADR_I_REGSET_NUM_H3); 1275 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1276 DDR_PHY_ADR_G_REGSET_H3, 1277 DDR_PHY_ADR_G_REGSET_NUM_H3); 1278 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3, 1279 DDR_PI_REGSET_NUM_H3); 1280 1281 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3; 1282 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3; 1283 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3; 1284 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3; 1285 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3; 1286 DDR_PHY_SLICE_REGSET_SIZE = 1287 DDR_PHY_SLICE_REGSET_SIZE_H3; 1288 DDR_PHY_ADR_V_REGSET_SIZE = 1289 DDR_PHY_ADR_V_REGSET_SIZE_H3; 1290 DDR_PHY_ADR_I_REGSET_SIZE = 1291 DDR_PHY_ADR_I_REGSET_SIZE_H3; 1292 DDR_PHY_ADR_G_REGSET_SIZE = 1293 DDR_PHY_ADR_G_REGSET_SIZE_H3; 1294 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3; 1295 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3; 1296 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3; 1297 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3; 1298 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3; 1299 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3; 1300 1301 DDR_PHY_ADR_I_NUM = 1; 1302 } else { 1303 /* H3 Ver.2.0 or later */ 1304 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1305 DDR_PHY_SLICE_REGSET_H3VER2, 1306 DDR_PHY_SLICE_REGSET_NUM_H3VER2); 1307 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1308 DDR_PHY_ADR_V_REGSET_H3VER2, 1309 DDR_PHY_ADR_V_REGSET_NUM_H3VER2); 1310 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1311 DDR_PHY_ADR_G_REGSET_H3VER2, 1312 DDR_PHY_ADR_G_REGSET_NUM_H3VER2); 1313 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2, 1314 DDR_PI_REGSET_NUM_H3VER2); 1315 1316 DDR_PHY_SLICE_REGSET_OFS = 1317 DDR_PHY_SLICE_REGSET_OFS_H3VER2; 1318 DDR_PHY_ADR_V_REGSET_OFS = 1319 DDR_PHY_ADR_V_REGSET_OFS_H3VER2; 1320 DDR_PHY_ADR_G_REGSET_OFS = 1321 DDR_PHY_ADR_G_REGSET_OFS_H3VER2; 1322 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2; 1323 DDR_PHY_SLICE_REGSET_SIZE = 1324 DDR_PHY_SLICE_REGSET_SIZE_H3VER2; 1325 DDR_PHY_ADR_V_REGSET_SIZE = 1326 DDR_PHY_ADR_V_REGSET_SIZE_H3VER2; 1327 DDR_PHY_ADR_G_REGSET_SIZE = 1328 DDR_PHY_ADR_G_REGSET_SIZE_H3VER2; 1329 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2; 1330 DDR_PHY_SLICE_REGSET_NUM = 1331 DDR_PHY_SLICE_REGSET_NUM_H3VER2; 1332 DDR_PHY_ADR_V_REGSET_NUM = 1333 DDR_PHY_ADR_V_REGSET_NUM_H3VER2; 1334 DDR_PHY_ADR_G_REGSET_NUM = 1335 DDR_PHY_ADR_G_REGSET_NUM_H3VER2; 1336 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2; 1337 1338 DDR_PHY_ADR_I_NUM = 0; 1339 } 1340 } else if (prr_product == PRR_PRODUCT_M3) { 1341 /* M3-W */ 1342 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1343 DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); 1344 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1345 DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3); 1346 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, 1347 DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3); 1348 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1349 DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3); 1350 _tblcopy(_cnf_DDR_PI_REGSET, 1351 DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3); 1352 1353 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3; 1354 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3; 1355 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3; 1356 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3; 1357 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3; 1358 DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3; 1359 DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3; 1360 DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3; 1361 DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3; 1362 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3; 1363 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3; 1364 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3; 1365 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3; 1366 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3; 1367 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3; 1368 1369 DDR_PHY_ADR_I_NUM = 2; 1370 } else { 1371 /* M3-N/V3H */ 1372 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1373 DDR_PHY_SLICE_REGSET_M3N, 1374 DDR_PHY_SLICE_REGSET_NUM_M3N); 1375 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N, 1376 DDR_PHY_ADR_V_REGSET_NUM_M3N); 1377 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N, 1378 DDR_PHY_ADR_I_REGSET_NUM_M3N); 1379 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N, 1380 DDR_PHY_ADR_G_REGSET_NUM_M3N); 1381 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N, 1382 DDR_PI_REGSET_NUM_M3N); 1383 1384 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N; 1385 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N; 1386 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N; 1387 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N; 1388 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N; 1389 DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N; 1390 DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N; 1391 DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N; 1392 DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N; 1393 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N; 1394 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N; 1395 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N; 1396 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N; 1397 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N; 1398 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N; 1399 1400 DDR_PHY_ADR_I_NUM = 2; 1401 } 1402 1403 /* PLL CODE CHANGE */ 1404 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { 1405 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 1406 0x1142); 1407 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1408 _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); 1409 } 1410 1411 /* on fly gate adjust */ 1412 if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { 1413 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1414 _reg_ON_FLY_GATE_ADJUST_EN, 0x00); 1415 } 1416 1417 /* Adjust PI parameters */ 1418 #ifdef _def_LPDDR4_ODT 1419 for (i = 0; i < 2; i++) { 1420 for (csab = 0; csab < CSAB_CNT; csab++) { 1421 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1422 reg_pi_mr11_data_fx_csx[i][csab], 1423 _def_LPDDR4_ODT); 1424 } 1425 } 1426 #endif /* _def_LPDDR4_ODT */ 1427 1428 #ifdef _def_LPDDR4_VREFCA 1429 for (i = 0; i < 2; i++) { 1430 for (csab = 0; csab < CSAB_CNT; csab++) { 1431 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1432 reg_pi_mr12_data_fx_csx[i][csab], 1433 _def_LPDDR4_VREFCA); 1434 } 1435 } 1436 #endif /* _def_LPDDR4_VREFCA */ 1437 if ((prr_product == PRR_PRODUCT_M3N) || 1438 (prr_product == PRR_PRODUCT_V3H)) { 1439 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; 1440 if (js2[js2_tiedly] > (RL)) 1441 js2[js2_tiedly] = RL; 1442 } else if ((prr_product == PRR_PRODUCT_H3) && 1443 (prr_cut > PRR_PRODUCT_11)) { 1444 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; 1445 } else if ((prr_product == PRR_PRODUCT_H3) && 1446 (prr_cut <= PRR_PRODUCT_11)) { 1447 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); 1448 } 1449 1450 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 1451 (prr_product == PRR_PRODUCT_M3N) || 1452 (prr_product == PRR_PRODUCT_V3H)) { 1453 if ((js2[js2_tiedly]) >= 0x1e) 1454 dataS = 0x1e; 1455 else 1456 dataS = js2[js2_tiedly]; 1457 } else { 1458 if ((js2[js2_tiedly]) >= 0x0e) 1459 dataS = 0x0e; 1460 else 1461 dataS = js2[js2_tiedly]; 1462 } 1463 1464 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); 1465 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, 1466 (dataS - 2)); 1467 if ((prr_product == PRR_PRODUCT_M3N) || 1468 (prr_product == PRR_PRODUCT_V3H)) { 1469 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1470 _reg_PHY_RDDATA_EN_OE_DLY, dataS - 2); 1471 } 1472 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); 1473 1474 if (ddrtbl_getval 1475 (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { 1476 data_l = WL - 1; 1477 } else { 1478 data_l = WL; 1479 } 1480 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2); 1481 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l); 1482 1483 if (board_cnf->dbi_en) { 1484 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 1485 0x01); 1486 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1487 _reg_PHY_WDQLVL_DATADM_MASK, 0x000); 1488 } else { 1489 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 1490 0x00); 1491 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1492 _reg_PHY_WDQLVL_DATADM_MASK, 0x100); 1493 } 1494 1495 tmp[0] = js1[js1_ind].MR1; 1496 tmp[1] = js1[js1_ind].MR2; 1497 data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); 1498 if (board_cnf->dbi_en) 1499 tmp[2] = data_l | 0xc0; 1500 else 1501 tmp[2] = data_l & (~0xc0); 1502 1503 for (i = 0; i < 2; i++) { 1504 for (csab = 0; csab < CSAB_CNT; csab++) { 1505 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1506 reg_pi_mr1_data_fx_csx[i][csab], tmp[0]); 1507 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1508 reg_pi_mr2_data_fx_csx[i][csab], tmp[1]); 1509 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1510 reg_pi_mr3_data_fx_csx[i][csab], tmp[2]); 1511 } 1512 } 1513 1514 /* DDRPHY INT START */ 1515 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1516 /* non */ 1517 } else { 1518 regif_pll_wa(); 1519 dbwait_loop(5); 1520 } 1521 1522 /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ 1523 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1524 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 1525 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); 1526 1527 /* SET DATA SLICE TABLE */ 1528 for (slice = 0; slice < SLICE_CNT; slice++) { 1529 adr = 1530 DDR_PHY_SLICE_REGSET_OFS + 1531 DDR_PHY_SLICE_REGSET_SIZE * slice; 1532 for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) { 1533 reg_ddrphy_write_a(adr + i, 1534 _cnf_DDR_PHY_SLICE_REGSET[i]); 1535 } 1536 } 1537 1538 /* SET ADR SLICE TABLE */ 1539 adr = DDR_PHY_ADR_V_REGSET_OFS; 1540 for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { 1541 reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); 1542 } 1543 1544 if (((prr_product == PRR_PRODUCT_M3) || 1545 (prr_product == PRR_PRODUCT_M3N)) && 1546 ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) 1547 != 0x00)) { 1548 adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; 1549 for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { 1550 reg_ddrphy_write_a(adr + i, 1551 _cnf_DDR_PHY_ADR_V_REGSET[i]); 1552 } 1553 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1554 _reg_PHY_ADR_DISABLE, 0x02); 1555 DDR_PHY_ADR_I_NUM -= 1; 1556 ddr_phycaslice = 1; 1557 1558 #ifndef _def_LPDDR4_ODT 1559 for (i = 0; i < 2; i++) { 1560 for (csab = 0; csab < CSAB_CNT; csab++) { 1561 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1562 reg_pi_mr11_data_fx_csx[i][csab], 1563 0x66); 1564 } 1565 } 1566 #endif/* _def_LPDDR4_ODT */ 1567 } else { 1568 ddr_phycaslice = 0; 1569 } 1570 1571 if (DDR_PHY_ADR_I_NUM > 0) { 1572 for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) { 1573 adr = 1574 DDR_PHY_ADR_I_REGSET_OFS + 1575 DDR_PHY_ADR_I_REGSET_SIZE * slice; 1576 for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) { 1577 reg_ddrphy_write_a(adr + i, 1578 _cnf_DDR_PHY_ADR_I_REGSET 1579 [i]); 1580 } 1581 } 1582 } 1583 1584 /* SET ADRCTRL SLICE TABLE */ 1585 adr = DDR_PHY_ADR_G_REGSET_OFS; 1586 for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { 1587 reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); 1588 } 1589 1590 /* SET PI REGISTERS */ 1591 adr = DDR_PI_REGSET_OFS; 1592 for (i = 0; i < DDR_PI_REGSET_NUM; i++) { 1593 reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); 1594 } 1595 } 1596 1597 /* CONFIGURE DDR REGISTERS */ 1598 static void ddr_config_sub(void) 1599 { 1600 uint32_t i; 1601 uint32_t ch, slice; 1602 uint32_t data_l; 1603 uint32_t tmp; 1604 uint8_t high_byte[SLICE_CNT]; 1605 const uint32_t _par_CALVL_DEVICE_MAP = 1; 1606 1607 foreach_vch(ch) { 1608 /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ 1609 for (slice = 0; slice < SLICE_CNT; slice++) { 1610 high_byte[slice] = 1611 (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; 1612 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, 1613 board_cnf->ch[ch].dq_swap[slice]); 1614 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, 1615 board_cnf->ch[ch].dm_swap[slice]); 1616 if (high_byte[slice]) { 1617 /* HIGHER 16 BYTE */ 1618 ddr_setval_s(ch, slice, 1619 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1620 0x00); 1621 } else { 1622 /* LOWER 16 BYTE */ 1623 ddr_setval_s(ch, slice, 1624 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1625 0x01); 1626 } 1627 } 1628 1629 /* BOARD SETTINGS (CA,ADDR_SEL) */ 1630 data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | 1631 0x00888888; 1632 1633 /* --- ADR_CALVL_SWIZZLE --- */ 1634 if (prr_product == PRR_PRODUCT_M3) { 1635 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); 1636 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 1637 0x00000000); 1638 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); 1639 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 1640 0x00000000); 1641 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 1642 _par_CALVL_DEVICE_MAP); 1643 } else { 1644 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); 1645 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); 1646 ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, 1647 _par_CALVL_DEVICE_MAP); 1648 } 1649 1650 /* --- ADR_ADDR_SEL --- */ 1651 if ((prr_product == PRR_PRODUCT_H3) && 1652 (prr_cut > PRR_PRODUCT_11)) { 1653 data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1654 } else { 1655 data_l = 0; 1656 tmp = board_cnf->ch[ch].ca_swap; 1657 for (i = 0; i < 6; i++) { 1658 data_l |= ((tmp & 0x0f) << (i * 5)); 1659 tmp = tmp >> 4; 1660 } 1661 } 1662 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l); 1663 if (ddr_phycaslice == 1) { 1664 /* ----------- adr slice2 swap ----------- */ 1665 tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40); 1666 data_l = (tmp & 0x00ffffff) | 0x00888888; 1667 1668 /* --- ADR_CALVL_SWIZZLE --- */ 1669 if (prr_product == PRR_PRODUCT_M3) { 1670 ddr_setval_s(ch, 2, 1671 _reg_PHY_ADR_CALVL_SWIZZLE0_0, 1672 data_l); 1673 ddr_setval_s(ch, 2, 1674 _reg_PHY_ADR_CALVL_SWIZZLE1_0, 1675 0x00000000); 1676 ddr_setval_s(ch, 2, 1677 _reg_PHY_ADR_CALVL_SWIZZLE0_1, 1678 data_l); 1679 ddr_setval_s(ch, 2, 1680 _reg_PHY_ADR_CALVL_SWIZZLE1_1, 1681 0x00000000); 1682 ddr_setval_s(ch, 2, 1683 _reg_PHY_ADR_CALVL_DEVICE_MAP, 1684 _par_CALVL_DEVICE_MAP); 1685 } else { 1686 ddr_setval_s(ch, 2, 1687 _reg_PHY_ADR_CALVL_SWIZZLE0, 1688 data_l); 1689 ddr_setval_s(ch, 2, 1690 _reg_PHY_ADR_CALVL_SWIZZLE1, 1691 0x00000000); 1692 ddr_setval_s(ch, 2, 1693 _reg_PHY_CALVL_DEVICE_MAP, 1694 _par_CALVL_DEVICE_MAP); 1695 } 1696 1697 /* --- ADR_ADDR_SEL --- */ 1698 data_l = 0; 1699 for (i = 0; i < 6; i++) { 1700 data_l |= ((tmp & 0x0f) << (i * 5)); 1701 tmp = tmp >> 4; 1702 } 1703 1704 ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); 1705 } 1706 1707 /* BOARD SETTINGS (BYTE_ORDER_SEL) */ 1708 if (prr_product == PRR_PRODUCT_M3) { 1709 /* --- DATA_BYTE_SWAP --- */ 1710 data_l = 0; 1711 tmp = board_cnf->ch[ch].dqs_swap; 1712 for (i = 0; i < 4; i++) { 1713 data_l |= ((tmp & 0x03) << (i * 2)); 1714 tmp = tmp >> 4; 1715 } 1716 } else { 1717 /* --- DATA_BYTE_SWAP --- */ 1718 data_l = board_cnf->ch[ch].dqs_swap; 1719 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); 1720 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, 1721 (data_l) & 0x0f); 1722 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, 1723 (data_l >> 4 * 1) & 0x0f); 1724 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, 1725 (data_l >> 4 * 2) & 0x0f); 1726 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, 1727 (data_l >> 4 * 3) & 0x0f); 1728 1729 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); 1730 } 1731 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l); 1732 } 1733 } 1734 1735 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) 1736 { 1737 uint32_t slice; 1738 uint32_t tmp; 1739 uint32_t tgt; 1740 1741 if (ddr_csn / 2) { 1742 tgt = 3; 1743 } else { 1744 tgt = 1; 1745 } 1746 1747 for (slice = 0; slice < SLICE_CNT; slice++) { 1748 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 1749 if (tgt == tmp) 1750 break; 1751 } 1752 tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1753 if (slice % 2) 1754 tmp |= 0x00888888; 1755 *p_swz = tmp; 1756 } 1757 1758 static void ddr_config_sub_h3v1x(void) 1759 { 1760 uint32_t ch, slice; 1761 uint32_t data_l; 1762 uint32_t tmp; 1763 uint8_t high_byte[SLICE_CNT]; 1764 uint32_t ca_swizzle; 1765 uint32_t ca; 1766 uint32_t csmap; 1767 uint32_t o_inv; 1768 uint32_t inv; 1769 uint32_t bit_soc; 1770 uint32_t bit_mem; 1771 uint32_t j; 1772 1773 const uint8_t o_mr15 = 0x55; 1774 const uint8_t o_mr20 = 0x55; 1775 const uint16_t o_mr32_mr40 = 0x5a3c; 1776 1777 foreach_vch(ch) { 1778 /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ 1779 csmap = 0; 1780 for (slice = 0; slice < SLICE_CNT; slice++) { 1781 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 1782 0x0f; 1783 high_byte[slice] = tmp % 2; 1784 if (tmp == 1 && (slice >= 2)) 1785 csmap |= 0x05; 1786 if (tmp == 3 && (slice >= 2)) 1787 csmap |= 0x50; 1788 ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, 1789 board_cnf->ch[ch].dq_swap[slice]); 1790 if (high_byte[slice]) { 1791 /* HIGHER 16 BYTE */ 1792 ddr_setval_s(ch, slice, 1793 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1794 0x00); 1795 } else { 1796 /* LOWER 16 BYTE */ 1797 ddr_setval_s(ch, slice, 1798 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1799 0x01); 1800 } 1801 } 1802 /* BOARD SETTINGS (CA,ADDR_SEL) */ 1803 ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1804 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); 1805 ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); 1806 1807 get_ca_swizzle(ch, 0, &ca_swizzle); 1808 1809 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle); 1810 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); 1811 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000); 1812 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); 1813 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01); 1814 1815 for (slice = 0; slice < SLICE_CNT; slice++) { 1816 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM, 1817 0x01); 1818 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START, 1819 0x08); 1820 1821 if (high_byte[slice]) 1822 o_inv = o_mr20; 1823 else 1824 o_inv = o_mr15; 1825 1826 tmp = board_cnf->ch[ch].dq_swap[slice]; 1827 inv = 0; 1828 j = 0; 1829 for (bit_soc = 0; bit_soc < 8; bit_soc++) { 1830 bit_mem = (tmp >> (4 * bit_soc)) & 0x0f; 1831 j |= (1U << bit_mem); 1832 if (o_inv & (1U << bit_mem)) 1833 inv |= (1U << bit_soc); 1834 } 1835 data_l = o_mr32_mr40; 1836 if (!high_byte[slice]) 1837 data_l |= (inv << 24); 1838 if (high_byte[slice]) 1839 data_l |= (inv << 16); 1840 ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, 1841 data_l); 1842 } 1843 } 1844 } 1845 1846 static void ddr_config(void) 1847 { 1848 int32_t i; 1849 uint32_t ch, slice; 1850 uint32_t data_l; 1851 uint32_t tmp; 1852 int8_t _adj; 1853 int16_t adj; 1854 uint32_t dq; 1855 union { 1856 uint32_t ui32[4]; 1857 uint8_t ui8[16]; 1858 } patt; 1859 uint16_t patm; 1860 1861 /* configure ddrphy registers */ 1862 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1863 ddr_config_sub_h3v1x(); 1864 } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ 1865 ddr_config_sub(); 1866 } 1867 1868 /* WDQ_USER_PATT */ 1869 foreach_vch(ch) { 1870 for (slice = 0; slice < SLICE_CNT; slice++) { 1871 patm = 0; 1872 for (i = 0; i < 16; i++) { 1873 tmp = board_cnf->ch[ch].wdqlvl_patt[i]; 1874 patt.ui8[i] = tmp & 0xff; 1875 if (tmp & 0x100) 1876 patm |= (1U << i); 1877 } 1878 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, 1879 patt.ui32[0]); 1880 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, 1881 patt.ui32[1]); 1882 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, 1883 patt.ui32[2]); 1884 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, 1885 patt.ui32[3]); 1886 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); 1887 } 1888 } 1889 1890 /* CACS DLY */ 1891 data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); 1892 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1893 0x00U); 1894 foreach_vch(ch) { 1895 for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) { 1896 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 1897 ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, 1898 _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 1899 data_l + adj); 1900 reg_ddrphy_write(ch, 1901 ddr_regdef_adr 1902 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), 1903 _cnf_DDR_PHY_ADR_V_REGSET 1904 [ddr_regdef_adr 1905 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1906 DDR_PHY_ADR_V_REGSET_OFS]); 1907 } 1908 1909 for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); 1910 i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { 1911 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 1912 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1913 _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 1914 data_l + adj); 1915 reg_ddrphy_write(ch, 1916 ddr_regdef_adr 1917 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), 1918 _cnf_DDR_PHY_ADR_G_REGSET 1919 [ddr_regdef_adr 1920 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1921 DDR_PHY_ADR_G_REGSET_OFS]); 1922 } 1923 1924 if (ddr_phycaslice == 1) { 1925 for (i = 0; i < 6; i++) { 1926 adj = _f_scale_adj 1927 (board_cnf->ch[ch].cacs_adj 1928 [i + 1929 _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); 1930 ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, 1931 _reg_PHY_CLK_CACS_SLAVE_DELAY_X 1932 [i], 1933 data_l + adj); 1934 reg_ddrphy_write(ch, 1935 ddr_regdef_adr 1936 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 1937 0x0100, 1938 _cnf_DDR_PHY_ADR_V_REGSET 1939 [ddr_regdef_adr 1940 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1941 DDR_PHY_ADR_V_REGSET_OFS]); 1942 } 1943 } 1944 } 1945 1946 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1947 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 1948 1949 /* WDQDM DLY */ 1950 data_l = board_cnf->dqdm_dly_w; 1951 foreach_vch(ch) { 1952 for (slice = 0; slice < SLICE_CNT; slice++) { 1953 for (i = 0; i <= 8; i++) { 1954 dq = slice * 8 + i; 1955 if (i == 8) 1956 _adj = board_cnf->ch[ch].dm_adj_w[slice]; 1957 else 1958 _adj = board_cnf->ch[ch].dq_adj_w[dq]; 1959 adj = _f_scale_adj(_adj); 1960 ddr_setval_s(ch, slice, 1961 _reg_PHY_CLK_WRX_SLAVE_DELAY[i], 1962 data_l + adj); 1963 } 1964 } 1965 } 1966 1967 /* RDQDM DLY */ 1968 data_l = board_cnf->dqdm_dly_r; 1969 foreach_vch(ch) { 1970 for (slice = 0; slice < SLICE_CNT; slice++) { 1971 for (i = 0; i <= 8; i++) { 1972 dq = slice * 8 + i; 1973 if (i == 8) 1974 _adj = board_cnf->ch[ch].dm_adj_r[slice]; 1975 else 1976 _adj = board_cnf->ch[ch].dq_adj_r[dq]; 1977 adj = _f_scale_adj(_adj); 1978 ddr_setval_s(ch, slice, 1979 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY 1980 [i], data_l + adj); 1981 ddr_setval_s(ch, slice, 1982 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 1983 [i], data_l + adj); 1984 } 1985 } 1986 } 1987 } 1988 1989 /* DBSC register setting functions */ 1990 static void dbsc_regset_pre(void) 1991 { 1992 uint32_t ch, csab; 1993 uint32_t data_l; 1994 1995 /* PRIMARY SETTINGS */ 1996 /* LPDDR4, BL=16, DFI interface */ 1997 mmio_write_32(DBSC_DBKIND, 0x0000000a); 1998 mmio_write_32(DBSC_DBBL, 0x00000002); 1999 mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); 2000 2001 /* FREQRATIO=2 */ 2002 mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); 2003 2004 /* Chanel map (H3 Ver.1.x) */ 2005 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) 2006 mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); 2007 2008 /* DRAM SIZE REGISTER: 2009 * set all ranks as density=0(4Gb) for PHY initialization 2010 */ 2011 foreach_vch(ch) { 2012 for (csab = 0; csab < 4; csab++) { 2013 mmio_write_32(DBSC_DBMEMCONF(ch, csab), 2014 DBMEMCONF_REGD(0)); 2015 } 2016 } 2017 2018 if (prr_product == PRR_PRODUCT_M3) { 2019 data_l = 0xe4e4e4e4; 2020 foreach_ech(ch) { 2021 if ((ddr_phyvalid & (1U << ch))) 2022 data_l = (data_l & (~(0x000000FF << (ch * 8)))) 2023 | (((board_cnf->ch[ch].dqs_swap & 0x0003) 2024 | ((board_cnf->ch[ch].dqs_swap & 0x0030) 2025 >> 2) 2026 | ((board_cnf->ch[ch].dqs_swap & 0x0300) 2027 >> 4) 2028 | ((board_cnf->ch[ch].dqs_swap & 0x3000) 2029 >> 6)) << (ch * 8)); 2030 } 2031 mmio_write_32(DBSC_DBBSWAP, data_l); 2032 } 2033 } 2034 2035 static void dbsc_regset(void) 2036 { 2037 int32_t i; 2038 uint32_t ch; 2039 uint32_t data_l; 2040 uint32_t data_l2; 2041 uint32_t tmp[4]; 2042 2043 /* RFC */ 2044 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && 2045 (max_density == 0)) { 2046 js2[js2_trfcab] = 2047 _f_scale(ddr_mbps, ddr_mbpsdiv, 2048 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); 2049 } else { 2050 js2[js2_trfcab] = 2051 _f_scale(ddr_mbps, ddr_mbpsdiv, 2052 1UL * jedec_spec2_trfc_ab[max_density] * 2053 1000, 0); 2054 } 2055 2056 /* DBTR0.CL : RL */ 2057 mmio_write_32(DBSC_DBTR(0), RL); 2058 2059 /* DBTR1.CWL : WL */ 2060 mmio_write_32(DBSC_DBTR(1), WL); 2061 2062 /* DBTR2.AL : 0 */ 2063 mmio_write_32(DBSC_DBTR(2), 0); 2064 2065 /* DBTR3.TRCD: tRCD */ 2066 mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); 2067 2068 /* DBTR4.TRPA,TRP: tRPab,tRPpb */ 2069 mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); 2070 2071 /* DBTR5.TRC : use tRCpb */ 2072 mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); 2073 2074 /* DBTR6.TRAS : tRAS */ 2075 mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); 2076 2077 /* DBTR7.TRRD : tRRD */ 2078 mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); 2079 2080 /* DBTR8.TFAW : tFAW */ 2081 mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); 2082 2083 /* DBTR9.TRDPR : tRTP */ 2084 mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); 2085 2086 /* DBTR10.TWR : nWR */ 2087 mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr); 2088 2089 /* 2090 * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff - 2091 * odtlon + tDQSCK - tODTon,min + 2092 * PCB delay (out+in) + tPHY_ODToff 2093 */ 2094 mmio_write_32(DBSC_DBTR(11), 2095 RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon + 2096 js2[js2_tdqsck] - js2[js2_tODTon_min] + 2097 _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0)); 2098 2099 /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ 2100 data_l = WL + 1 + (16 / 2) + js2[js2_twtr]; 2101 mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l); 2102 2103 /* DBTR13.TRFCAB : tRFCab */ 2104 mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab])); 2105 2106 /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ 2107 mmio_write_32(DBSC_DBTR(14), 2108 (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd])); 2109 2110 /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ 2111 mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd])); 2112 2113 /* DBTR16 */ 2114 /* WDQL : tphy_wrlat + tphy_wrdata */ 2115 tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); 2116 /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 2117 * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 2118 */ 2119 tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); 2120 /* DQL : tphy_rdlat + trdata_en */ 2121 /* it is not important for dbsc */ 2122 tmp[2] = RL + 16; 2123 /* DQIENLTNCY : trdata_en */ 2124 tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; 2125 mmio_write_32(DBSC_DBTR(16), 2126 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2127 2128 /* DBTR24 */ 2129 /* WRCSLAT = WRLAT -5 */ 2130 tmp[0] -= 5; 2131 /* WRCSGAP = 5 */ 2132 tmp[1] = 5; 2133 /* RDCSLAT = RDLAT_ADJ +2 */ 2134 if (prr_product == PRR_PRODUCT_M3) { 2135 tmp[2] = tmp[3]; 2136 } else { 2137 tmp[2] = tmp[3] + 2; 2138 } 2139 /* RDCSGAP = 6 */ 2140 if (prr_product == PRR_PRODUCT_M3) { 2141 tmp[3] = 4; 2142 } else { 2143 tmp[3] = 6; 2144 } 2145 mmio_write_32(DBSC_DBTR(24), 2146 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2147 2148 /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ 2149 mmio_write_32(DBSC_DBTR(17), 2150 (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16)); 2151 2152 /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ 2153 mmio_write_32(DBSC_DBTR(18), 0); 2154 2155 /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ 2156 mmio_write_32(DBSC_DBTR(19), 0); 2157 2158 /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ 2159 data_l = js2[js2_trfcab] + js2[js2_tckehcmd]; 2160 mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l); 2161 2162 /* DBTR21.TCCD */ 2163 /* DBTR23.TCCD */ 2164 /* H3 Ver.1.0 cannot use TBTR23 feature */ 2165 if (ddr_tccd == 8 && 2166 !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10)) 2167 ) { 2168 data_l = 8; 2169 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2170 mmio_write_32(DBSC_DBTR(23), 0x00000002); 2171 } else if (ddr_tccd <= 11) { 2172 data_l = 11; 2173 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2174 mmio_write_32(DBSC_DBTR(23), 0x00000000); 2175 } else { 2176 data_l = ddr_tccd; 2177 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2178 mmio_write_32(DBSC_DBTR(23), 0x00000000); 2179 } 2180 2181 /* DBTR22.ZQLAT : */ 2182 data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */ 2183 data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20); 2184 mmio_write_32(DBSC_DBTR(22), data_l); 2185 2186 /* DBTR25 : do not use in LPDDR4 */ 2187 mmio_write_32(DBSC_DBTR(25), 0); 2188 2189 /* DBRNK : */ 2190 /* 2191 * DBSC_DBRNK2 rkrr 2192 * DBSC_DBRNK3 rkrw 2193 * DBSC_DBRNK4 rkwr 2194 * DBSC_DBRNK5 rkww 2195 */ 2196 #define _par_DBRNK_VAL (0x7007) 2197 2198 for (i = 0; i < 4; i++) { 2199 data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; 2200 if ((prr_product == PRR_PRODUCT_H3) && 2201 (prr_cut > PRR_PRODUCT_11) && (i == 0)) { 2202 data_l += 1; 2203 } 2204 data_l2 = 0; 2205 foreach_vch(ch) { 2206 data_l2 = data_l2 | (data_l << (4 * ch)); 2207 } 2208 mmio_write_32(DBSC_DBRNK(2 + i), data_l2); 2209 } 2210 mmio_write_32(DBSC_DBADJ0, 0x00000000); 2211 2212 /* timing registers for Scheduler */ 2213 /* SCFCTST0 */ 2214 /* SCFCTST0 ACT-ACT */ 2215 tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; 2216 /* SCFCTST0 RDA-ACT */ 2217 tmp[2] = 2218 1UL * ((16 / 2) + js2[js2_trtp] - 8 + 2219 js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps; 2220 /* SCFCTST0 WRA-ACT */ 2221 tmp[1] = 2222 1UL * (WL + 1 + (16 / 2) + 2223 js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps; 2224 /* SCFCTST0 PRE-ACT */ 2225 tmp[0] = 1UL * js2[js2_trppb]; 2226 mmio_write_32(DBSC_SCFCTST0, 2227 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2228 2229 /* SCFCTST1 */ 2230 /* SCFCTST1 RD-WR */ 2231 tmp[3] = 2232 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / 2233 ddr_mbps; 2234 /* SCFCTST1 WR-RD */ 2235 tmp[2] = 2236 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / 2237 ddr_mbps; 2238 /* SCFCTST1 ACT-RD/WR */ 2239 tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps; 2240 /* SCFCTST1 ASYNCOFS */ 2241 tmp[0] = 12; 2242 mmio_write_32(DBSC_SCFCTST1, 2243 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2244 2245 /* DBSCHRW1 */ 2246 /* DBSCHRW1 SCTRFCAB */ 2247 tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps; 2248 data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) 2249 + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2250 + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; 2251 if (tmp[0] < data_l) 2252 tmp[0] = data_l; 2253 2254 if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { 2255 mmio_write_32(DBSC_DBSCHRW1, tmp[0] 2256 + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2257 * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / 2258 ddr_mbps - 3); 2259 } else { 2260 mmio_write_32(DBSC_DBSCHRW1, tmp[0] 2261 + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2262 * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / 2263 ddr_mbps); 2264 } 2265 2266 /* QOS and CAM */ 2267 #ifdef ddr_qos_init_setting /* only for non qos_init */ 2268 /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ 2269 mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); 2270 /*0(fillunit),8(dirtymax),4(dirtymin) */ 2271 mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); 2272 /*stop_tolerance */ 2273 mmio_write_32(DBSC_DBSCHRW0, 0x22421111); 2274 /*rd-wr/wr-rd toggle priority */ 2275 mmio_write_32(DBSC_SCFCTST2, 0x012F1123); 2276 mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); 2277 mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); 2278 2279 /* QoS Settings */ 2280 mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); 2281 mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); 2282 mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); 2283 mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); 2284 mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); 2285 mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); 2286 mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); 2287 mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); 2288 mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); 2289 mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); 2290 mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); 2291 mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); 2292 mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); 2293 mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); 2294 mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); 2295 mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); 2296 mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); 2297 mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); 2298 mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); 2299 mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); 2300 mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); 2301 mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); 2302 mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); 2303 mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); 2304 mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); 2305 mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); 2306 mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); 2307 mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); 2308 2309 mmio_write_32(QOSCTRL_RAEN, 0x00000001U); 2310 #endif /* ddr_qos_init_setting */ 2311 /* H3 Ver.1.1 need to set monitor function */ 2312 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { 2313 mmio_write_32(DBSC_DBMONCONF4, 0x00700000); 2314 } 2315 2316 if (prr_product == PRR_PRODUCT_H3) { 2317 if (prr_cut == PRR_PRODUCT_10) { 2318 /* resrdis, simple mode, sc off */ 2319 mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); 2320 } else if (prr_cut == PRR_PRODUCT_11) { 2321 /* resrdis, simple mode */ 2322 mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); 2323 } else if (prr_cut < PRR_PRODUCT_30) { 2324 /* H3 Ver.2.0 */ 2325 /* resrdis */ 2326 mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); 2327 } else { /* H3 Ver.3.0(include H3N) */ 2328 /* exprespque */ 2329 mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); 2330 } 2331 } else { /* M3-W/M3-N/V3H */ 2332 /* resrdis */ 2333 mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); 2334 } 2335 } 2336 2337 static void dbsc_regset_post(void) 2338 { 2339 uint32_t ch, cs; 2340 uint32_t data_l; 2341 uint32_t slice, rdlat_max, rdlat_min; 2342 2343 rdlat_max = 0; 2344 rdlat_min = 0xffff; 2345 foreach_vch(ch) { 2346 for (cs = 0; cs < CS_CNT; cs++) { 2347 if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { 2348 for (slice = 0; slice < SLICE_CNT; slice++) { 2349 ddr_setval_s(ch, slice, 2350 _reg_PHY_PER_CS_TRAINING_INDEX, 2351 cs); 2352 data_l = ddr_getval_s(ch, slice, 2353 _reg_PHY_RDDQS_LATENCY_ADJUST); 2354 if (data_l > rdlat_max) 2355 rdlat_max = data_l; 2356 if (data_l < rdlat_min) 2357 rdlat_min = data_l; 2358 } 2359 } 2360 } 2361 } 2362 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) { 2363 #if RCAR_DRAM_SPLIT == 2 2364 if (board_cnf->phyvalid == 0x05) { 2365 mmio_write_32(DBSC_DBTR(24), 2366 (rdlat_max << 24) + (rdlat_min << 16) + 2367 mmio_read_32(DBSC_DBTR(24))); 2368 } else { 2369 mmio_write_32(DBSC_DBTR(24), 2370 ((rdlat_max * 2 - rdlat_min + 4) << 24) + 2371 ((rdlat_min + 2) << 16) + 2372 mmio_read_32(DBSC_DBTR(24))); 2373 } 2374 #else /*RCAR_DRAM_SPLIT == 2 */ 2375 mmio_write_32(DBSC_DBTR(24), 2376 ((rdlat_max * 2 - rdlat_min + 4) << 24) + 2377 ((rdlat_min + 2) << 16) + 2378 mmio_read_32(DBSC_DBTR(24))); 2379 #endif /*RCAR_DRAM_SPLIT == 2 */ 2380 } else { 2381 mmio_write_32(DBSC_DBTR(24), 2382 ((rdlat_max + 2) << 24) + 2383 ((rdlat_max + 2) << 16) + 2384 mmio_read_32(DBSC_DBTR(24))); 2385 } 2386 2387 /* set ddr density information */ 2388 foreach_ech(ch) { 2389 for (cs = 0; cs < CS_CNT; cs++) { 2390 if (ddr_density[ch][cs] == 0xff) { 2391 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); 2392 } else { 2393 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 2394 DBMEMCONF_REGD(ddr_density[ch] 2395 [cs])); 2396 } 2397 } 2398 mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); 2399 mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); 2400 } 2401 2402 mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); 2403 2404 /*set DBI */ 2405 if (board_cnf->dbi_en) 2406 mmio_write_32(DBSC_DBDBICNT, 0x00000003); 2407 2408 /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ 2409 if ((((prr_product == PRR_PRODUCT_H3) && 2410 (prr_cut > PRR_PRODUCT_11)) || 2411 (prr_product == PRR_PRODUCT_M3N) || 2412 (prr_product == PRR_PRODUCT_V3H)) && 2413 board_cnf->dbi_en) 2414 reg_ddrphy_write_a(0x00001010, 0x01000000); 2415 2416 /*set REFCYCLE */ 2417 data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; 2418 mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff)); 2419 mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); 2420 2421 #if RCAR_REWT_TRAINING != 0 2422 /* Periodic-WriteDQ Training seeting */ 2423 if (((prr_product == PRR_PRODUCT_H3) && 2424 (prr_cut <= PRR_PRODUCT_11)) || 2425 ((prr_product == PRR_PRODUCT_M3) && 2426 (prr_cut == PRR_PRODUCT_10))) { 2427 /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ 2428 } else { 2429 /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ 2430 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); 2431 2432 ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); 2433 ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); 2434 ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); 2435 ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); 2436 2437 ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, 2438 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2439 _reg_PI_WDQLVL_CS_MAP)); 2440 ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); 2441 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); 2442 ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); 2443 ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); 2444 ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); 2445 ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); 2446 2447 if (prr_product == PRR_PRODUCT_M3) { 2448 ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); 2449 } else { 2450 ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); 2451 } 2452 ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); 2453 2454 /* DFI_PHYMSTR_ACK , WTmode setting */ 2455 /* DFI_PHYMSTR_ACK: WTmode =b'01 */ 2456 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); 2457 } 2458 #endif /* RCAR_REWT_TRAINING */ 2459 /* periodic dram zqcal enable */ 2460 mmio_write_32(DBSC_DBCALCNF, 0x01000010); 2461 2462 /* periodic phy ctrl update enable */ 2463 if (((prr_product == PRR_PRODUCT_H3) && 2464 (prr_cut <= PRR_PRODUCT_11)) || 2465 ((prr_product == PRR_PRODUCT_M3) && 2466 (prr_cut < PRR_PRODUCT_30))) { 2467 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 2468 } else { 2469 #if RCAR_DRAM_SPLIT == 2 2470 if ((prr_product == PRR_PRODUCT_H3) && 2471 (board_cnf->phyvalid == 0x05)) 2472 mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); 2473 else 2474 mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); 2475 #else /* RCAR_DRAM_SPLIT == 2 */ 2476 mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); 2477 #endif /* RCAR_DRAM_SPLIT == 2 */ 2478 } 2479 2480 #ifdef DDR_BACKUPMODE 2481 /* SRX */ 2482 if (ddr_backup == DRAM_BOOT_STATUS_WARM) { 2483 #ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */ 2484 NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n"); 2485 send_dbcmd(0x0A040001); 2486 if (Prr_Product == PRR_PRODUCT_H3) 2487 send_dbcmd(0x0A140001); 2488 #else /* DDR_BACKUPMODE_HALF */ /* for All channels */ 2489 send_dbcmd(0x0A840001); 2490 #endif /* DDR_BACKUPMODE_HALF */ 2491 } 2492 #endif /* DDR_BACKUPMODE */ 2493 2494 /* set Auto Refresh */ 2495 mmio_write_32(DBSC_DBRFEN, 0x00000001); 2496 2497 #if RCAR_REWT_TRAINING != 0 2498 /* Periodic WriteDQ Traning */ 2499 if (((prr_product == PRR_PRODUCT_H3) && 2500 (prr_cut <= PRR_PRODUCT_11)) || 2501 ((prr_product == PRR_PRODUCT_M3) && 2502 (prr_cut == PRR_PRODUCT_10))) { 2503 /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ 2504 } else { 2505 /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ 2506 ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); 2507 } 2508 #endif /* RCAR_REWT_TRAINING */ 2509 2510 /* dram access enable */ 2511 mmio_write_32(DBSC_DBACEN, 0x00000001); 2512 2513 MSG_LF(__func__ "(done)"); 2514 } 2515 2516 /* DFI_INIT_START */ 2517 static uint32_t dfi_init_start(void) 2518 { 2519 uint32_t ch; 2520 uint32_t phytrainingok; 2521 uint32_t retry; 2522 uint32_t data_l; 2523 const uint32_t RETRY_MAX = 0x10000; 2524 2525 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2526 /* PLL3 Disable */ 2527 /* protect register interface */ 2528 ddrphy_regif_idle(); 2529 2530 pll3_control(0); 2531 2532 /* init start */ 2533 /* dbdficnt0: 2534 * dfi_dram_clk_disable=1 2535 * dfi_frequency = 0 2536 * freq_ratio = 01 (2:1) 2537 * init_start =0 2538 */ 2539 foreach_vch(ch) 2540 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); 2541 dsb_sev(); 2542 2543 /* dbdficnt0: 2544 * dfi_dram_clk_disable=1 2545 * dfi_frequency = 0 2546 * freq_ratio = 01 (2:1) 2547 * init_start =1 2548 */ 2549 foreach_vch(ch) 2550 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); 2551 dsb_sev(); 2552 2553 } else { 2554 ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); 2555 dsb_sev(); 2556 ddrphy_regif_idle(); 2557 } 2558 2559 /* dll_rst negate */ 2560 foreach_vch(ch) 2561 mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); 2562 dsb_sev(); 2563 2564 /* wait init_complete */ 2565 phytrainingok = 0; 2566 retry = 0; 2567 while (retry++ < RETRY_MAX) { 2568 foreach_vch(ch) { 2569 data_l = mmio_read_32(DBSC_DBDFISTAT(ch)); 2570 if (data_l & 0x00000001) 2571 phytrainingok |= (1U << ch); 2572 } 2573 dsb_sev(); 2574 if (phytrainingok == ddr_phyvalid) 2575 break; 2576 if (retry % 256 == 0) 2577 ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); 2578 } 2579 2580 /* all ch ok? */ 2581 if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) 2582 return 0xff; 2583 2584 /* dbdficnt0: 2585 * dfi_dram_clk_disable=0 2586 * dfi_frequency = 0 2587 * freq_ratio = 01 (2:1) 2588 * init_start =0 2589 */ 2590 foreach_vch(ch) 2591 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); 2592 dsb_sev(); 2593 2594 return 0; 2595 } 2596 2597 /* drivablity setting : CMOS MODE ON/OFF */ 2598 static void change_lpddr4_en(uint32_t mode) 2599 { 2600 uint32_t ch; 2601 uint32_t i; 2602 uint32_t data_l; 2603 const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { 2604 _reg_PHY_PAD_ADDR_DRIVE, 2605 _reg_PHY_PAD_CLK_DRIVE, 2606 _reg_PHY_PAD_CS_DRIVE 2607 }; 2608 2609 foreach_vch(ch) { 2610 for (i = 0; i < 3; i++) { 2611 data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); 2612 if (mode) { 2613 data_l |= (1U << 14); 2614 } else { 2615 data_l &= ~(1U << 14); 2616 } 2617 ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l); 2618 } 2619 } 2620 } 2621 2622 /* drivablity setting */ 2623 static uint32_t set_term_code(void) 2624 { 2625 int32_t i; 2626 uint32_t ch, index; 2627 uint32_t data_l; 2628 uint32_t chip_id[2]; 2629 uint32_t term_code; 2630 uint32_t override; 2631 uint32_t pvtr; 2632 uint32_t pvtp; 2633 uint32_t pvtn; 2634 2635 term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 2636 _reg_PHY_PAD_DATA_TERM); 2637 override = 0; 2638 for (i = 0; i < 2; i++) 2639 chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); 2640 2641 index = 0; 2642 while (1) { 2643 if (termcode_by_sample[index][0] == 0xffffffff) { 2644 break; 2645 } 2646 if ((termcode_by_sample[index][0] == chip_id[0]) && 2647 (termcode_by_sample[index][1] == chip_id[1])) { 2648 term_code = termcode_by_sample[index][2]; 2649 override = 1; 2650 break; 2651 } 2652 index++; 2653 } 2654 2655 if (override) { 2656 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { 2657 data_l = 2658 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 2659 _reg_PHY_PAD_TERM_X[index]); 2660 data_l = (data_l & 0xfffe0000) | term_code; 2661 ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); 2662 } 2663 } else if ((prr_product == PRR_PRODUCT_M3) && 2664 (prr_cut == PRR_PRODUCT_10)) { 2665 /* non */ 2666 } else { 2667 ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], 2668 (ddrtbl_getval 2669 (_cnf_DDR_PHY_ADR_G_REGSET, 2670 _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); 2671 ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); 2672 ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); 2673 foreach_vch(ch) { 2674 do { 2675 data_l = 2676 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); 2677 } while (!(data_l & 0x00800000)); 2678 } 2679 if ((prr_product == PRR_PRODUCT_H3) && 2680 (prr_cut <= PRR_PRODUCT_11)) { 2681 foreach_vch(ch) { 2682 data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); 2683 pvtr = (data_l >> 12) & 0x1f; 2684 pvtr += 8; 2685 if (pvtr > 0x1f) 2686 pvtr = 0x1f; 2687 data_l = 2688 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); 2689 pvtn = (data_l >> 6) & 0x03f; 2690 pvtp = (data_l >> 0) & 0x03f; 2691 2692 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; 2693 index++) { 2694 data_l = 2695 ddrtbl_getval 2696 (_cnf_DDR_PHY_ADR_G_REGSET, 2697 _reg_PHY_PAD_TERM_X[index]); 2698 data_l = (data_l & 0xfffe0000) 2699 | (pvtr << 12) 2700 | (pvtn << 6) 2701 | (pvtp); 2702 ddr_setval(ch, 2703 _reg_PHY_PAD_TERM_X[index], 2704 data_l); 2705 } 2706 } 2707 } else { 2708 /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ 2709 foreach_vch(ch) { 2710 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; 2711 index++) { 2712 data_l = 2713 ddr_getval(ch, 2714 _reg_PHY_PAD_TERM_X 2715 [index]); 2716 ddr_setval(ch, 2717 _reg_PHY_PAD_TERM_X[index], 2718 (data_l & 0xFFFE0FFF) | 2719 0x00015000); 2720 } 2721 } 2722 } 2723 } 2724 2725 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2726 /* non */ 2727 } else { 2728 ddr_padcal_tcompensate_getinit(override); 2729 } 2730 2731 return 0; 2732 } 2733 2734 /* DDR mode register setting */ 2735 static void ddr_register_set(void) 2736 { 2737 int32_t fspwp; 2738 uint32_t tmp; 2739 2740 for (fspwp = 1; fspwp >= 0; fspwp--) { 2741 /*MR13, fspwp */ 2742 send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); 2743 2744 tmp = 2745 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2746 reg_pi_mr1_data_fx_csx[fspwp][0]); 2747 send_dbcmd(0x0e840100 | tmp); 2748 2749 tmp = 2750 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2751 reg_pi_mr2_data_fx_csx[fspwp][0]); 2752 send_dbcmd(0x0e840200 | tmp); 2753 2754 tmp = 2755 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2756 reg_pi_mr3_data_fx_csx[fspwp][0]); 2757 send_dbcmd(0x0e840300 | tmp); 2758 2759 tmp = 2760 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2761 reg_pi_mr11_data_fx_csx[fspwp][0]); 2762 send_dbcmd(0x0e840b00 | tmp); 2763 2764 tmp = 2765 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2766 reg_pi_mr12_data_fx_csx[fspwp][0]); 2767 send_dbcmd(0x0e840c00 | tmp); 2768 2769 tmp = 2770 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2771 reg_pi_mr14_data_fx_csx[fspwp][0]); 2772 send_dbcmd(0x0e840e00 | tmp); 2773 /* MR22 */ 2774 send_dbcmd(0x0e841616); 2775 2776 /* ZQCAL start */ 2777 send_dbcmd(0x0d84004F); 2778 2779 /* ZQLAT */ 2780 send_dbcmd(0x0d840051); 2781 } 2782 2783 /* MR13, fspwp */ 2784 send_dbcmd(0x0e840d08); 2785 } 2786 2787 /* Training handshake functions */ 2788 static inline uint32_t wait_freqchgreq(uint32_t assert) 2789 { 2790 uint32_t data_l; 2791 uint32_t count; 2792 uint32_t ch; 2793 2794 count = 100000; 2795 2796 /* H3 Ver.1.x cannot see frqchg_req */ 2797 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2798 return 0; 2799 } 2800 2801 if (assert) { 2802 do { 2803 data_l = 1; 2804 foreach_vch(ch) { 2805 data_l &= mmio_read_32(DBSC_DBPDSTAT(ch)); 2806 } 2807 count = count - 1; 2808 } while (((data_l & 0x01) != 0x01) & (count != 0)); 2809 } else { 2810 do { 2811 data_l = 0; 2812 foreach_vch(ch) { 2813 data_l |= mmio_read_32(DBSC_DBPDSTAT(ch)); 2814 } 2815 count = count - 1; 2816 } while (((data_l & 0x01) != 0x00) & (count != 0)); 2817 } 2818 2819 return (count == 0); 2820 } 2821 2822 static inline void set_freqchgack(uint32_t assert) 2823 { 2824 uint32_t ch; 2825 uint32_t data_l; 2826 2827 if (assert) 2828 data_l = 0x0CF20000; 2829 else 2830 data_l = 0x00000000; 2831 2832 foreach_vch(ch) 2833 mmio_write_32(DBSC_DBPDCNT2(ch), data_l); 2834 } 2835 2836 static inline void set_dfifrequency(uint32_t freq) 2837 { 2838 uint32_t ch; 2839 2840 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2841 foreach_vch(ch) 2842 mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); 2843 } else { 2844 foreach_vch(ch) { 2845 mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, 2846 (freq << 24)); 2847 } 2848 } 2849 dsb_sev(); 2850 } 2851 2852 static uint32_t pll3_freq(uint32_t on) 2853 { 2854 uint32_t timeout; 2855 2856 timeout = wait_freqchgreq(1); 2857 2858 if (timeout) { 2859 return 1; 2860 } 2861 2862 pll3_control(on); 2863 set_dfifrequency(on); 2864 2865 set_freqchgack(1); 2866 timeout = wait_freqchgreq(0); 2867 set_freqchgack(0); 2868 2869 if (timeout) { 2870 FATAL_MSG("BL2: Time out[2]\n"); 2871 return 1; 2872 } 2873 return 0; 2874 } 2875 2876 /* update dly */ 2877 static void update_dly(void) 2878 { 2879 ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); 2880 ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); 2881 } 2882 2883 /* training by pi */ 2884 static uint32_t pi_training_go(void) 2885 { 2886 uint32_t flag; 2887 uint32_t data_l; 2888 uint32_t retry; 2889 const uint32_t RETRY_MAX = 4096 * 16; 2890 uint32_t ch; 2891 2892 uint32_t mst_ch; 2893 uint32_t cur_frq; 2894 uint32_t complete; 2895 uint32_t frqchg_req; 2896 2897 /* pi_start */ 2898 ddr_setval_ach(_reg_PI_START, 0x01); 2899 foreach_vch(ch) 2900 ddr_getval(ch, _reg_PI_INT_STATUS); 2901 2902 /* set dfi_phymstr_ack = 1 */ 2903 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); 2904 dsb_sev(); 2905 2906 /* wait pi_int_status[0] */ 2907 mst_ch = 0; 2908 flag = 0; 2909 complete = 0; 2910 cur_frq = 0; 2911 retry = RETRY_MAX; 2912 do { 2913 frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; 2914 2915 /* H3 Ver.1.x cannot see frqchg_req */ 2916 if ((prr_product == PRR_PRODUCT_H3) && 2917 (prr_cut <= PRR_PRODUCT_11)) { 2918 if ((retry % 4096) == 1) { 2919 frqchg_req = 1; 2920 } else { 2921 frqchg_req = 0; 2922 } 2923 } 2924 2925 if (frqchg_req) { 2926 if (cur_frq) { 2927 /* Low frequency */ 2928 flag = pll3_freq(0); 2929 cur_frq = 0; 2930 } else { 2931 /* High frequency */ 2932 flag = pll3_freq(1); 2933 cur_frq = 1; 2934 } 2935 if (flag) 2936 break; 2937 } else { 2938 if (cur_frq) { 2939 foreach_vch(ch) { 2940 if (complete & (1U << ch)) 2941 continue; 2942 data_l = 2943 ddr_getval(ch, _reg_PI_INT_STATUS); 2944 if (data_l & 0x01) { 2945 complete |= (1U << ch); 2946 } 2947 } 2948 if (complete == ddr_phyvalid) 2949 break; 2950 } 2951 } 2952 } while (--retry); 2953 foreach_vch(ch) { 2954 /* dummy read */ 2955 data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); 2956 data_l = ddr_getval(ch, _reg_PI_INT_STATUS); 2957 ddr_setval(ch, _reg_PI_INT_ACK, data_l); 2958 } 2959 if (ddrphy_regif_chk()) { 2960 return 0xfd; 2961 } 2962 return complete; 2963 } 2964 2965 /* Initialize DDR */ 2966 static uint32_t init_ddr(void) 2967 { 2968 int32_t i; 2969 uint32_t data_l; 2970 uint32_t phytrainingok; 2971 uint32_t ch, slice; 2972 uint32_t err; 2973 int16_t adj; 2974 2975 MSG_LF(__func__ ":0\n"); 2976 2977 #ifdef DDR_BACKUPMODE 2978 rcar_dram_get_boot_status(&ddr_backup); 2979 #endif 2980 2981 /* unlock phy */ 2982 /* Unlock DDRPHY register(AGAIN) */ 2983 foreach_vch(ch) 2984 mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); 2985 dsb_sev(); 2986 2987 if ((((prr_product == PRR_PRODUCT_H3) && 2988 (prr_cut > PRR_PRODUCT_11)) || 2989 (prr_product == PRR_PRODUCT_M3N) || 2990 (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en) 2991 reg_ddrphy_write_a(0x00001010, 0x01000001); 2992 else 2993 reg_ddrphy_write_a(0x00001010, 0x00000001); 2994 /* DBSC register pre-setting */ 2995 dbsc_regset_pre(); 2996 2997 /* load ddrphy registers */ 2998 2999 ddrtbl_load(); 3000 3001 /* configure ddrphy registers */ 3002 ddr_config(); 3003 3004 /* dfi_reset assert */ 3005 foreach_vch(ch) 3006 mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); 3007 dsb_sev(); 3008 3009 /* dbsc register set */ 3010 dbsc_regset(); 3011 MSG_LF(__func__ ":1\n"); 3012 3013 /* dfi_reset negate */ 3014 foreach_vch(ch) 3015 mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); 3016 dsb_sev(); 3017 3018 /* dfi_init_start (start ddrphy) */ 3019 err = dfi_init_start(); 3020 if (err) { 3021 return INITDRAM_ERR_I; 3022 } 3023 MSG_LF(__func__ ":2\n"); 3024 3025 /* ddr backupmode end */ 3026 #ifdef DDR_BACKUPMODE 3027 if (ddr_backup) { 3028 NOTICE("BL2: [WARM_BOOT]\n"); 3029 } else { 3030 NOTICE("BL2: [COLD_BOOT]\n"); 3031 } 3032 err = rcar_dram_update_boot_status(ddr_backup); 3033 if (err) { 3034 NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); 3035 return INITDRAM_ERR_I; 3036 } 3037 #endif 3038 MSG_LF(__func__ ":3\n"); 3039 3040 /* override term code after dfi_init_complete */ 3041 err = set_term_code(); 3042 if (err) { 3043 return INITDRAM_ERR_I; 3044 } 3045 MSG_LF(__func__ ":4\n"); 3046 3047 /* rx offset calibration */ 3048 if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || 3049 (prr_product == PRR_PRODUCT_V3H)) { 3050 err = rx_offset_cal_hw(); 3051 } else { 3052 err = rx_offset_cal(); 3053 } 3054 if (err) 3055 return INITDRAM_ERR_O; 3056 MSG_LF(__func__ ":5\n"); 3057 3058 /* Dummy PDE */ 3059 send_dbcmd(0x08840000); 3060 3061 /* PDX */ 3062 send_dbcmd(0x08840001); 3063 3064 /* check register i/f is alive */ 3065 err = ddrphy_regif_chk(); 3066 if (err) { 3067 return INITDRAM_ERR_O; 3068 } 3069 MSG_LF(__func__ ":6\n"); 3070 3071 /* phy initialize end */ 3072 3073 /* setup DDR mode registers */ 3074 /* CMOS MODE */ 3075 change_lpddr4_en(0); 3076 3077 /* MRS */ 3078 ddr_register_set(); 3079 3080 /* Thermal sensor setting */ 3081 /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ 3082 data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; 3083 mmio_write_32(THS1_THCTR, data_l); 3084 3085 /* LPDDR4 MODE */ 3086 change_lpddr4_en(1); 3087 3088 MSG_LF(__func__ ":7\n"); 3089 3090 /* mask CS_MAP if RANKx is not found */ 3091 foreach_vch(ch) { 3092 data_l = ddr_getval(ch, _reg_PI_CS_MAP); 3093 if (!(ch_have_this_cs[1] & (1U << ch))) 3094 data_l = data_l & 0x05; 3095 ddr_setval(ch, _reg_PI_CS_MAP, data_l); 3096 } 3097 3098 /* exec pi_training */ 3099 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 3100 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 3101 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); 3102 3103 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3104 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); 3105 } else { 3106 foreach_vch(ch) { 3107 for (slice = 0; slice < SLICE_CNT; slice++) { 3108 ddr_setval_s(ch, slice, 3109 _reg_PHY_PER_CS_TRAINING_EN, 3110 ((ch_have_this_cs[1]) >> ch) 3111 & 0x01); 3112 } 3113 } 3114 } 3115 3116 phytrainingok = pi_training_go(); 3117 3118 if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { 3119 return INITDRAM_ERR_T | phytrainingok; 3120 } 3121 3122 MSG_LF(__func__ ":8\n"); 3123 3124 /* CACS DLY ADJUST */ 3125 data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); 3126 foreach_vch(ch) { 3127 for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { 3128 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 3129 ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 3130 data_l + adj); 3131 } 3132 3133 if (ddr_phycaslice == 1) { 3134 for (i = 0; i < 6; i++) { 3135 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj 3136 [i + 3137 _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); 3138 ddr_setval_s(ch, 2, 3139 _reg_PHY_CLK_CACS_SLAVE_DELAY_X 3140 [i], 3141 data_l + adj 3142 ); 3143 } 3144 } 3145 } 3146 3147 update_dly(); 3148 MSG_LF(__func__ ":9\n"); 3149 3150 /* H3 fix rd latency to avoid bug in elasitic buffer */ 3151 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) 3152 adjust_rddqs_latency(); 3153 3154 /* Adjust Write path latency */ 3155 if (ddrtbl_getval 3156 (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) 3157 adjust_wpath_latency(); 3158 3159 /* RDQLVL Training */ 3160 if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) 3161 ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); 3162 3163 err = rdqdm_man(); 3164 3165 if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) 3166 ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); 3167 3168 if (err) { 3169 return INITDRAM_ERR_T; 3170 } 3171 update_dly(); 3172 MSG_LF(__func__ ":10\n"); 3173 3174 /* WDQLVL Training */ 3175 err = wdqdm_man(); 3176 if (err) { 3177 return INITDRAM_ERR_T; 3178 } 3179 update_dly(); 3180 MSG_LF(__func__ ":11\n"); 3181 3182 /* training complete, setup DBSC */ 3183 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 3184 (prr_product == PRR_PRODUCT_M3N) || 3185 (prr_product == PRR_PRODUCT_V3H)) { 3186 ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); 3187 ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); 3188 } 3189 3190 dbsc_regset_post(); 3191 MSG_LF(__func__ ":12\n"); 3192 3193 return phytrainingok; 3194 } 3195 3196 /* SW LEVELING COMMON */ 3197 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) 3198 { 3199 uint32_t ch; 3200 uint32_t data_l; 3201 uint32_t retry; 3202 uint32_t waiting; 3203 uint32_t err; 3204 3205 const uint32_t RETRY_MAX = 0x1000; 3206 3207 err = 0; 3208 /* set EXIT -> OP_DONE is cleared */ 3209 ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); 3210 3211 /* kick */ 3212 foreach_vch(ch) { 3213 if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) { 3214 ddr_setval(ch, reg_cs, ddr_csn); 3215 ddr_setval(ch, reg_kick, 0x01); 3216 } 3217 } 3218 foreach_vch(ch) { 3219 /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */ 3220 ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); 3221 } 3222 waiting = ch_have_this_cs[ddr_csn % 2]; 3223 dsb_sev(); 3224 retry = RETRY_MAX; 3225 do { 3226 foreach_vch(ch) { 3227 if (!(waiting & (1U << ch))) 3228 continue; 3229 data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); 3230 if (data_l & 0x01) 3231 waiting &= ~(1U << ch); 3232 } 3233 retry--; 3234 } while (waiting && (retry > 0)); 3235 if (retry == 0) { 3236 err = 1; 3237 } 3238 3239 dsb_sev(); 3240 /* set EXIT -> OP_DONE is cleared */ 3241 ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); 3242 dsb_sev(); 3243 3244 return err; 3245 } 3246 3247 /* WDQ TRAINING */ 3248 #ifndef DDR_FAST_INIT 3249 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) 3250 { 3251 int32_t i, k; 3252 uint32_t cs, slice; 3253 uint32_t data_l; 3254 3255 /* clr of training results buffer */ 3256 cs = ddr_csn % 2; 3257 data_l = board_cnf->dqdm_dly_w; 3258 for (slice = 0; slice < SLICE_CNT; slice++) { 3259 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3260 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3261 continue; 3262 3263 for (i = 0; i <= 8; i++) { 3264 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) 3265 wdqdm_dly[ch][cs][slice][i] = 3266 wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; 3267 else 3268 wdqdm_dly[ch][cs][slice][i] = data_l; 3269 wdqdm_le[ch][cs][slice][i] = 0; 3270 wdqdm_te[ch][cs][slice][i] = 0; 3271 } 3272 wdqdm_st[ch][cs][slice] = 0; 3273 wdqdm_win[ch][cs][slice] = 0; 3274 } 3275 } 3276 3277 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) 3278 { 3279 int32_t i, k; 3280 uint32_t cs, slice; 3281 uint32_t data_l; 3282 uint32_t err; 3283 const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; 3284 3285 int32_t min_win; 3286 int32_t win; 3287 int8_t _adj; 3288 int16_t adj; 3289 uint32_t dq; 3290 3291 /* analysis of training results */ 3292 err = 0; 3293 for (slice = 0; slice < SLICE_CNT; slice += 1) { 3294 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3295 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3296 continue; 3297 3298 cs = ddr_csn % 2; 3299 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); 3300 for (i = 0; i < 9; i++) { 3301 dq = slice * 8 + i; 3302 if (i == 8) 3303 _adj = board_cnf->ch[ch].dm_adj_w[slice]; 3304 else 3305 _adj = board_cnf->ch[ch].dq_adj_w[dq]; 3306 adj = _f_scale_adj(_adj); 3307 3308 data_l = 3309 ddr_getval_s(ch, slice, 3310 _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; 3311 ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], 3312 data_l); 3313 wdqdm_dly[ch][cs][slice][i] = data_l; 3314 } 3315 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); 3316 data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); 3317 wdqdm_st[ch][cs][slice] = data_l; 3318 min_win = INT_LEAST32_MAX; 3319 for (i = 0; i <= 8; i++) { 3320 ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, 3321 i); 3322 3323 data_l = 3324 ddr_getval_s(ch, slice, 3325 _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); 3326 wdqdm_te[ch][cs][slice][i] = data_l; 3327 data_l = 3328 ddr_getval_s(ch, slice, 3329 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); 3330 wdqdm_le[ch][cs][slice][i] = data_l; 3331 win = 3332 (int32_t)wdqdm_te[ch][cs][slice][i] - 3333 wdqdm_le[ch][cs][slice][i]; 3334 if (min_win > win) 3335 min_win = win; 3336 if (data_l >= _par_WDQLVL_RETRY_THRES) 3337 err = 2; 3338 } 3339 wdqdm_win[ch][cs][slice] = min_win; 3340 if ((prr_product == PRR_PRODUCT_H3) && 3341 (prr_cut <= PRR_PRODUCT_11)) { 3342 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 3343 0x01); 3344 } else { 3345 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 3346 ((ch_have_this_cs[1]) >> ch) & 0x01); 3347 } 3348 } 3349 return err; 3350 } 3351 #endif/* DDR_FAST_INIT */ 3352 3353 static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) 3354 { 3355 uint32_t i; 3356 uint32_t ch, slice; 3357 uint32_t tgt_cs, src_cs; 3358 uint32_t tmp_r; 3359 3360 /* copy of training results */ 3361 foreach_vch(ch) { 3362 for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { 3363 for (slice = 0; slice < SLICE_CNT; slice++) { 3364 ddr_setval_s(ch, slice, 3365 _reg_PHY_PER_CS_TRAINING_INDEX, 3366 tgt_cs); 3367 src_cs = ddr_csn % 2; 3368 if (!(ch_have_this_cs[1] & (1U << ch))) 3369 src_cs = 0; 3370 for (i = 0; i <= 4; i += 4) { 3371 if (restore) 3372 tmp_r = 3373 rdqdm_dly[ch][tgt_cs][slice] 3374 [i]; 3375 else 3376 tmp_r = 3377 rdqdm_dly[ch][src_cs][slice] 3378 [i]; 3379 3380 ddr_setval_s(ch, slice, 3381 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 3382 [i], tmp_r); 3383 } 3384 } 3385 } 3386 } 3387 } 3388 3389 static uint32_t wdqdm_man1(void) 3390 { 3391 int32_t k; 3392 uint32_t ch, cs, slice; 3393 uint32_t ddr_csn; 3394 uint32_t data_l; 3395 uint32_t err; 3396 uint32_t high_dq[DRAM_CH_CNT]; 3397 uint32_t mr14_csab0_bak[DRAM_CH_CNT]; 3398 #ifndef DDR_FAST_INIT 3399 uint32_t err_flg; 3400 #endif/* DDR_FAST_INIT */ 3401 3402 /* manual execution of training */ 3403 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3404 foreach_vch(ch) { 3405 high_dq[ch] = 0; 3406 for (slice = 0; slice < SLICE_CNT; slice++) { 3407 k = (board_cnf->ch[ch].dqs_swap >> 3408 (4 * slice)) & 0x0f; 3409 if (k >= 2) 3410 high_dq[ch] |= (1U << slice); 3411 } 3412 ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00); 3413 } 3414 } 3415 err = 0; 3416 /* CLEAR PREV RESULT */ 3417 for (cs = 0; cs < CS_CNT; cs++) { 3418 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); 3419 if (((prr_product == PRR_PRODUCT_H3) && 3420 (prr_cut > PRR_PRODUCT_11)) || 3421 (prr_product == PRR_PRODUCT_M3N) || 3422 (prr_product == PRR_PRODUCT_V3H)) { 3423 ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 3424 0x01); 3425 } else { 3426 ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 3427 0x01); 3428 } 3429 } 3430 ddrphy_regif_idle(); 3431 3432 #ifndef DDR_FAST_INIT 3433 err_flg = 0; 3434 #endif/* DDR_FAST_INIT */ 3435 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3436 if ((prr_product == PRR_PRODUCT_H3) && 3437 (prr_cut <= PRR_PRODUCT_11)) { 3438 foreach_vch(ch) { 3439 data_l = mmio_read_32(DBSC_DBDFICNT(ch)); 3440 data_l &= ~(0x00ffU << 16); 3441 3442 if (ddr_csn >= 2) 3443 k = (high_dq[ch] ^ 0x0f); 3444 else 3445 k = high_dq[ch]; 3446 data_l |= (k << 16); 3447 mmio_write_32(DBSC_DBDFICNT(ch), data_l); 3448 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); 3449 } 3450 } 3451 if (((prr_product == PRR_PRODUCT_H3) && 3452 (prr_cut <= PRR_PRODUCT_11)) || 3453 ((prr_product == PRR_PRODUCT_M3) && 3454 (prr_cut == PRR_PRODUCT_10))) { 3455 wdqdm_cp(ddr_csn, 0); 3456 } 3457 3458 foreach_vch(ch) { 3459 data_l = 3460 ddr_getval(ch, 3461 reg_pi_mr14_data_fx_csx[1][ddr_csn]); 3462 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l); 3463 } 3464 3465 /* KICK WDQLVL */ 3466 err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); 3467 if (err) 3468 goto err_exit; 3469 3470 if (ddr_csn == 0) 3471 foreach_vch(ch) { 3472 mr14_csab0_bak[ch] = 3473 ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]); 3474 } else 3475 foreach_vch(ch) { 3476 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], 3477 mr14_csab0_bak[ch]); 3478 } 3479 #ifndef DDR_FAST_INIT 3480 foreach_vch(ch) { 3481 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { 3482 wdqdm_clr1(ch, ddr_csn); 3483 continue; 3484 } 3485 err = wdqdm_ana1(ch, ddr_csn); 3486 if (err) 3487 err_flg |= (1U << (ddr_csn * 4 + ch)); 3488 ddrphy_regif_idle(); 3489 } 3490 #endif/* DDR_FAST_INIT */ 3491 } 3492 err_exit: 3493 #ifndef DDR_FAST_INIT 3494 err |= err_flg; 3495 #endif/* DDR_FAST_INIT */ 3496 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3497 ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); 3498 foreach_vch(ch) { 3499 data_l = mmio_read_32(DBSC_DBDFICNT(ch)); 3500 data_l &= ~(0x00ffU << 16); 3501 mmio_write_32(DBSC_DBDFICNT(ch), data_l); 3502 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); 3503 } 3504 } 3505 return err; 3506 } 3507 3508 static uint32_t wdqdm_man(void) 3509 { 3510 uint32_t err, retry_cnt; 3511 const uint32_t retry_max = 0x10; 3512 uint32_t datal, ch, ddr_csn, mr14_bkup[4][4]; 3513 3514 datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19; 3515 if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal) 3516 datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF; 3517 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal); 3518 3519 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 3520 (prr_product == PRR_PRODUCT_M3N) || 3521 (prr_product == PRR_PRODUCT_V3H)) { 3522 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, 3523 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3524 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, 3525 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3526 } else { 3527 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, 3528 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3529 } 3530 ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); 3531 ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); 3532 3533 retry_cnt = 0; 3534 err = 0; 3535 do { 3536 if ((prr_product == PRR_PRODUCT_H3) && 3537 (prr_cut <= PRR_PRODUCT_11)) { 3538 err = wdqdm_man1(); 3539 } else { 3540 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); 3541 ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 3542 0x01); 3543 if ((prr_product == PRR_PRODUCT_M3N) || 3544 (prr_product == PRR_PRODUCT_V3H)) { 3545 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3546 0x0C); 3547 } else { 3548 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); 3549 } 3550 dsb_sev(); 3551 err = wdqdm_man1(); 3552 foreach_vch(ch) { 3553 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3554 mr14_bkup[ch][ddr_csn] = 3555 ddr_getval(ch, 3556 reg_pi_mr14_data_fx_csx 3557 [1][ddr_csn]); 3558 dsb_sev(); 3559 } 3560 } 3561 3562 if ((prr_product == PRR_PRODUCT_M3N) || 3563 (prr_product == PRR_PRODUCT_V3H)) { 3564 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3565 0x04); 3566 } else { 3567 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); 3568 } 3569 pvtcode_update(); 3570 err = wdqdm_man1(); 3571 foreach_vch(ch) { 3572 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3573 mr14_bkup[ch][ddr_csn] = 3574 (mr14_bkup[ch][ddr_csn] + 3575 ddr_getval(ch, 3576 reg_pi_mr14_data_fx_csx 3577 [1][ddr_csn])) / 2; 3578 ddr_setval(ch, 3579 reg_pi_mr14_data_fx_csx[1] 3580 [ddr_csn], 3581 mr14_bkup[ch][ddr_csn]); 3582 } 3583 } 3584 3585 ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 3586 0x00); 3587 if ((prr_product == PRR_PRODUCT_M3N) || 3588 (prr_product == PRR_PRODUCT_V3H)) { 3589 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3590 0x00); 3591 ddr_setval_ach 3592 (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, 3593 0x00); 3594 ddr_setval_ach 3595 (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, 3596 0x00); 3597 } else { 3598 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); 3599 ddr_setval_ach 3600 (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 3601 0x00); 3602 ddr_setval_ach 3603 (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 3604 0x00); 3605 } 3606 ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 3607 0x00); 3608 3609 pvtcode_update2(); 3610 err = wdqdm_man1(); 3611 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); 3612 } 3613 } while (err && (++retry_cnt < retry_max)); 3614 3615 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 3616 ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { 3617 wdqdm_cp(0, 1); 3618 } 3619 3620 return (retry_cnt >= retry_max); 3621 } 3622 3623 /* RDQ TRAINING */ 3624 #ifndef DDR_FAST_INIT 3625 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) 3626 { 3627 int32_t i, k; 3628 uint32_t cs, slice; 3629 uint32_t data_l; 3630 3631 /* clr of training results buffer */ 3632 cs = ddr_csn % 2; 3633 data_l = board_cnf->dqdm_dly_r; 3634 for (slice = 0; slice < SLICE_CNT; slice++) { 3635 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3636 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3637 continue; 3638 3639 for (i = 0; i <= 8; i++) { 3640 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) { 3641 rdqdm_dly[ch][cs][slice][i] = 3642 rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; 3643 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = 3644 rdqdm_dly[ch][CS_CNT - 1 - cs][slice + 3645 SLICE_CNT] 3646 [i]; 3647 } else { 3648 rdqdm_dly[ch][cs][slice][i] = data_l; 3649 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = 3650 data_l; 3651 } 3652 rdqdm_le[ch][cs][slice][i] = 0; 3653 rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; 3654 rdqdm_te[ch][cs][slice][i] = 0; 3655 rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; 3656 rdqdm_nw[ch][cs][slice][i] = 0; 3657 rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; 3658 } 3659 rdqdm_st[ch][cs][slice] = 0; 3660 rdqdm_win[ch][cs][slice] = 0; 3661 } 3662 } 3663 3664 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) 3665 { 3666 int32_t i, k; 3667 uint32_t cs, slice; 3668 uint32_t data_l; 3669 uint32_t err; 3670 int8_t _adj; 3671 int16_t adj; 3672 uint32_t dq; 3673 int32_t min_win; 3674 int32_t win; 3675 uint32_t rdq_status_obs_select; 3676 3677 /* analysis of training results */ 3678 err = 0; 3679 for (slice = 0; slice < SLICE_CNT; slice++) { 3680 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3681 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3682 continue; 3683 3684 cs = ddr_csn % 2; 3685 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); 3686 ddrphy_regif_idle(); 3687 3688 ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); 3689 ddrphy_regif_idle(); 3690 3691 for (i = 0; i <= 8; i++) { 3692 dq = slice * 8 + i; 3693 if (i == 8) 3694 _adj = board_cnf->ch[ch].dm_adj_r[slice]; 3695 else 3696 _adj = board_cnf->ch[ch].dq_adj_r[dq]; 3697 3698 adj = _f_scale_adj(_adj); 3699 3700 data_l = 3701 ddr_getval_s(ch, slice, 3702 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + 3703 adj; 3704 ddr_setval_s(ch, slice, 3705 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], 3706 data_l); 3707 rdqdm_dly[ch][cs][slice][i] = data_l; 3708 3709 data_l = 3710 ddr_getval_s(ch, slice, 3711 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + 3712 adj; 3713 ddr_setval_s(ch, slice, 3714 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], 3715 data_l); 3716 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; 3717 } 3718 min_win = INT_LEAST32_MAX; 3719 for (i = 0; i <= 8; i++) { 3720 data_l = 3721 ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); 3722 rdqdm_st[ch][cs][slice] = data_l; 3723 rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l; 3724 /* k : rise/fall */ 3725 for (k = 0; k < 2; k++) { 3726 if (i == 8) { 3727 rdq_status_obs_select = 16 + 8 * k; 3728 } else { 3729 rdq_status_obs_select = i + k * 8; 3730 } 3731 ddr_setval_s(ch, slice, 3732 _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, 3733 rdq_status_obs_select); 3734 3735 data_l = 3736 ddr_getval_s(ch, slice, 3737 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); 3738 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = 3739 data_l; 3740 3741 data_l = 3742 ddr_getval_s(ch, slice, 3743 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); 3744 rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = 3745 data_l; 3746 3747 data_l = 3748 ddr_getval_s(ch, slice, 3749 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); 3750 rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = 3751 data_l; 3752 3753 win = 3754 (int32_t)rdqdm_te[ch][cs][slice + 3755 SLICE_CNT * 3756 k][i] - 3757 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; 3758 if (i != 8) { 3759 if (min_win > win) 3760 min_win = win; 3761 } 3762 } 3763 } 3764 rdqdm_win[ch][cs][slice] = min_win; 3765 if (min_win <= 0) { 3766 err = 2; 3767 } 3768 } 3769 return err; 3770 } 3771 #endif/* DDR_FAST_INIT */ 3772 3773 static uint32_t rdqdm_man1(void) 3774 { 3775 uint32_t ch; 3776 uint32_t ddr_csn; 3777 #ifdef DDR_FAST_INIT 3778 uint32_t slice; 3779 uint32_t i, adj, data_l; 3780 #endif/* DDR_FAST_INIT */ 3781 uint32_t err; 3782 3783 /* manual execution of training */ 3784 err = 0; 3785 3786 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3787 /* KICK RDQLVL */ 3788 err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); 3789 if (err) 3790 goto err_exit; 3791 #ifndef DDR_FAST_INIT 3792 foreach_vch(ch) { 3793 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { 3794 rdqdm_clr1(ch, ddr_csn); 3795 ddrphy_regif_idle(); 3796 continue; 3797 } 3798 err = rdqdm_ana1(ch, ddr_csn); 3799 ddrphy_regif_idle(); 3800 if (err) 3801 goto err_exit; 3802 } 3803 #else/* DDR_FAST_INIT */ 3804 foreach_vch(ch) { 3805 if (ch_have_this_cs[ddr_csn] & (1U << ch)) { 3806 for (slice = 0; slice < SLICE_CNT; slice++) { 3807 if (ddr_getval_s(ch, slice, 3808 _reg_PHY_RDLVL_STATUS_OBS) != 3809 0x0D00FFFF) { 3810 err = (1U << ch) | 3811 (0x10U << slice); 3812 goto err_exit; 3813 } 3814 } 3815 } 3816 if (((prr_product == PRR_PRODUCT_H3) && 3817 (prr_cut <= PRR_PRODUCT_11)) || 3818 ((prr_product == PRR_PRODUCT_M3) && 3819 (prr_cut <= PRR_PRODUCT_10))) { 3820 for (slice = 0; slice < SLICE_CNT; slice++) { 3821 for (i = 0; i <= 8; i++) { 3822 if (i == 8) 3823 adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]); 3824 else 3825 adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]); 3826 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); 3827 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; 3828 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l); 3829 rdqdm_dly[ch][ddr_csn][slice][i] = data_l; 3830 rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l; 3831 3832 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; 3833 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l); 3834 rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l; 3835 rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l; 3836 } 3837 } 3838 } 3839 } 3840 ddrphy_regif_idle(); 3841 3842 #endif/* DDR_FAST_INIT */ 3843 } 3844 3845 err_exit: 3846 return err; 3847 } 3848 3849 static uint32_t rdqdm_man(void) 3850 { 3851 uint32_t err, retry_cnt; 3852 const uint32_t retry_max = 0x01; 3853 3854 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, 3855 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3856 _reg_PHY_DQ_TSEL_ENABLE)); 3857 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, 3858 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3859 _reg_PHY_DQS_TSEL_ENABLE)); 3860 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, 3861 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3862 _reg_PHY_DQ_TSEL_SELECT)); 3863 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, 3864 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3865 _reg_PHY_DQS_TSEL_SELECT)); 3866 3867 retry_cnt = 0; 3868 do { 3869 err = rdqdm_man1(); 3870 ddrphy_regif_idle(); 3871 } while (err && (++retry_cnt < retry_max)); 3872 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, 3873 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3874 _reg_PHY_DQ_TSEL_ENABLE)); 3875 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, 3876 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3877 _reg_PHY_DQS_TSEL_ENABLE)); 3878 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, 3879 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3880 _reg_PHY_DQ_TSEL_SELECT)); 3881 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, 3882 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3883 _reg_PHY_DQS_TSEL_SELECT)); 3884 3885 return (retry_cnt >= retry_max); 3886 } 3887 3888 /* rx offset calibration */ 3889 static int32_t _find_change(uint64_t val, uint32_t dir) 3890 { 3891 int32_t i; 3892 uint32_t startval; 3893 uint32_t curval; 3894 const int32_t VAL_END = 0x3f; 3895 3896 if (dir == 0) { 3897 startval = (val & 0x01); 3898 for (i = 1; i <= VAL_END; i++) { 3899 curval = (val >> i) & 0x01; 3900 if (curval != startval) 3901 return i; 3902 } 3903 return VAL_END; 3904 } 3905 3906 startval = (val >> dir) & 0x01; 3907 for (i = dir - 1; i >= 0; i--) { 3908 curval = (val >> i) & 0x01; 3909 if (curval != startval) 3910 return i; 3911 } 3912 return 0; 3913 } 3914 3915 static uint32_t _rx_offset_cal_updn(uint32_t code) 3916 { 3917 const uint32_t CODE_MAX = 0x40; 3918 uint32_t tmp; 3919 3920 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3921 if (code == 0) 3922 tmp = (1U << 6) | (CODE_MAX - 1); 3923 else if (code <= 0x20) 3924 tmp = 3925 ((CODE_MAX - 1 - 3926 (0x20 - code) * 2) << 6) | (CODE_MAX - 1); 3927 else 3928 tmp = 3929 ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 - 3930 (code - 0x20) * 2); 3931 } else { 3932 if (code == 0) 3933 tmp = (1U << 6) | (CODE_MAX - 1); 3934 else 3935 tmp = (code << 6) | (CODE_MAX - code); 3936 } 3937 return tmp; 3938 } 3939 3940 static uint32_t rx_offset_cal(void) 3941 { 3942 uint32_t index; 3943 uint32_t code; 3944 const uint32_t CODE_MAX = 0x40; 3945 const uint32_t CODE_STEP = 2; 3946 uint32_t ch, slice; 3947 uint32_t tmp; 3948 uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; 3949 uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; 3950 uint64_t tmpval; 3951 int32_t lsb, msb; 3952 3953 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); 3954 foreach_vch(ch) { 3955 for (slice = 0; slice < SLICE_CNT; slice++) { 3956 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) 3957 val[ch][slice][index] = 0; 3958 } 3959 } 3960 3961 for (code = 0; code < CODE_MAX / CODE_STEP; code++) { 3962 tmp = _rx_offset_cal_updn(code * CODE_STEP); 3963 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { 3964 ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); 3965 } 3966 dsb_sev(); 3967 ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); 3968 3969 foreach_vch(ch) { 3970 for (slice = 0; slice < SLICE_CNT; slice++) { 3971 tmp = tmp_ach_as[ch][slice]; 3972 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; 3973 index++) { 3974 if (tmp & (1U << index)) { 3975 val[ch][slice][index] |= 3976 (1ULL << code); 3977 } else { 3978 val[ch][slice][index] &= 3979 ~(1ULL << code); 3980 } 3981 } 3982 } 3983 } 3984 } 3985 foreach_vch(ch) { 3986 for (slice = 0; slice < SLICE_CNT; slice++) { 3987 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; 3988 index++) { 3989 tmpval = val[ch][slice][index]; 3990 lsb = _find_change(tmpval, 0); 3991 msb = 3992 _find_change(tmpval, 3993 (CODE_MAX / CODE_STEP) - 1); 3994 tmp = (lsb + msb) >> 1; 3995 3996 tmp = _rx_offset_cal_updn(tmp * CODE_STEP); 3997 ddr_setval_s(ch, slice, 3998 _reg_PHY_RX_CAL_X[index], tmp); 3999 } 4000 } 4001 } 4002 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); 4003 4004 return 0; 4005 } 4006 4007 static uint32_t rx_offset_cal_hw(void) 4008 { 4009 uint32_t ch, slice; 4010 uint32_t retry; 4011 uint32_t complete; 4012 uint32_t tmp; 4013 uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; 4014 4015 ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); 4016 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); 4017 ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); 4018 4019 retry = 0; 4020 while (retry < 4096) { 4021 if ((retry & 0xff) == 0) { 4022 ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); 4023 } 4024 foreach_vch(ch) 4025 for (slice = 0; slice < SLICE_CNT; slice++) 4026 tmp_ach_as[ch][slice] = 4027 ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); 4028 4029 complete = 1; 4030 foreach_vch(ch) { 4031 for (slice = 0; slice < SLICE_CNT; slice++) { 4032 tmp = tmp_ach_as[ch][slice]; 4033 tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); 4034 if (((prr_product == PRR_PRODUCT_H3) && 4035 (prr_cut > PRR_PRODUCT_11)) || 4036 (prr_product == PRR_PRODUCT_M3N) || 4037 (prr_product == PRR_PRODUCT_V3H)) { 4038 if (tmp != 0x3E) 4039 complete = 0; 4040 } else { 4041 if (tmp != 0x40) 4042 complete = 0; 4043 } 4044 } 4045 } 4046 if (complete) 4047 break; 4048 4049 retry++; 4050 } 4051 4052 return (complete == 0); 4053 } 4054 4055 /* adjust rddqs latency */ 4056 static void adjust_rddqs_latency(void) 4057 { 4058 uint32_t ch, slice; 4059 uint32_t dly; 4060 uint32_t maxlatx2; 4061 uint32_t tmp; 4062 uint32_t rdlat_adjx2[SLICE_CNT]; 4063 4064 foreach_vch(ch) { 4065 maxlatx2 = 0; 4066 for (slice = 0; slice < SLICE_CNT; slice++) { 4067 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, 4068 0x00); 4069 4070 dly = 4071 ddr_getval_s(ch, slice, 4072 _reg_PHY_RDDQS_GATE_SLAVE_DELAY); 4073 tmp = 4074 ddr_getval_s(ch, slice, 4075 _reg_PHY_RDDQS_LATENCY_ADJUST); 4076 /* note gate_slave_delay[9] is always 0 */ 4077 tmp = (tmp << 1) + (dly >> 8); 4078 rdlat_adjx2[slice] = tmp; 4079 if (maxlatx2 < tmp) 4080 maxlatx2 = tmp; 4081 } 4082 maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; 4083 for (slice = 0; slice < SLICE_CNT; slice++) { 4084 tmp = maxlatx2 - rdlat_adjx2[slice]; 4085 tmp = (tmp >> 1); 4086 if (tmp) { 4087 ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, 4088 ddr_getval_s(ch, slice, 4089 _reg_PHY_RPTR_UPDATE) 4090 + 1); 4091 } 4092 } 4093 } 4094 } 4095 4096 /* adjust wpath latency */ 4097 static void adjust_wpath_latency(void) 4098 { 4099 uint32_t ch, cs, slice; 4100 uint32_t dly; 4101 uint32_t wpath_add; 4102 const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; 4103 4104 foreach_vch(ch) { 4105 for (slice = 0; slice < SLICE_CNT; slice += 1) { 4106 for (cs = 0; cs < CS_CNT; cs++) { 4107 ddr_setval_s(ch, slice, 4108 _reg_PHY_PER_CS_TRAINING_INDEX, 4109 cs); 4110 ddr_getval_s(ch, slice, 4111 _reg_PHY_PER_CS_TRAINING_INDEX); 4112 dly = 4113 ddr_getval_s(ch, slice, 4114 _reg_PHY_CLK_WRDQS_SLAVE_DELAY); 4115 if (dly <= _par_EARLY_THRESHOLD_VAL) 4116 continue; 4117 4118 wpath_add = 4119 ddr_getval_s(ch, slice, 4120 _reg_PHY_WRITE_PATH_LAT_ADD); 4121 ddr_setval_s(ch, slice, 4122 _reg_PHY_WRITE_PATH_LAT_ADD, 4123 wpath_add - 1); 4124 } 4125 } 4126 } 4127 } 4128 4129 /* DDR Initialize entry */ 4130 int32_t rcar_dram_init(void) 4131 { 4132 uint32_t ch, cs; 4133 uint32_t data_l; 4134 uint32_t bus_mbps, bus_mbpsdiv; 4135 uint32_t tmp_tccd; 4136 uint32_t failcount; 4137 uint32_t cnf_boardtype; 4138 4139 /* Thermal sensor setting */ 4140 data_l = mmio_read_32(CPG_MSTPSR5); 4141 if (data_l & BIT(22)) { /* case THS/TSC Standby */ 4142 data_l &= ~BIT(22); 4143 cpg_write_32(CPG_SMSTPCR5, data_l); 4144 while (mmio_read_32(CPG_MSTPSR5) & BIT(22)) 4145 ; /* wait bit=0 */ 4146 } 4147 4148 /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ 4149 data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; 4150 mmio_write_32(THS1_THCTR, data_l); 4151 4152 /* Judge product and cut */ 4153 #ifdef RCAR_DDR_FIXED_LSI_TYPE 4154 #if (RCAR_LSI == RCAR_AUTO) 4155 prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; 4156 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4157 #else /* RCAR_LSI */ 4158 #ifndef RCAR_LSI_CUT 4159 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4160 #endif /* RCAR_LSI_CUT */ 4161 #endif /* RCAR_LSI */ 4162 #else /* RCAR_DDR_FIXED_LSI_TYPE */ 4163 prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; 4164 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4165 #endif /* RCAR_DDR_FIXED_LSI_TYPE */ 4166 4167 if (prr_product == PRR_PRODUCT_H3) { 4168 if (prr_cut <= PRR_PRODUCT_11) { 4169 p_ddr_regdef_tbl = 4170 (const uint32_t *)&DDR_REGDEF_TBL[0][0]; 4171 } else { 4172 p_ddr_regdef_tbl = 4173 (const uint32_t *)&DDR_REGDEF_TBL[2][0]; 4174 } 4175 } else if (prr_product == PRR_PRODUCT_M3) { 4176 p_ddr_regdef_tbl = 4177 (const uint32_t *)&DDR_REGDEF_TBL[1][0]; 4178 } else if ((prr_product == PRR_PRODUCT_M3N) || 4179 (prr_product == PRR_PRODUCT_V3H)) { 4180 p_ddr_regdef_tbl = 4181 (const uint32_t *)&DDR_REGDEF_TBL[3][0]; 4182 } else { 4183 FATAL_MSG("BL2: DDR:Unknown Product\n"); 4184 return 0xff; 4185 } 4186 4187 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 4188 ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { 4189 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 4190 } else { 4191 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); 4192 } 4193 4194 /* Judge board type */ 4195 cnf_boardtype = boardcnf_get_brd_type(); 4196 if (cnf_boardtype >= BOARDNUM) { 4197 FATAL_MSG("BL2: DDR:Unknown Board\n"); 4198 return 0xff; 4199 } 4200 board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype]; 4201 4202 /* RCAR_DRAM_SPLIT_2CH (2U) */ 4203 #if RCAR_DRAM_SPLIT == 2 4204 /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */ 4205 if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { 4206 mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); 4207 ddr_phyvalid = 0x03; 4208 } else { 4209 ddr_phyvalid = board_cnf->phyvalid; 4210 } 4211 #else /* RCAR_DRAM_SPLIT_2CH */ 4212 ddr_phyvalid = board_cnf->phyvalid; 4213 #endif /* RCAR_DRAM_SPLIT_2CH */ 4214 4215 max_density = 0; 4216 4217 for (cs = 0; cs < CS_CNT; cs++) { 4218 ch_have_this_cs[cs] = 0; 4219 } 4220 4221 foreach_ech(ch) 4222 for (cs = 0; cs < CS_CNT; cs++) 4223 ddr_density[ch][cs] = 0xff; 4224 4225 foreach_vch(ch) { 4226 for (cs = 0; cs < CS_CNT; cs++) { 4227 data_l = board_cnf->ch[ch].ddr_density[cs]; 4228 ddr_density[ch][cs] = data_l; 4229 4230 if (data_l == 0xff) 4231 continue; 4232 if (data_l > max_density) 4233 max_density = data_l; 4234 if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) && 4235 (prr_cut <= PRR_PRODUCT_11)) 4236 continue; 4237 ch_have_this_cs[cs] |= (1U << ch); 4238 } 4239 } 4240 4241 /* Judge board clock frequency (in MHz) */ 4242 boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); 4243 if ((brd_clk / brd_clkdiv) > 25) { 4244 brd_clkdiva = 1; 4245 } else { 4246 brd_clkdiva = 0; 4247 } 4248 4249 /* Judge ddr operating frequency clock(in Mbps) */ 4250 boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); 4251 4252 ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); 4253 4254 ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, 4255 brd_clkdiv * (brd_clkdiva + 1)); 4256 4257 /* Adjust tccd */ 4258 data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; 4259 bus_mbps = 0; 4260 bus_mbpsdiv = 0; 4261 switch (data_l) { 4262 case 0: 4263 bus_mbps = brd_clk * 0x60 * 2; 4264 bus_mbpsdiv = brd_clkdiv * 1; 4265 break; 4266 case 1: 4267 bus_mbps = brd_clk * 0x50 * 2; 4268 bus_mbpsdiv = brd_clkdiv * 1; 4269 break; 4270 case 2: 4271 bus_mbps = brd_clk * 0x40 * 2; 4272 bus_mbpsdiv = brd_clkdiv * 1; 4273 break; 4274 case 3: 4275 bus_mbps = brd_clk * 0x60 * 2; 4276 bus_mbpsdiv = brd_clkdiv * 2; 4277 break; 4278 default: 4279 bus_mbps = brd_clk * 0x60 * 2; 4280 bus_mbpsdiv = brd_clkdiv * 2; 4281 break; 4282 } 4283 tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); 4284 if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) 4285 tmp_tccd = tmp_tccd + 1; 4286 4287 if (tmp_tccd < 8) 4288 ddr_tccd = 8; 4289 else 4290 ddr_tccd = tmp_tccd; 4291 4292 NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); 4293 4294 MSG_LF("Start\n"); 4295 4296 /* PLL Setting */ 4297 pll3_control(1); 4298 4299 /* initialize DDR */ 4300 data_l = init_ddr(); 4301 if (data_l == ddr_phyvalid) { 4302 failcount = 0; 4303 } else { 4304 failcount = 1; 4305 } 4306 4307 foreach_vch(ch) 4308 mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); 4309 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 4310 ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { 4311 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 4312 } else { 4313 mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); 4314 } 4315 4316 if (failcount == 0) { 4317 return INITDRAM_OK; 4318 } else { 4319 return INITDRAM_NG; 4320 } 4321 } 4322 4323 void pvtcode_update(void) 4324 { 4325 uint32_t ch; 4326 uint32_t data_l; 4327 uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; 4328 int32_t pvtp_tmp, pvtn_tmp; 4329 4330 foreach_vch(ch) { 4331 pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; 4332 pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; 4333 4334 if (8912 * pvtp_init > 44230) { 4335 pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; 4336 } else { 4337 pvtp_tmp = 4338 -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); 4339 } 4340 pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; 4341 4342 pvtn[ch] = pvtn_tmp + pvtn_init; 4343 pvtp[ch] = pvtp_tmp + pvtp_init; 4344 4345 if (pvtn[ch] > 63) { 4346 pvtn[ch] = 63; 4347 pvtp[ch] = 4348 (pvtp_tmp) * (63 - 6 * pvtn_tmp - 4349 pvtn_init) / (pvtn_tmp) + 4350 6 * pvtp_tmp + pvtp_init; 4351 } 4352 if ((prr_product == PRR_PRODUCT_H3) && 4353 (prr_cut <= PRR_PRODUCT_11)) { 4354 data_l = pvtp[ch] | (pvtn[ch] << 6) | 4355 (tcal.tcomp_cal[ch] & 0xfffff000); 4356 reg_ddrphy_write(ch, 4357 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4358 data_l | 0x00020000); 4359 reg_ddrphy_write(ch, 4360 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4361 data_l); 4362 reg_ddrphy_write(ch, 4363 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4364 data_l); 4365 reg_ddrphy_write(ch, 4366 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4367 data_l); 4368 reg_ddrphy_write(ch, 4369 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4370 data_l); 4371 } else { 4372 data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; 4373 reg_ddrphy_write(ch, 4374 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4375 data_l | 0x00020000); 4376 reg_ddrphy_write(ch, 4377 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4378 data_l); 4379 reg_ddrphy_write(ch, 4380 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4381 data_l); 4382 reg_ddrphy_write(ch, 4383 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4384 data_l); 4385 reg_ddrphy_write(ch, 4386 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4387 data_l); 4388 } 4389 } 4390 } 4391 4392 void pvtcode_update2(void) 4393 { 4394 uint32_t ch; 4395 4396 foreach_vch(ch) { 4397 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4398 tcal.init_cal[ch] | 0x00020000); 4399 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4400 tcal.init_cal[ch]); 4401 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4402 tcal.init_cal[ch]); 4403 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4404 tcal.init_cal[ch]); 4405 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4406 tcal.init_cal[ch]); 4407 } 4408 } 4409 4410 void ddr_padcal_tcompensate_getinit(uint32_t override) 4411 { 4412 uint32_t ch; 4413 uint32_t data_l; 4414 uint32_t pvtp, pvtn; 4415 4416 tcal.init_temp = 0; 4417 for (ch = 0; ch < 4; ch++) { 4418 tcal.init_cal[ch] = 0; 4419 tcal.tcomp_cal[ch] = 0; 4420 } 4421 4422 foreach_vch(ch) { 4423 tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); 4424 tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); 4425 } 4426 4427 if (!override) { 4428 data_l = mmio_read_32(THS1_TEMP); 4429 if (data_l < 2800) { 4430 tcal.init_temp = 4431 (143 * (int32_t)data_l - 359000) / 1000; 4432 } else { 4433 tcal.init_temp = 4434 (121 * (int32_t)data_l - 296300) / 1000; 4435 } 4436 4437 foreach_vch(ch) { 4438 pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; 4439 pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; 4440 if ((int32_t)pvtp > 4441 ((tcal.init_temp * 29 - 3625) / 1000)) 4442 pvtp = 4443 (int32_t)pvtp + 4444 ((3625 - tcal.init_temp * 29) / 1000); 4445 else 4446 pvtp = 0; 4447 4448 if ((int32_t)pvtn > 4449 ((tcal.init_temp * 54 - 6750) / 1000)) 4450 pvtn = 4451 (int32_t)pvtn + 4452 ((6750 - tcal.init_temp * 54) / 1000); 4453 else 4454 pvtn = 0; 4455 4456 if ((prr_product == PRR_PRODUCT_H3) && 4457 (prr_cut <= PRR_PRODUCT_11)) { 4458 tcal.init_cal[ch] = 4459 (tcal.init_cal[ch] & 0xfffff000) | 4460 (pvtn << 6) | 4461 pvtp; 4462 } else { 4463 tcal.init_cal[ch] = 4464 0x00015000 | (pvtn << 6) | pvtp; 4465 } 4466 } 4467 tcal.init_temp = 125; 4468 } 4469 } 4470 4471 #ifndef ddr_qos_init_setting 4472 /* For QoS init */ 4473 uint8_t get_boardcnf_phyvalid(void) 4474 { 4475 return ddr_phyvalid; 4476 } 4477 #endif /* ddr_qos_init_setting */ 4478