1 /* 2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <stdint.h> 9 #include <string.h> 10 #include <stdio.h> 11 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 15 #include "ddr_regdef.h" 16 #include "init_dram_tbl_h3.h" 17 #include "init_dram_tbl_m3.h" 18 #include "init_dram_tbl_h3ver2.h" 19 #include "init_dram_tbl_m3n.h" 20 #include "boot_init_dram_regdef.h" 21 #include "boot_init_dram.h" 22 #include "dram_sub_func.h" 23 #include "micro_delay.h" 24 #include "rcar_def.h" 25 26 #define DDR_BACKUPMODE 27 #define FATAL_MSG(x) NOTICE(x) 28 29 /* variables */ 30 #ifdef RCAR_DDR_FIXED_LSI_TYPE 31 #ifndef RCAR_AUTO 32 #define RCAR_AUTO 99 33 #define RCAR_H3 0 34 #define RCAR_M3 1 35 #define RCAR_M3N 2 36 #define RCAR_E3 3 /* NON */ 37 #define RCAR_H3N 4 38 39 #define RZ_G2M 100U 40 41 #define RCAR_CUT_10 0 42 #define RCAR_CUT_11 1 43 #define RCAR_CUT_20 10 44 #define RCAR_CUT_30 20 45 #endif 46 #ifndef RCAR_LSI 47 #define RCAR_LSI RCAR_AUTO 48 #endif 49 50 #if (RCAR_LSI == RCAR_AUTO) 51 static uint32_t prr_product; 52 static uint32_t prr_cut; 53 #else 54 #if (RCAR_LSI == RCAR_H3) 55 static const uint32_t prr_product = PRR_PRODUCT_H3; 56 #elif(RCAR_LSI == RCAR_M3 || RCAR_LSI == RZ_G2M) 57 static const uint32_t prr_product = PRR_PRODUCT_M3; 58 #elif(RCAR_LSI == RCAR_M3N) 59 static const uint32_t prr_product = PRR_PRODUCT_M3N; 60 #elif(RCAR_LSI == RCAR_H3N) 61 static const uint32_t prr_product = PRR_PRODUCT_H3; 62 #endif /* RCAR_LSI */ 63 64 #ifndef RCAR_LSI_CUT 65 static uint32_t prr_cut; 66 #else /* RCAR_LSI_CUT */ 67 #if (RCAR_LSI_CUT == RCAR_CUT_10) 68 static const uint32_t prr_cut = PRR_PRODUCT_10; 69 #elif(RCAR_LSI_CUT == RCAR_CUT_11) 70 static const uint32_t prr_cut = PRR_PRODUCT_11; 71 #elif(RCAR_LSI_CUT == RCAR_CUT_20) 72 static const uint32_t prr_cut = PRR_PRODUCT_20; 73 #elif(RCAR_LSI_CUT == RCAR_CUT_30) 74 static const uint32_t prr_cut = PRR_PRODUCT_30; 75 #endif /* RCAR_LSI_CUT */ 76 #endif /* RCAR_LSI_CUT */ 77 #endif /* RCAR_AUTO_NON */ 78 #else /* RCAR_DDR_FIXED_LSI_TYPE */ 79 static uint32_t prr_product; 80 static uint32_t prr_cut; 81 #endif /* RCAR_DDR_FIXED_LSI_TYPE */ 82 83 static const uint32_t *p_ddr_regdef_tbl; 84 static uint32_t brd_clk; 85 static uint32_t brd_clkdiv; 86 static uint32_t brd_clkdiva; 87 static uint32_t ddr_mbps; 88 static uint32_t ddr_mbpsdiv; 89 static uint32_t ddr_tccd; 90 static uint32_t ddr_phycaslice; 91 static const struct _boardcnf *board_cnf; 92 static uint32_t ddr_phyvalid; 93 static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; 94 static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); 95 static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9]; 96 static uint32_t max_density; 97 static uint32_t ddr0800_mul; 98 static uint32_t ddr_mul; 99 static uint32_t DDR_PHY_SLICE_REGSET_OFS; 100 static uint32_t DDR_PHY_ADR_V_REGSET_OFS; 101 static uint32_t DDR_PHY_ADR_I_REGSET_OFS; 102 static uint32_t DDR_PHY_ADR_G_REGSET_OFS; 103 static uint32_t DDR_PI_REGSET_OFS; 104 static uint32_t DDR_PHY_SLICE_REGSET_SIZE; 105 static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; 106 static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; 107 static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; 108 static uint32_t DDR_PI_REGSET_SIZE; 109 static uint32_t DDR_PHY_SLICE_REGSET_NUM; 110 static uint32_t DDR_PHY_ADR_V_REGSET_NUM; 111 static uint32_t DDR_PHY_ADR_I_REGSET_NUM; 112 static uint32_t DDR_PHY_ADR_G_REGSET_NUM; 113 static uint32_t DDR_PI_REGSET_NUM; 114 static uint32_t DDR_PHY_ADR_I_NUM; 115 #define DDR_PHY_REGSET_MAX 128 116 #define DDR_PI_REGSET_MAX 320 117 static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; 118 static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; 119 static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; 120 static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; 121 static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; 122 static uint32_t pll3_mode; 123 static uint32_t loop_max; 124 #ifdef DDR_BACKUPMODE 125 uint32_t ddr_backup; 126 /* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ 127 #endif 128 129 #ifdef ddr_qos_init_setting /* only for non qos_init */ 130 #define OPERATING_FREQ (400U) /* Mhz */ 131 #define BASE_SUB_SLOT_NUM (0x6U) 132 #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ 133 #define QOSWT_WTSET0_CYCLE \ 134 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \ 135 OPERATING_FREQ) /* unit:ns */ 136 137 uint32_t get_refperiod(void) 138 { 139 return QOSWT_WTSET0_CYCLE; 140 } 141 #else /* ddr_qos_init_setting // only for non qos_init */ 142 extern uint32_t get_refperiod(void); 143 #endif /* ddr_qos_init_setting // only for non qos_init */ 144 145 #define _reg_PHY_RX_CAL_X_NUM 11 146 static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { 147 _reg_PHY_RX_CAL_DQ0, 148 _reg_PHY_RX_CAL_DQ1, 149 _reg_PHY_RX_CAL_DQ2, 150 _reg_PHY_RX_CAL_DQ3, 151 _reg_PHY_RX_CAL_DQ4, 152 _reg_PHY_RX_CAL_DQ5, 153 _reg_PHY_RX_CAL_DQ6, 154 _reg_PHY_RX_CAL_DQ7, 155 _reg_PHY_RX_CAL_DM, 156 _reg_PHY_RX_CAL_DQS, 157 _reg_PHY_RX_CAL_FDBK 158 }; 159 160 #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 161 static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY 162 [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { 163 _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, 164 _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, 165 _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, 166 _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, 167 _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, 168 _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, 169 _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, 170 _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, 171 _reg_PHY_CLK_WRDM_SLAVE_DELAY, 172 _reg_PHY_CLK_WRDQS_SLAVE_DELAY 173 }; 174 175 #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 176 static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY 177 [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { 178 _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, 179 _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, 180 _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, 181 _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, 182 _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, 183 _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, 184 _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, 185 _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, 186 _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 187 }; 188 189 #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 190 static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 191 [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { 192 _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, 193 _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, 194 _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, 195 _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, 196 _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, 197 _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, 198 _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, 199 _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, 200 _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 201 }; 202 203 #define _reg_PHY_PAD_TERM_X_NUM 8 204 static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { 205 _reg_PHY_PAD_FDBK_TERM, 206 _reg_PHY_PAD_DATA_TERM, 207 _reg_PHY_PAD_DQS_TERM, 208 _reg_PHY_PAD_ADDR_TERM, 209 _reg_PHY_PAD_CLK_TERM, 210 _reg_PHY_PAD_CKE_TERM, 211 _reg_PHY_PAD_RST_TERM, 212 _reg_PHY_PAD_CS_TERM 213 }; 214 215 #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 216 static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X 217 [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { 218 _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, 219 _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, 220 _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, 221 _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, 222 _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, 223 _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, 224 225 _reg_PHY_GRP_SLAVE_DELAY_0, 226 _reg_PHY_GRP_SLAVE_DELAY_1, 227 _reg_PHY_GRP_SLAVE_DELAY_2, 228 _reg_PHY_GRP_SLAVE_DELAY_3 229 }; 230 231 /* Prototypes */ 232 static inline uint32_t vch_nxt(uint32_t pos); 233 static void cpg_write_32(uint32_t a, uint32_t v); 234 static void pll3_control(uint32_t high); 235 static inline void dsb_sev(void); 236 static void wait_dbcmd(void); 237 static void send_dbcmd(uint32_t cmd); 238 static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); 239 static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); 240 static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); 241 static inline uint32_t ddr_regdef(uint32_t _regdef); 242 static inline uint32_t ddr_regdef_adr(uint32_t _regdef); 243 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); 244 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, 245 uint32_t val); 246 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); 247 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); 248 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); 249 static void ddr_setval_ach(uint32_t regdef, uint32_t val); 250 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); 251 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); 252 static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); 253 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); 254 static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); 255 static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); 256 static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); 257 static uint32_t ddrphy_regif_chk(void); 258 static inline void ddrphy_regif_idle(void); 259 static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, 260 uint16_t cyc); 261 static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, 262 uint16_t *_js2); 263 static int16_t _f_scale_adj(int16_t ps); 264 static void ddrtbl_load(void); 265 static void ddr_config_sub(void); 266 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); 267 static void ddr_config_sub_h3v1x(void); 268 static void ddr_config(void); 269 static void dbsc_regset(void); 270 static void dbsc_regset_post(void); 271 static uint32_t dfi_init_start(void); 272 static void change_lpddr4_en(uint32_t mode); 273 static uint32_t set_term_code(void); 274 static void ddr_register_set(void); 275 static inline uint32_t wait_freqchgreq(uint32_t assert); 276 static inline void set_freqchgack(uint32_t assert); 277 static inline void set_dfifrequency(uint32_t freq); 278 static uint32_t pll3_freq(uint32_t on); 279 static void update_dly(void); 280 static uint32_t pi_training_go(void); 281 static uint32_t init_ddr(void); 282 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); 283 static uint32_t wdqdm_man1(void); 284 static uint32_t wdqdm_man(void); 285 static uint32_t rdqdm_man1(void); 286 static uint32_t rdqdm_man(void); 287 288 static int32_t _find_change(uint64_t val, uint32_t dir); 289 static uint32_t _rx_offset_cal_updn(uint32_t code); 290 static uint32_t rx_offset_cal(void); 291 static uint32_t rx_offset_cal_hw(void); 292 static void adjust_rddqs_latency(void); 293 static void adjust_wpath_latency(void); 294 295 struct ddrt_data { 296 int32_t init_temp; /* Initial Temperature (do) */ 297 uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ 298 uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */ 299 }; 300 301 static struct ddrt_data tcal; 302 303 static void pvtcode_update(void); 304 static void pvtcode_update2(void); 305 static void ddr_padcal_tcompensate_getinit(uint32_t override); 306 307 /* load board configuration */ 308 #include "boot_init_dram_config.c" 309 310 #ifndef DDR_FAST_INIT 311 static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 312 static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 313 static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; 314 static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 315 static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; 316 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); 317 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); 318 319 static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 320 static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 321 static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; 322 static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 323 static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; 324 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); 325 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); 326 #endif/* DDR_FAST_INIT */ 327 328 /* macro for channel selection loop */ 329 static inline uint32_t vch_nxt(uint32_t pos) 330 { 331 uint32_t posn; 332 333 for (posn = pos; posn < DRAM_CH_CNT; posn++) { 334 if (ddr_phyvalid & (1U << posn)) 335 break; 336 } 337 return posn; 338 } 339 340 #define foreach_vch(ch) \ 341 for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) 342 343 #define foreach_ech(ch) \ 344 for (ch = 0; ch < DRAM_CH_CNT; ch++) 345 346 /* Printing functions */ 347 #define MSG_LF(...) 348 349 /* clock settings, reset control */ 350 static void cpg_write_32(uint32_t a, uint32_t v) 351 { 352 mmio_write_32(CPG_CPGWPR, ~v); 353 mmio_write_32(a, v); 354 } 355 356 static void pll3_control(uint32_t high) 357 { 358 uint32_t data_l, data_div, data_mul, tmp_div; 359 360 if (high) { 361 tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / 362 (brd_clk * ddr_mul) / 2; 363 data_mul = ((ddr_mul * tmp_div) - 1) << 24; 364 pll3_mode = 1; 365 loop_max = 2; 366 } else { 367 tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / 368 (brd_clk * ddr0800_mul) / 2; 369 data_mul = ((ddr0800_mul * tmp_div) - 1) << 24; 370 pll3_mode = 0; 371 loop_max = 8; 372 } 373 374 switch (tmp_div) { 375 case 1: 376 data_div = 0; 377 break; 378 case 2: 379 case 3: 380 case 4: 381 data_div = tmp_div; 382 break; 383 default: 384 data_div = 6; 385 data_mul = (data_mul * tmp_div) / 3; 386 break; 387 } 388 data_mul = data_mul | (brd_clkdiva << 7); 389 390 /* PLL3 disable */ 391 data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; 392 cpg_write_32(CPG_PLLECR, data_l); 393 dsb_sev(); 394 395 if ((prr_product == PRR_PRODUCT_M3) || 396 ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) { 397 /* PLL3 DIV resetting(Lowest value:3) */ 398 data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); 399 cpg_write_32(CPG_FRQCRD, data_l); 400 dsb_sev(); 401 402 /* zb3 clk stop */ 403 data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); 404 cpg_write_32(CPG_ZB3CKCR, data_l); 405 dsb_sev(); 406 407 /* PLL3 enable */ 408 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); 409 cpg_write_32(CPG_PLLECR, data_l); 410 dsb_sev(); 411 412 do { 413 data_l = mmio_read_32(CPG_PLLECR); 414 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 415 dsb_sev(); 416 417 /* PLL3 DIV resetting (Highest value:0) */ 418 data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); 419 cpg_write_32(CPG_FRQCRD, data_l); 420 dsb_sev(); 421 422 /* DIV SET KICK */ 423 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 424 cpg_write_32(CPG_FRQCRB, data_l); 425 dsb_sev(); 426 427 /* PLL3 multiplie set */ 428 cpg_write_32(CPG_PLL3CR, data_mul); 429 dsb_sev(); 430 431 do { 432 data_l = mmio_read_32(CPG_PLLECR); 433 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 434 dsb_sev(); 435 436 /* PLL3 DIV resetting(Target value) */ 437 data_l = (data_div << 16) | data_div | 438 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); 439 cpg_write_32(CPG_FRQCRD, data_l); 440 dsb_sev(); 441 442 /* DIV SET KICK */ 443 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 444 cpg_write_32(CPG_FRQCRB, data_l); 445 dsb_sev(); 446 447 do { 448 data_l = mmio_read_32(CPG_PLLECR); 449 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 450 dsb_sev(); 451 452 /* zb3 clk start */ 453 data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); 454 cpg_write_32(CPG_ZB3CKCR, data_l); 455 dsb_sev(); 456 457 } else { /* H3Ver.3.0/M3N/V3H */ 458 459 /* PLL3 multiplie set */ 460 cpg_write_32(CPG_PLL3CR, data_mul); 461 dsb_sev(); 462 463 /* PLL3 DIV set(Target value) */ 464 data_l = (data_div << 16) | data_div | 465 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); 466 cpg_write_32(CPG_FRQCRD, data_l); 467 468 /* DIV SET KICK */ 469 data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); 470 cpg_write_32(CPG_FRQCRB, data_l); 471 dsb_sev(); 472 473 /* PLL3 enable */ 474 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); 475 cpg_write_32(CPG_PLLECR, data_l); 476 dsb_sev(); 477 478 do { 479 data_l = mmio_read_32(CPG_PLLECR); 480 } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); 481 dsb_sev(); 482 } 483 } 484 485 /* barrier */ 486 static inline void dsb_sev(void) 487 { 488 __asm__ __volatile__("dsb sy"); 489 } 490 491 /* DDR memory register access */ 492 static void wait_dbcmd(void) 493 { 494 uint32_t data_l; 495 /* dummy read */ 496 data_l = mmio_read_32(DBSC_DBCMD); 497 dsb_sev(); 498 while (1) { 499 /* wait DBCMD 1=busy, 0=ready */ 500 data_l = mmio_read_32(DBSC_DBWAIT); 501 dsb_sev(); 502 if ((data_l & 0x00000001) == 0x00) 503 break; 504 } 505 } 506 507 static void send_dbcmd(uint32_t cmd) 508 { 509 /* dummy read */ 510 wait_dbcmd(); 511 mmio_write_32(DBSC_DBCMD, cmd); 512 dsb_sev(); 513 } 514 515 static void dbwait_loop(uint32_t wait_loop) 516 { 517 uint32_t i; 518 519 for (i = 0; i < wait_loop; i++) 520 wait_dbcmd(); 521 } 522 523 /* DDRPHY register access (raw) */ 524 static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) 525 { 526 uint32_t val; 527 uint32_t loop; 528 529 val = 0; 530 if ((prr_product != PRR_PRODUCT_M3N) && 531 (prr_product != PRR_PRODUCT_V3H)) { 532 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 533 dsb_sev(); 534 535 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 536 dsb_sev(); 537 } 538 dsb_sev(); 539 540 for (loop = 0; loop < loop_max; loop++) { 541 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 542 dsb_sev(); 543 } 544 (void)val; 545 } else { 546 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); 547 dsb_sev(); 548 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != 549 (regadd | 0x0000C000)) { 550 dsb_sev(); 551 }; 552 val = mmio_read_32(DBSC_DBPDRGA(phyno)); 553 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 554 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 555 dsb_sev(); 556 }; 557 dsb_sev(); 558 559 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 560 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 561 dsb_sev(); 562 }; 563 564 dsb_sev(); 565 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 566 dsb_sev(); 567 (void)val; 568 } 569 return val; 570 } 571 572 static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) 573 { 574 uint32_t val; 575 uint32_t loop; 576 577 if ((prr_product != PRR_PRODUCT_M3N) && 578 (prr_product != PRR_PRODUCT_V3H)) { 579 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 580 dsb_sev(); 581 for (loop = 0; loop < loop_max; loop++) { 582 val = mmio_read_32(DBSC_DBPDRGA(phyno)); 583 dsb_sev(); 584 } 585 mmio_write_32(DBSC_DBPDRGD(phyno), regdata); 586 dsb_sev(); 587 588 for (loop = 0; loop < loop_max; loop++) { 589 val = mmio_read_32(DBSC_DBPDRGD(phyno)); 590 dsb_sev(); 591 } 592 } else { 593 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 594 dsb_sev(); 595 596 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 597 dsb_sev(); 598 }; 599 dsb_sev(); 600 601 mmio_write_32(DBSC_DBPDRGD(phyno), regdata); 602 dsb_sev(); 603 604 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != 605 (regadd | 0x00008000)) { 606 dsb_sev(); 607 }; 608 mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); 609 610 while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { 611 dsb_sev(); 612 }; 613 dsb_sev(); 614 615 mmio_write_32(DBSC_DBPDRGA(phyno), regadd); 616 } 617 (void)val; 618 } 619 620 static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) 621 { 622 uint32_t ch; 623 uint32_t val; 624 uint32_t loop; 625 626 if ((prr_product != PRR_PRODUCT_M3N) && 627 (prr_product != PRR_PRODUCT_V3H)) { 628 foreach_vch(ch) { 629 mmio_write_32(DBSC_DBPDRGA(ch), regadd); 630 dsb_sev(); 631 } 632 633 foreach_vch(ch) { 634 mmio_write_32(DBSC_DBPDRGD(ch), regdata); 635 dsb_sev(); 636 } 637 638 for (loop = 0; loop < loop_max; loop++) { 639 val = mmio_read_32(DBSC_DBPDRGD(0)); 640 dsb_sev(); 641 } 642 (void)val; 643 } else { 644 foreach_vch(ch) { 645 reg_ddrphy_write(ch, regadd, regdata); 646 dsb_sev(); 647 } 648 } 649 } 650 651 static inline void ddrphy_regif_idle(void) 652 { 653 uint32_t val; 654 655 val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); 656 dsb_sev(); 657 (void)val; 658 } 659 660 /* DDRPHY register access (field modify) */ 661 static inline uint32_t ddr_regdef(uint32_t _regdef) 662 { 663 return p_ddr_regdef_tbl[_regdef]; 664 } 665 666 static inline uint32_t ddr_regdef_adr(uint32_t _regdef) 667 { 668 return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]); 669 } 670 671 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) 672 { 673 return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]); 674 } 675 676 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, 677 uint32_t val) 678 { 679 uint32_t adr; 680 uint32_t lsb; 681 uint32_t len; 682 uint32_t msk; 683 uint32_t tmp; 684 uint32_t regdef; 685 686 regdef = ddr_regdef(_regdef); 687 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; 688 len = DDR_REGDEF_LEN(regdef); 689 lsb = DDR_REGDEF_LSB(regdef); 690 if (len == 0x20) 691 msk = 0xffffffff; 692 else 693 msk = ((1U << len) - 1) << lsb; 694 695 tmp = reg_ddrphy_read(ch, adr); 696 tmp = (tmp & (~msk)) | ((val << lsb) & msk); 697 reg_ddrphy_write(ch, adr, tmp); 698 } 699 700 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) 701 { 702 uint32_t adr; 703 uint32_t lsb; 704 uint32_t len; 705 uint32_t msk; 706 uint32_t tmp; 707 uint32_t regdef; 708 709 regdef = ddr_regdef(_regdef); 710 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; 711 len = DDR_REGDEF_LEN(regdef); 712 lsb = DDR_REGDEF_LSB(regdef); 713 if (len == 0x20) 714 msk = 0xffffffff; 715 else 716 msk = ((1U << len) - 1); 717 718 tmp = reg_ddrphy_read(ch, adr); 719 tmp = (tmp >> lsb) & msk; 720 721 return tmp; 722 } 723 724 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) 725 { 726 ddr_setval_s(ch, 0, regdef, val); 727 } 728 729 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) 730 { 731 uint32_t ch; 732 733 foreach_vch(ch) 734 ddr_setval_s(ch, slice, regdef, val); 735 } 736 737 static void ddr_setval_ach(uint32_t regdef, uint32_t val) 738 { 739 ddr_setval_ach_s(0, regdef, val); 740 } 741 742 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) 743 { 744 uint32_t slice; 745 746 for (slice = 0; slice < SLICE_CNT; slice++) 747 ddr_setval_ach_s(slice, regdef, val); 748 } 749 750 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) 751 { 752 return ddr_getval_s(ch, 0, regdef); 753 } 754 755 static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p) 756 { 757 uint32_t ch; 758 759 foreach_vch(ch) 760 p[ch] = ddr_getval_s(ch, 0, regdef); 761 return p[0]; 762 } 763 764 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) 765 { 766 uint32_t ch, slice; 767 uint32_t *pp; 768 769 pp = p; 770 foreach_vch(ch) 771 for (slice = 0; slice < SLICE_CNT; slice++) 772 *pp++ = ddr_getval_s(ch, slice, regdef); 773 return p[0]; 774 } 775 776 /* handling functions for setteing ddrphy value table */ 777 static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) 778 { 779 uint32_t i; 780 781 for (i = 0; i < size; i++) { 782 to[i] = from[i]; 783 } 784 } 785 786 static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) 787 { 788 uint32_t adr; 789 uint32_t lsb; 790 uint32_t len; 791 uint32_t msk; 792 uint32_t tmp; 793 uint32_t adrmsk; 794 uint32_t regdef; 795 796 regdef = ddr_regdef(_regdef); 797 adr = DDR_REGDEF_ADR(regdef); 798 len = DDR_REGDEF_LEN(regdef); 799 lsb = DDR_REGDEF_LSB(regdef); 800 if (len == 0x20) 801 msk = 0xffffffff; 802 else 803 msk = ((1U << len) - 1) << lsb; 804 805 if (adr < 0x400) { 806 adrmsk = 0xff; 807 } else { 808 adrmsk = 0x7f; 809 } 810 811 tmp = tbl[adr & adrmsk]; 812 tmp = (tmp & (~msk)) | ((val << lsb) & msk); 813 tbl[adr & adrmsk] = tmp; 814 } 815 816 static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) 817 { 818 uint32_t adr; 819 uint32_t lsb; 820 uint32_t len; 821 uint32_t msk; 822 uint32_t tmp; 823 uint32_t adrmsk; 824 uint32_t regdef; 825 826 regdef = ddr_regdef(_regdef); 827 adr = DDR_REGDEF_ADR(regdef); 828 len = DDR_REGDEF_LEN(regdef); 829 lsb = DDR_REGDEF_LSB(regdef); 830 if (len == 0x20) 831 msk = 0xffffffff; 832 else 833 msk = ((1U << len) - 1); 834 835 if (adr < 0x400) { 836 adrmsk = 0xff; 837 } else { 838 adrmsk = 0x7f; 839 } 840 841 tmp = tbl[adr & adrmsk]; 842 tmp = (tmp >> lsb) & msk; 843 844 return tmp; 845 } 846 847 /* DDRPHY register access handling */ 848 static uint32_t ddrphy_regif_chk(void) 849 { 850 uint32_t tmp_ach[DRAM_CH_CNT]; 851 uint32_t ch; 852 uint32_t err; 853 uint32_t PI_VERSION_CODE; 854 855 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 856 (prr_product == PRR_PRODUCT_M3)) { 857 PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ 858 } else { 859 PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ 860 } 861 862 ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); 863 err = 0; 864 foreach_vch(ch) { 865 if (tmp_ach[ch] != PI_VERSION_CODE) 866 err = 1; 867 } 868 return err; 869 } 870 871 /* functions and parameters for timing setting */ 872 struct _jedec_spec1 { 873 uint16_t fx3; 874 uint8_t rlwodbi; 875 uint8_t rlwdbi; 876 uint8_t WL; 877 uint8_t nwr; 878 uint8_t nrtp; 879 uint8_t odtlon; 880 uint8_t MR1; 881 uint8_t MR2; 882 }; 883 884 #define JS1_USABLEC_SPEC_LO 2 885 #define JS1_USABLEC_SPEC_HI 5 886 #define JS1_FREQ_TBL_NUM 8 887 #define JS1_MR1(f) (0x04 | ((f) << 4)) 888 #define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) 889 const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { 890 /* 533.333Mbps */ 891 { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 }, 892 /* 1066.666Mbps */ 893 { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 }, 894 /* 1600.000Mbps */ 895 { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 }, 896 /* 2133.333Mbps */ 897 { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) }, 898 /* 2666.666Mbps */ 899 { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) }, 900 /* 3200.000Mbps */ 901 { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) }, 902 /* 3733.333Mbps */ 903 { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) }, 904 /* 4266.666Mbps */ 905 { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) } 906 }; 907 908 struct _jedec_spec2 { 909 uint16_t ps; 910 uint16_t cyc; 911 }; 912 913 #define js2_tsr 0 914 #define js2_txp 1 915 #define js2_trtp 2 916 #define js2_trcd 3 917 #define js2_trppb 4 918 #define js2_trpab 5 919 #define js2_tras 6 920 #define js2_twr 7 921 #define js2_twtr 8 922 #define js2_trrd 9 923 #define js2_tppd 10 924 #define js2_tfaw 11 925 #define js2_tdqsck 12 926 #define js2_tckehcmd 13 927 #define js2_tckelcmd 14 928 #define js2_tckelpd 15 929 #define js2_tmrr 16 930 #define js2_tmrw 17 931 #define js2_tmrd 18 932 #define js2_tzqcalns 19 933 #define js2_tzqlat 20 934 #define js2_tiedly 21 935 #define js2_tODTon_min 22 936 #define JS2_TBLCNT 23 937 938 #define js2_trcpb (JS2_TBLCNT) 939 #define js2_trcab (JS2_TBLCNT + 1) 940 #define js2_trfcab (JS2_TBLCNT + 2) 941 #define JS2_CNT (JS2_TBLCNT + 3) 942 943 #ifndef JS2_DERATE 944 #define JS2_DERATE 0 945 #endif 946 const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { 947 { 948 /*tSR */ {15000, 3}, 949 /*tXP */ {7500, 3}, 950 /*tRTP */ {7500, 8}, 951 /*tRCD */ {18000, 4}, 952 /*tRPpb */ {18000, 3}, 953 /*tRPab */ {21000, 3}, 954 /*tRAS */ {42000, 3}, 955 /*tWR */ {18000, 4}, 956 /*tWTR */ {10000, 8}, 957 /*tRRD */ {10000, 4}, 958 /*tPPD */ {0, 0}, 959 /*tFAW */ {40000, 0}, 960 /*tDQSCK*/ {3500, 0}, 961 /*tCKEHCMD*/ {7500, 3}, 962 /*tCKELCMD*/ {7500, 3}, 963 /*tCKELPD*/ {7500, 3}, 964 /*tMRR*/ {0, 8}, 965 /*tMRW*/ {10000, 10}, 966 /*tMRD*/ {14000, 10}, 967 /*tZQCALns*/ {1000 * 10, 0}, 968 /*tZQLAT*/ {30000, 10}, 969 /*tIEdly*/ {12500, 0}, 970 /*tODTon_min*/ {1500, 0} 971 }, { 972 /*tSR */ {15000, 3}, 973 /*tXP */ {7500, 3}, 974 /*tRTP */ {7500, 8}, 975 /*tRCD */ {19875, 4}, 976 /*tRPpb */ {19875, 3}, 977 /*tRPab */ {22875, 3}, 978 /*tRAS */ {43875, 3}, 979 /*tWR */ {18000, 4}, 980 /*tWTR */ {10000, 8}, 981 /*tRRD */ {11875, 4}, 982 /*tPPD */ {0, 0}, 983 /*tFAW */ {40000, 0}, 984 /*tDQSCK*/ {3600, 0}, 985 /*tCKEHCMD*/ {7500, 3}, 986 /*tCKELCMD*/ {7500, 3}, 987 /*tCKELPD*/ {7500, 3}, 988 /*tMRR*/ {0, 8}, 989 /*tMRW*/ {10000, 10}, 990 /*tMRD*/ {14000, 10}, 991 /*tZQCALns*/ {1000 * 10, 0}, 992 /*tZQLAT*/ {30000, 10}, 993 /*tIEdly*/ {12500, 0}, 994 /*tODTon_min*/ {1500, 0} 995 } 996 }; 997 998 const uint16_t jedec_spec2_trfc_ab[7] = { 999 /* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ 1000 130, 180, 180, 280, 280, 560, 560 1001 }; 1002 1003 static uint32_t js1_ind; 1004 static uint16_t js2[JS2_CNT]; 1005 static uint8_t RL; 1006 static uint8_t WL; 1007 1008 static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, 1009 uint16_t cyc) 1010 { 1011 uint32_t tmp; 1012 uint32_t div; 1013 1014 tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps; 1015 div = tmp / (200000 * _ddr_mbpsdiv); 1016 if (tmp != (div * 200000 * _ddr_mbpsdiv)) 1017 div = div + 1; 1018 1019 if (div > cyc) 1020 return (uint16_t)div; 1021 return cyc; 1022 } 1023 1024 static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, 1025 uint16_t *_js2) 1026 { 1027 int i; 1028 1029 for (i = 0; i < JS2_TBLCNT; i++) { 1030 _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv, 1031 1UL * jedec_spec2[JS2_DERATE][i].ps, 1032 jedec_spec2[JS2_DERATE][i].cyc); 1033 } 1034 1035 _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb]; 1036 _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab]; 1037 } 1038 1039 /* scaler for DELAY value */ 1040 static int16_t _f_scale_adj(int16_t ps) 1041 { 1042 int32_t tmp; 1043 /* 1044 * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; 1045 * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 1046 * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 1047 */ 1048 tmp = 1049 (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / 1050 (int32_t)ddr_mbpsdiv; 1051 tmp = (int32_t)tmp / (int32_t)15625; 1052 1053 return (int16_t)tmp; 1054 } 1055 1056 static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = { 1057 { 1058 _reg_PI_MR1_DATA_F0_0, 1059 _reg_PI_MR1_DATA_F0_1, 1060 _reg_PI_MR1_DATA_F0_2, 1061 _reg_PI_MR1_DATA_F0_3}, 1062 { 1063 _reg_PI_MR1_DATA_F1_0, 1064 _reg_PI_MR1_DATA_F1_1, 1065 _reg_PI_MR1_DATA_F1_2, 1066 _reg_PI_MR1_DATA_F1_3} 1067 }; 1068 1069 static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = { 1070 { 1071 _reg_PI_MR2_DATA_F0_0, 1072 _reg_PI_MR2_DATA_F0_1, 1073 _reg_PI_MR2_DATA_F0_2, 1074 _reg_PI_MR2_DATA_F0_3}, 1075 { 1076 _reg_PI_MR2_DATA_F1_0, 1077 _reg_PI_MR2_DATA_F1_1, 1078 _reg_PI_MR2_DATA_F1_2, 1079 _reg_PI_MR2_DATA_F1_3} 1080 }; 1081 1082 static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = { 1083 { 1084 _reg_PI_MR3_DATA_F0_0, 1085 _reg_PI_MR3_DATA_F0_1, 1086 _reg_PI_MR3_DATA_F0_2, 1087 _reg_PI_MR3_DATA_F0_3}, 1088 { 1089 _reg_PI_MR3_DATA_F1_0, 1090 _reg_PI_MR3_DATA_F1_1, 1091 _reg_PI_MR3_DATA_F1_2, 1092 _reg_PI_MR3_DATA_F1_3} 1093 }; 1094 1095 const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = { 1096 { 1097 _reg_PI_MR11_DATA_F0_0, 1098 _reg_PI_MR11_DATA_F0_1, 1099 _reg_PI_MR11_DATA_F0_2, 1100 _reg_PI_MR11_DATA_F0_3}, 1101 { 1102 _reg_PI_MR11_DATA_F1_0, 1103 _reg_PI_MR11_DATA_F1_1, 1104 _reg_PI_MR11_DATA_F1_2, 1105 _reg_PI_MR11_DATA_F1_3} 1106 }; 1107 1108 const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = { 1109 { 1110 _reg_PI_MR12_DATA_F0_0, 1111 _reg_PI_MR12_DATA_F0_1, 1112 _reg_PI_MR12_DATA_F0_2, 1113 _reg_PI_MR12_DATA_F0_3}, 1114 { 1115 _reg_PI_MR12_DATA_F1_0, 1116 _reg_PI_MR12_DATA_F1_1, 1117 _reg_PI_MR12_DATA_F1_2, 1118 _reg_PI_MR12_DATA_F1_3} 1119 }; 1120 1121 const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { 1122 { 1123 _reg_PI_MR14_DATA_F0_0, 1124 _reg_PI_MR14_DATA_F0_1, 1125 _reg_PI_MR14_DATA_F0_2, 1126 _reg_PI_MR14_DATA_F0_3}, 1127 { 1128 _reg_PI_MR14_DATA_F1_0, 1129 _reg_PI_MR14_DATA_F1_1, 1130 _reg_PI_MR14_DATA_F1_2, 1131 _reg_PI_MR14_DATA_F1_3} 1132 }; 1133 1134 /* 1135 * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) 1136 */ 1137 static void regif_pll_wa(void) 1138 { 1139 uint32_t ch; 1140 1141 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1142 // PLL setting for PHY : H3 Ver.1.x 1143 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), 1144 (0x0064U << 1145 ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); 1146 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 1147 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1148 _reg_PHY_PLL_CTRL)); 1149 1150 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), 1151 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1152 _reg_PHY_LP4_BOOT_PLL_CTRL)); 1153 1154 } else { 1155 /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ 1156 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), 1157 (0x5064U << 1158 ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); 1159 1160 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 1161 (ddrtbl_getval 1162 (_cnf_DDR_PHY_ADR_G_REGSET, 1163 _reg_PHY_PLL_CTRL_TOP) << 16) | 1164 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1165 _reg_PHY_PLL_CTRL)); 1166 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 1167 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1168 _reg_PHY_PLL_CTRL_CA)); 1169 1170 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), 1171 (ddrtbl_getval 1172 (_cnf_DDR_PHY_ADR_G_REGSET, 1173 _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | 1174 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1175 _reg_PHY_LP4_BOOT_PLL_CTRL)); 1176 reg_ddrphy_write_a(ddr_regdef_adr 1177 (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), 1178 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 1179 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 1180 )); 1181 } 1182 1183 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), 1184 _cnf_DDR_PHY_ADR_G_REGSET 1185 [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - 1186 DDR_PHY_ADR_G_REGSET_OFS]); 1187 1188 /* protect register interface */ 1189 ddrphy_regif_idle(); 1190 pll3_control(0); 1191 1192 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1193 /* non */ 1194 } else { 1195 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), 1196 (0x01U << 1197 ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); 1198 ddrphy_regif_idle(); 1199 } 1200 1201 /* init start */ 1202 /* dbdficnt0: 1203 * dfi_dram_clk_disable=1 1204 * dfi_frequency = 0 1205 * freq_ratio = 01 (2:1) 1206 * init_start =0 1207 */ 1208 foreach_vch(ch) 1209 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); 1210 dsb_sev(); 1211 1212 /* dbdficnt0: 1213 * dfi_dram_clk_disable=1 1214 * dfi_frequency = 0 1215 * freq_ratio = 01 (2:1) 1216 * init_start =1 1217 */ 1218 foreach_vch(ch) 1219 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); 1220 dsb_sev(); 1221 1222 foreach_ech(ch) 1223 if ((board_cnf->phyvalid) & BIT(ch)) 1224 while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) 1225 ; 1226 dsb_sev(); 1227 } 1228 1229 /* load table data into DDR registers */ 1230 static void ddrtbl_load(void) 1231 { 1232 uint32_t i; 1233 uint32_t slice; 1234 uint32_t csab; 1235 uint32_t adr; 1236 uint32_t data_l; 1237 uint32_t tmp[3]; 1238 uint16_t dataS; 1239 1240 /* TIMING REGISTERS */ 1241 /* search jedec_spec1 index */ 1242 for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { 1243 if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) 1244 break; 1245 } 1246 if (i > JS1_USABLEC_SPEC_HI) 1247 js1_ind = JS1_USABLEC_SPEC_HI; 1248 else 1249 js1_ind = i; 1250 1251 if (board_cnf->dbi_en) 1252 RL = js1[js1_ind].rlwdbi; 1253 else 1254 RL = js1[js1_ind].rlwodbi; 1255 1256 WL = js1[js1_ind].WL; 1257 1258 /* calculate jedec_spec2 */ 1259 _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); 1260 1261 /* PREPARE TBL */ 1262 if (prr_product == PRR_PRODUCT_H3) { 1263 if (prr_cut <= PRR_PRODUCT_11) { 1264 /* H3 Ver.1.x */ 1265 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1266 DDR_PHY_SLICE_REGSET_H3, 1267 DDR_PHY_SLICE_REGSET_NUM_H3); 1268 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1269 DDR_PHY_ADR_V_REGSET_H3, 1270 DDR_PHY_ADR_V_REGSET_NUM_H3); 1271 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, 1272 DDR_PHY_ADR_I_REGSET_H3, 1273 DDR_PHY_ADR_I_REGSET_NUM_H3); 1274 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1275 DDR_PHY_ADR_G_REGSET_H3, 1276 DDR_PHY_ADR_G_REGSET_NUM_H3); 1277 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3, 1278 DDR_PI_REGSET_NUM_H3); 1279 1280 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3; 1281 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3; 1282 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3; 1283 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3; 1284 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3; 1285 DDR_PHY_SLICE_REGSET_SIZE = 1286 DDR_PHY_SLICE_REGSET_SIZE_H3; 1287 DDR_PHY_ADR_V_REGSET_SIZE = 1288 DDR_PHY_ADR_V_REGSET_SIZE_H3; 1289 DDR_PHY_ADR_I_REGSET_SIZE = 1290 DDR_PHY_ADR_I_REGSET_SIZE_H3; 1291 DDR_PHY_ADR_G_REGSET_SIZE = 1292 DDR_PHY_ADR_G_REGSET_SIZE_H3; 1293 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3; 1294 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3; 1295 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3; 1296 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3; 1297 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3; 1298 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3; 1299 1300 DDR_PHY_ADR_I_NUM = 1; 1301 } else { 1302 /* H3 Ver.2.0 or later */ 1303 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1304 DDR_PHY_SLICE_REGSET_H3VER2, 1305 DDR_PHY_SLICE_REGSET_NUM_H3VER2); 1306 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1307 DDR_PHY_ADR_V_REGSET_H3VER2, 1308 DDR_PHY_ADR_V_REGSET_NUM_H3VER2); 1309 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1310 DDR_PHY_ADR_G_REGSET_H3VER2, 1311 DDR_PHY_ADR_G_REGSET_NUM_H3VER2); 1312 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2, 1313 DDR_PI_REGSET_NUM_H3VER2); 1314 1315 DDR_PHY_SLICE_REGSET_OFS = 1316 DDR_PHY_SLICE_REGSET_OFS_H3VER2; 1317 DDR_PHY_ADR_V_REGSET_OFS = 1318 DDR_PHY_ADR_V_REGSET_OFS_H3VER2; 1319 DDR_PHY_ADR_G_REGSET_OFS = 1320 DDR_PHY_ADR_G_REGSET_OFS_H3VER2; 1321 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2; 1322 DDR_PHY_SLICE_REGSET_SIZE = 1323 DDR_PHY_SLICE_REGSET_SIZE_H3VER2; 1324 DDR_PHY_ADR_V_REGSET_SIZE = 1325 DDR_PHY_ADR_V_REGSET_SIZE_H3VER2; 1326 DDR_PHY_ADR_G_REGSET_SIZE = 1327 DDR_PHY_ADR_G_REGSET_SIZE_H3VER2; 1328 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2; 1329 DDR_PHY_SLICE_REGSET_NUM = 1330 DDR_PHY_SLICE_REGSET_NUM_H3VER2; 1331 DDR_PHY_ADR_V_REGSET_NUM = 1332 DDR_PHY_ADR_V_REGSET_NUM_H3VER2; 1333 DDR_PHY_ADR_G_REGSET_NUM = 1334 DDR_PHY_ADR_G_REGSET_NUM_H3VER2; 1335 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2; 1336 1337 DDR_PHY_ADR_I_NUM = 0; 1338 } 1339 } else if (prr_product == PRR_PRODUCT_M3) { 1340 /* M3-W */ 1341 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1342 DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); 1343 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, 1344 DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3); 1345 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, 1346 DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3); 1347 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, 1348 DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3); 1349 _tblcopy(_cnf_DDR_PI_REGSET, 1350 DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3); 1351 1352 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3; 1353 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3; 1354 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3; 1355 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3; 1356 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3; 1357 DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3; 1358 DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3; 1359 DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3; 1360 DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3; 1361 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3; 1362 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3; 1363 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3; 1364 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3; 1365 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3; 1366 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3; 1367 1368 DDR_PHY_ADR_I_NUM = 2; 1369 } else { 1370 /* M3-N/V3H */ 1371 _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, 1372 DDR_PHY_SLICE_REGSET_M3N, 1373 DDR_PHY_SLICE_REGSET_NUM_M3N); 1374 _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N, 1375 DDR_PHY_ADR_V_REGSET_NUM_M3N); 1376 _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N, 1377 DDR_PHY_ADR_I_REGSET_NUM_M3N); 1378 _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N, 1379 DDR_PHY_ADR_G_REGSET_NUM_M3N); 1380 _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N, 1381 DDR_PI_REGSET_NUM_M3N); 1382 1383 DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N; 1384 DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N; 1385 DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N; 1386 DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N; 1387 DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N; 1388 DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N; 1389 DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N; 1390 DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N; 1391 DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N; 1392 DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N; 1393 DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N; 1394 DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N; 1395 DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N; 1396 DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N; 1397 DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N; 1398 1399 DDR_PHY_ADR_I_NUM = 2; 1400 } 1401 1402 /* PLL CODE CHANGE */ 1403 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { 1404 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 1405 0x1142); 1406 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1407 _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); 1408 } 1409 1410 /* on fly gate adjust */ 1411 if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { 1412 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1413 _reg_ON_FLY_GATE_ADJUST_EN, 0x00); 1414 } 1415 1416 /* Adjust PI parameters */ 1417 #ifdef _def_LPDDR4_ODT 1418 for (i = 0; i < 2; i++) { 1419 for (csab = 0; csab < CSAB_CNT; csab++) { 1420 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1421 reg_pi_mr11_data_fx_csx[i][csab], 1422 _def_LPDDR4_ODT); 1423 } 1424 } 1425 #endif /* _def_LPDDR4_ODT */ 1426 1427 #ifdef _def_LPDDR4_VREFCA 1428 for (i = 0; i < 2; i++) { 1429 for (csab = 0; csab < CSAB_CNT; csab++) { 1430 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1431 reg_pi_mr12_data_fx_csx[i][csab], 1432 _def_LPDDR4_VREFCA); 1433 } 1434 } 1435 #endif /* _def_LPDDR4_VREFCA */ 1436 if ((prr_product == PRR_PRODUCT_M3N) || 1437 (prr_product == PRR_PRODUCT_V3H)) { 1438 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; 1439 if (js2[js2_tiedly] > (RL)) 1440 js2[js2_tiedly] = RL; 1441 } else if ((prr_product == PRR_PRODUCT_H3) && 1442 (prr_cut > PRR_PRODUCT_11)) { 1443 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; 1444 } else if ((prr_product == PRR_PRODUCT_H3) && 1445 (prr_cut <= PRR_PRODUCT_11)) { 1446 js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); 1447 } 1448 1449 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 1450 (prr_product == PRR_PRODUCT_M3N) || 1451 (prr_product == PRR_PRODUCT_V3H)) { 1452 if ((js2[js2_tiedly]) >= 0x1e) 1453 dataS = 0x1e; 1454 else 1455 dataS = js2[js2_tiedly]; 1456 } else { 1457 if ((js2[js2_tiedly]) >= 0x0e) 1458 dataS = 0x0e; 1459 else 1460 dataS = js2[js2_tiedly]; 1461 } 1462 1463 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); 1464 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, 1465 (dataS - 2)); 1466 if ((prr_product == PRR_PRODUCT_M3N) || 1467 (prr_product == PRR_PRODUCT_V3H)) { 1468 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1469 _reg_PHY_RDDATA_EN_OE_DLY, dataS - 2); 1470 } 1471 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); 1472 1473 if (ddrtbl_getval 1474 (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { 1475 data_l = WL - 1; 1476 } else { 1477 data_l = WL; 1478 } 1479 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2); 1480 ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l); 1481 1482 if (board_cnf->dbi_en) { 1483 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 1484 0x01); 1485 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1486 _reg_PHY_WDQLVL_DATADM_MASK, 0x000); 1487 } else { 1488 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 1489 0x00); 1490 ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, 1491 _reg_PHY_WDQLVL_DATADM_MASK, 0x100); 1492 } 1493 1494 tmp[0] = js1[js1_ind].MR1; 1495 tmp[1] = js1[js1_ind].MR2; 1496 data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); 1497 if (board_cnf->dbi_en) 1498 tmp[2] = data_l | 0xc0; 1499 else 1500 tmp[2] = data_l & (~0xc0); 1501 1502 for (i = 0; i < 2; i++) { 1503 for (csab = 0; csab < CSAB_CNT; csab++) { 1504 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1505 reg_pi_mr1_data_fx_csx[i][csab], tmp[0]); 1506 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1507 reg_pi_mr2_data_fx_csx[i][csab], tmp[1]); 1508 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1509 reg_pi_mr3_data_fx_csx[i][csab], tmp[2]); 1510 } 1511 } 1512 1513 /* DDRPHY INT START */ 1514 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1515 /* non */ 1516 } else { 1517 regif_pll_wa(); 1518 dbwait_loop(5); 1519 } 1520 1521 /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ 1522 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1523 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 1524 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); 1525 1526 /* SET DATA SLICE TABLE */ 1527 for (slice = 0; slice < SLICE_CNT; slice++) { 1528 adr = 1529 DDR_PHY_SLICE_REGSET_OFS + 1530 DDR_PHY_SLICE_REGSET_SIZE * slice; 1531 for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) { 1532 reg_ddrphy_write_a(adr + i, 1533 _cnf_DDR_PHY_SLICE_REGSET[i]); 1534 } 1535 } 1536 1537 /* SET ADR SLICE TABLE */ 1538 adr = DDR_PHY_ADR_V_REGSET_OFS; 1539 for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { 1540 reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); 1541 } 1542 1543 if (((prr_product == PRR_PRODUCT_M3) || 1544 (prr_product == PRR_PRODUCT_M3N)) && 1545 ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) 1546 != 0x00)) { 1547 adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; 1548 for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { 1549 reg_ddrphy_write_a(adr + i, 1550 _cnf_DDR_PHY_ADR_V_REGSET[i]); 1551 } 1552 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1553 _reg_PHY_ADR_DISABLE, 0x02); 1554 DDR_PHY_ADR_I_NUM -= 1; 1555 ddr_phycaslice = 1; 1556 1557 #ifndef _def_LPDDR4_ODT 1558 for (i = 0; i < 2; i++) { 1559 for (csab = 0; csab < CSAB_CNT; csab++) { 1560 ddrtbl_setval(_cnf_DDR_PI_REGSET, 1561 reg_pi_mr11_data_fx_csx[i][csab], 1562 0x66); 1563 } 1564 } 1565 #endif/* _def_LPDDR4_ODT */ 1566 } else { 1567 ddr_phycaslice = 0; 1568 } 1569 1570 if (DDR_PHY_ADR_I_NUM > 0) { 1571 for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) { 1572 adr = 1573 DDR_PHY_ADR_I_REGSET_OFS + 1574 DDR_PHY_ADR_I_REGSET_SIZE * slice; 1575 for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) { 1576 reg_ddrphy_write_a(adr + i, 1577 _cnf_DDR_PHY_ADR_I_REGSET 1578 [i]); 1579 } 1580 } 1581 } 1582 1583 /* SET ADRCTRL SLICE TABLE */ 1584 adr = DDR_PHY_ADR_G_REGSET_OFS; 1585 for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { 1586 reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); 1587 } 1588 1589 /* SET PI REGISTERS */ 1590 adr = DDR_PI_REGSET_OFS; 1591 for (i = 0; i < DDR_PI_REGSET_NUM; i++) { 1592 reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); 1593 } 1594 } 1595 1596 /* CONFIGURE DDR REGISTERS */ 1597 static void ddr_config_sub(void) 1598 { 1599 uint32_t i; 1600 uint32_t ch, slice; 1601 uint32_t data_l; 1602 uint32_t tmp; 1603 uint8_t high_byte[SLICE_CNT]; 1604 const uint32_t _par_CALVL_DEVICE_MAP = 1; 1605 1606 foreach_vch(ch) { 1607 /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ 1608 for (slice = 0; slice < SLICE_CNT; slice++) { 1609 high_byte[slice] = 1610 (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; 1611 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, 1612 board_cnf->ch[ch].dq_swap[slice]); 1613 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, 1614 board_cnf->ch[ch].dm_swap[slice]); 1615 if (high_byte[slice]) { 1616 /* HIGHER 16 BYTE */ 1617 ddr_setval_s(ch, slice, 1618 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1619 0x00); 1620 } else { 1621 /* LOWER 16 BYTE */ 1622 ddr_setval_s(ch, slice, 1623 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1624 0x01); 1625 } 1626 } 1627 1628 /* BOARD SETTINGS (CA,ADDR_SEL) */ 1629 data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | 1630 0x00888888; 1631 1632 /* --- ADR_CALVL_SWIZZLE --- */ 1633 if (prr_product == PRR_PRODUCT_M3) { 1634 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); 1635 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 1636 0x00000000); 1637 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); 1638 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 1639 0x00000000); 1640 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 1641 _par_CALVL_DEVICE_MAP); 1642 } else { 1643 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); 1644 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); 1645 ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, 1646 _par_CALVL_DEVICE_MAP); 1647 } 1648 1649 /* --- ADR_ADDR_SEL --- */ 1650 if ((prr_product == PRR_PRODUCT_H3) && 1651 (prr_cut > PRR_PRODUCT_11)) { 1652 data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1653 } else { 1654 data_l = 0; 1655 tmp = board_cnf->ch[ch].ca_swap; 1656 for (i = 0; i < 6; i++) { 1657 data_l |= ((tmp & 0x0f) << (i * 5)); 1658 tmp = tmp >> 4; 1659 } 1660 } 1661 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l); 1662 if (ddr_phycaslice == 1) { 1663 /* ----------- adr slice2 swap ----------- */ 1664 tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40); 1665 data_l = (tmp & 0x00ffffff) | 0x00888888; 1666 1667 /* --- ADR_CALVL_SWIZZLE --- */ 1668 if (prr_product == PRR_PRODUCT_M3) { 1669 ddr_setval_s(ch, 2, 1670 _reg_PHY_ADR_CALVL_SWIZZLE0_0, 1671 data_l); 1672 ddr_setval_s(ch, 2, 1673 _reg_PHY_ADR_CALVL_SWIZZLE1_0, 1674 0x00000000); 1675 ddr_setval_s(ch, 2, 1676 _reg_PHY_ADR_CALVL_SWIZZLE0_1, 1677 data_l); 1678 ddr_setval_s(ch, 2, 1679 _reg_PHY_ADR_CALVL_SWIZZLE1_1, 1680 0x00000000); 1681 ddr_setval_s(ch, 2, 1682 _reg_PHY_ADR_CALVL_DEVICE_MAP, 1683 _par_CALVL_DEVICE_MAP); 1684 } else { 1685 ddr_setval_s(ch, 2, 1686 _reg_PHY_ADR_CALVL_SWIZZLE0, 1687 data_l); 1688 ddr_setval_s(ch, 2, 1689 _reg_PHY_ADR_CALVL_SWIZZLE1, 1690 0x00000000); 1691 ddr_setval_s(ch, 2, 1692 _reg_PHY_CALVL_DEVICE_MAP, 1693 _par_CALVL_DEVICE_MAP); 1694 } 1695 1696 /* --- ADR_ADDR_SEL --- */ 1697 data_l = 0; 1698 for (i = 0; i < 6; i++) { 1699 data_l |= ((tmp & 0x0f) << (i * 5)); 1700 tmp = tmp >> 4; 1701 } 1702 1703 ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); 1704 } 1705 1706 /* BOARD SETTINGS (BYTE_ORDER_SEL) */ 1707 if (prr_product == PRR_PRODUCT_M3) { 1708 /* --- DATA_BYTE_SWAP --- */ 1709 data_l = 0; 1710 tmp = board_cnf->ch[ch].dqs_swap; 1711 for (i = 0; i < 4; i++) { 1712 data_l |= ((tmp & 0x03) << (i * 2)); 1713 tmp = tmp >> 4; 1714 } 1715 } else { 1716 /* --- DATA_BYTE_SWAP --- */ 1717 data_l = board_cnf->ch[ch].dqs_swap; 1718 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); 1719 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, 1720 (data_l) & 0x0f); 1721 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, 1722 (data_l >> 4 * 1) & 0x0f); 1723 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, 1724 (data_l >> 4 * 2) & 0x0f); 1725 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, 1726 (data_l >> 4 * 3) & 0x0f); 1727 1728 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); 1729 } 1730 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l); 1731 } 1732 } 1733 1734 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) 1735 { 1736 uint32_t slice; 1737 uint32_t tmp; 1738 uint32_t tgt; 1739 1740 if (ddr_csn / 2) { 1741 tgt = 3; 1742 } else { 1743 tgt = 1; 1744 } 1745 1746 for (slice = 0; slice < SLICE_CNT; slice++) { 1747 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 1748 if (tgt == tmp) 1749 break; 1750 } 1751 tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1752 if (slice % 2) 1753 tmp |= 0x00888888; 1754 *p_swz = tmp; 1755 } 1756 1757 static void ddr_config_sub_h3v1x(void) 1758 { 1759 uint32_t ch, slice; 1760 uint32_t data_l; 1761 uint32_t tmp; 1762 uint8_t high_byte[SLICE_CNT]; 1763 uint32_t ca_swizzle; 1764 uint32_t ca; 1765 uint32_t csmap; 1766 uint32_t o_inv; 1767 uint32_t inv; 1768 uint32_t bit_soc; 1769 uint32_t bit_mem; 1770 uint32_t j; 1771 1772 const uint8_t o_mr15 = 0x55; 1773 const uint8_t o_mr20 = 0x55; 1774 const uint16_t o_mr32_mr40 = 0x5a3c; 1775 1776 foreach_vch(ch) { 1777 /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ 1778 csmap = 0; 1779 for (slice = 0; slice < SLICE_CNT; slice++) { 1780 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 1781 0x0f; 1782 high_byte[slice] = tmp % 2; 1783 if (tmp == 1 && (slice >= 2)) 1784 csmap |= 0x05; 1785 if (tmp == 3 && (slice >= 2)) 1786 csmap |= 0x50; 1787 ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, 1788 board_cnf->ch[ch].dq_swap[slice]); 1789 if (high_byte[slice]) { 1790 /* HIGHER 16 BYTE */ 1791 ddr_setval_s(ch, slice, 1792 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1793 0x00); 1794 } else { 1795 /* LOWER 16 BYTE */ 1796 ddr_setval_s(ch, slice, 1797 _reg_PHY_CALVL_VREF_DRIVING_SLICE, 1798 0x01); 1799 } 1800 } 1801 /* BOARD SETTINGS (CA,ADDR_SEL) */ 1802 ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; 1803 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); 1804 ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); 1805 1806 get_ca_swizzle(ch, 0, &ca_swizzle); 1807 1808 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle); 1809 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); 1810 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000); 1811 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); 1812 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01); 1813 1814 for (slice = 0; slice < SLICE_CNT; slice++) { 1815 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM, 1816 0x01); 1817 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START, 1818 0x08); 1819 1820 if (high_byte[slice]) 1821 o_inv = o_mr20; 1822 else 1823 o_inv = o_mr15; 1824 1825 tmp = board_cnf->ch[ch].dq_swap[slice]; 1826 inv = 0; 1827 j = 0; 1828 for (bit_soc = 0; bit_soc < 8; bit_soc++) { 1829 bit_mem = (tmp >> (4 * bit_soc)) & 0x0f; 1830 j |= (1U << bit_mem); 1831 if (o_inv & (1U << bit_mem)) 1832 inv |= (1U << bit_soc); 1833 } 1834 data_l = o_mr32_mr40; 1835 if (!high_byte[slice]) 1836 data_l |= (inv << 24); 1837 if (high_byte[slice]) 1838 data_l |= (inv << 16); 1839 ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, 1840 data_l); 1841 } 1842 } 1843 } 1844 1845 static void ddr_config(void) 1846 { 1847 int32_t i; 1848 uint32_t ch, slice; 1849 uint32_t data_l; 1850 uint32_t tmp; 1851 int8_t _adj; 1852 int16_t adj; 1853 uint32_t dq; 1854 union { 1855 uint32_t ui32[4]; 1856 uint8_t ui8[16]; 1857 } patt; 1858 uint16_t patm; 1859 1860 /* configure ddrphy registers */ 1861 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 1862 ddr_config_sub_h3v1x(); 1863 } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ 1864 ddr_config_sub(); 1865 } 1866 1867 /* WDQ_USER_PATT */ 1868 foreach_vch(ch) { 1869 for (slice = 0; slice < SLICE_CNT; slice++) { 1870 patm = 0; 1871 for (i = 0; i < 16; i++) { 1872 tmp = board_cnf->ch[ch].wdqlvl_patt[i]; 1873 patt.ui8[i] = tmp & 0xff; 1874 if (tmp & 0x100) 1875 patm |= (1U << i); 1876 } 1877 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, 1878 patt.ui32[0]); 1879 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, 1880 patt.ui32[1]); 1881 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, 1882 patt.ui32[2]); 1883 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, 1884 patt.ui32[3]); 1885 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); 1886 } 1887 } 1888 1889 /* CACS DLY */ 1890 data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); 1891 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1892 0x00U); 1893 foreach_vch(ch) { 1894 for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) { 1895 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 1896 ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, 1897 _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 1898 data_l + adj); 1899 reg_ddrphy_write(ch, 1900 ddr_regdef_adr 1901 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), 1902 _cnf_DDR_PHY_ADR_V_REGSET 1903 [ddr_regdef_adr 1904 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1905 DDR_PHY_ADR_V_REGSET_OFS]); 1906 } 1907 1908 for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); 1909 i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { 1910 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 1911 ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, 1912 _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 1913 data_l + adj); 1914 reg_ddrphy_write(ch, 1915 ddr_regdef_adr 1916 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), 1917 _cnf_DDR_PHY_ADR_G_REGSET 1918 [ddr_regdef_adr 1919 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1920 DDR_PHY_ADR_G_REGSET_OFS]); 1921 } 1922 1923 if (ddr_phycaslice == 1) { 1924 for (i = 0; i < 6; i++) { 1925 adj = _f_scale_adj 1926 (board_cnf->ch[ch].cacs_adj 1927 [i + 1928 _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); 1929 ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, 1930 _reg_PHY_CLK_CACS_SLAVE_DELAY_X 1931 [i], 1932 data_l + adj); 1933 reg_ddrphy_write(ch, 1934 ddr_regdef_adr 1935 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 1936 0x0100, 1937 _cnf_DDR_PHY_ADR_V_REGSET 1938 [ddr_regdef_adr 1939 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - 1940 DDR_PHY_ADR_V_REGSET_OFS]); 1941 } 1942 } 1943 } 1944 1945 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 1946 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 1947 1948 /* WDQDM DLY */ 1949 data_l = board_cnf->dqdm_dly_w; 1950 foreach_vch(ch) { 1951 for (slice = 0; slice < SLICE_CNT; slice++) { 1952 for (i = 0; i <= 8; i++) { 1953 dq = slice * 8 + i; 1954 if (i == 8) 1955 _adj = board_cnf->ch[ch].dm_adj_w[slice]; 1956 else 1957 _adj = board_cnf->ch[ch].dq_adj_w[dq]; 1958 adj = _f_scale_adj(_adj); 1959 ddr_setval_s(ch, slice, 1960 _reg_PHY_CLK_WRX_SLAVE_DELAY[i], 1961 data_l + adj); 1962 } 1963 } 1964 } 1965 1966 /* RDQDM DLY */ 1967 data_l = board_cnf->dqdm_dly_r; 1968 foreach_vch(ch) { 1969 for (slice = 0; slice < SLICE_CNT; slice++) { 1970 for (i = 0; i <= 8; i++) { 1971 dq = slice * 8 + i; 1972 if (i == 8) 1973 _adj = board_cnf->ch[ch].dm_adj_r[slice]; 1974 else 1975 _adj = board_cnf->ch[ch].dq_adj_r[dq]; 1976 adj = _f_scale_adj(_adj); 1977 ddr_setval_s(ch, slice, 1978 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY 1979 [i], data_l + adj); 1980 ddr_setval_s(ch, slice, 1981 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 1982 [i], data_l + adj); 1983 } 1984 } 1985 } 1986 } 1987 1988 /* DBSC register setting functions */ 1989 static void dbsc_regset_pre(void) 1990 { 1991 uint32_t ch, csab; 1992 uint32_t data_l; 1993 1994 /* PRIMARY SETTINGS */ 1995 /* LPDDR4, BL=16, DFI interface */ 1996 mmio_write_32(DBSC_DBKIND, 0x0000000a); 1997 mmio_write_32(DBSC_DBBL, 0x00000002); 1998 mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); 1999 2000 /* FREQRATIO=2 */ 2001 mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); 2002 2003 /* Chanel map (H3 Ver.1.x) */ 2004 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) 2005 mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); 2006 2007 /* DRAM SIZE REGISTER: 2008 * set all ranks as density=0(4Gb) for PHY initialization 2009 */ 2010 foreach_vch(ch) { 2011 for (csab = 0; csab < 4; csab++) { 2012 mmio_write_32(DBSC_DBMEMCONF(ch, csab), 2013 DBMEMCONF_REGD(0)); 2014 } 2015 } 2016 2017 if (prr_product == PRR_PRODUCT_M3) { 2018 data_l = 0xe4e4e4e4; 2019 foreach_ech(ch) { 2020 if ((ddr_phyvalid & (1U << ch))) 2021 data_l = (data_l & (~(0x000000FF << (ch * 8)))) 2022 | (((board_cnf->ch[ch].dqs_swap & 0x0003) 2023 | ((board_cnf->ch[ch].dqs_swap & 0x0030) 2024 >> 2) 2025 | ((board_cnf->ch[ch].dqs_swap & 0x0300) 2026 >> 4) 2027 | ((board_cnf->ch[ch].dqs_swap & 0x3000) 2028 >> 6)) << (ch * 8)); 2029 } 2030 mmio_write_32(DBSC_DBBSWAP, data_l); 2031 } 2032 } 2033 2034 static void dbsc_regset(void) 2035 { 2036 int32_t i; 2037 uint32_t ch; 2038 uint32_t data_l; 2039 uint32_t data_l2; 2040 uint32_t tmp[4]; 2041 2042 /* RFC */ 2043 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && 2044 (max_density == 0)) { 2045 js2[js2_trfcab] = 2046 _f_scale(ddr_mbps, ddr_mbpsdiv, 2047 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); 2048 } else { 2049 js2[js2_trfcab] = 2050 _f_scale(ddr_mbps, ddr_mbpsdiv, 2051 1UL * jedec_spec2_trfc_ab[max_density] * 2052 1000, 0); 2053 } 2054 2055 /* DBTR0.CL : RL */ 2056 mmio_write_32(DBSC_DBTR(0), RL); 2057 2058 /* DBTR1.CWL : WL */ 2059 mmio_write_32(DBSC_DBTR(1), WL); 2060 2061 /* DBTR2.AL : 0 */ 2062 mmio_write_32(DBSC_DBTR(2), 0); 2063 2064 /* DBTR3.TRCD: tRCD */ 2065 mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); 2066 2067 /* DBTR4.TRPA,TRP: tRPab,tRPpb */ 2068 mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); 2069 2070 /* DBTR5.TRC : use tRCpb */ 2071 mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); 2072 2073 /* DBTR6.TRAS : tRAS */ 2074 mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); 2075 2076 /* DBTR7.TRRD : tRRD */ 2077 mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); 2078 2079 /* DBTR8.TFAW : tFAW */ 2080 mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); 2081 2082 /* DBTR9.TRDPR : tRTP */ 2083 mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); 2084 2085 /* DBTR10.TWR : nWR */ 2086 mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr); 2087 2088 /* 2089 * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff - 2090 * odtlon + tDQSCK - tODTon,min + 2091 * PCB delay (out+in) + tPHY_ODToff 2092 */ 2093 mmio_write_32(DBSC_DBTR(11), 2094 RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon + 2095 js2[js2_tdqsck] - js2[js2_tODTon_min] + 2096 _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0)); 2097 2098 /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ 2099 data_l = WL + 1 + (16 / 2) + js2[js2_twtr]; 2100 mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l); 2101 2102 /* DBTR13.TRFCAB : tRFCab */ 2103 mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab])); 2104 2105 /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ 2106 mmio_write_32(DBSC_DBTR(14), 2107 (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd])); 2108 2109 /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ 2110 mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd])); 2111 2112 /* DBTR16 */ 2113 /* WDQL : tphy_wrlat + tphy_wrdata */ 2114 tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); 2115 /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 2116 * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 2117 */ 2118 tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); 2119 /* DQL : tphy_rdlat + trdata_en */ 2120 /* it is not important for dbsc */ 2121 tmp[2] = RL + 16; 2122 /* DQIENLTNCY : trdata_en */ 2123 tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; 2124 mmio_write_32(DBSC_DBTR(16), 2125 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2126 2127 /* DBTR24 */ 2128 /* WRCSLAT = WRLAT -5 */ 2129 tmp[0] -= 5; 2130 /* WRCSGAP = 5 */ 2131 tmp[1] = 5; 2132 /* RDCSLAT = RDLAT_ADJ +2 */ 2133 if (prr_product == PRR_PRODUCT_M3) { 2134 tmp[2] = tmp[3]; 2135 } else { 2136 tmp[2] = tmp[3] + 2; 2137 } 2138 /* RDCSGAP = 6 */ 2139 if (prr_product == PRR_PRODUCT_M3) { 2140 tmp[3] = 4; 2141 } else { 2142 tmp[3] = 6; 2143 } 2144 mmio_write_32(DBSC_DBTR(24), 2145 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2146 2147 /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ 2148 mmio_write_32(DBSC_DBTR(17), 2149 (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16)); 2150 2151 /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ 2152 mmio_write_32(DBSC_DBTR(18), 0); 2153 2154 /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ 2155 mmio_write_32(DBSC_DBTR(19), 0); 2156 2157 /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ 2158 data_l = js2[js2_trfcab] + js2[js2_tckehcmd]; 2159 mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l); 2160 2161 /* DBTR21.TCCD */ 2162 /* DBTR23.TCCD */ 2163 /* H3 Ver.1.0 cannot use TBTR23 feature */ 2164 if (ddr_tccd == 8 && 2165 !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10)) 2166 ) { 2167 data_l = 8; 2168 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2169 mmio_write_32(DBSC_DBTR(23), 0x00000002); 2170 } else if (ddr_tccd <= 11) { 2171 data_l = 11; 2172 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2173 mmio_write_32(DBSC_DBTR(23), 0x00000000); 2174 } else { 2175 data_l = ddr_tccd; 2176 mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); 2177 mmio_write_32(DBSC_DBTR(23), 0x00000000); 2178 } 2179 2180 /* DBTR22.ZQLAT : */ 2181 data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */ 2182 data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20); 2183 mmio_write_32(DBSC_DBTR(22), data_l); 2184 2185 /* DBTR25 : do not use in LPDDR4 */ 2186 mmio_write_32(DBSC_DBTR(25), 0); 2187 2188 /* DBRNK : */ 2189 /* 2190 * DBSC_DBRNK2 rkrr 2191 * DBSC_DBRNK3 rkrw 2192 * DBSC_DBRNK4 rkwr 2193 * DBSC_DBRNK5 rkww 2194 */ 2195 #define _par_DBRNK_VAL (0x7007) 2196 2197 for (i = 0; i < 4; i++) { 2198 data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; 2199 if ((prr_product == PRR_PRODUCT_H3) && 2200 (prr_cut > PRR_PRODUCT_11) && (i == 0)) { 2201 data_l += 1; 2202 } 2203 data_l2 = 0; 2204 foreach_vch(ch) { 2205 data_l2 = data_l2 | (data_l << (4 * ch)); 2206 } 2207 mmio_write_32(DBSC_DBRNK(2 + i), data_l2); 2208 } 2209 mmio_write_32(DBSC_DBADJ0, 0x00000000); 2210 2211 /* timing registers for Scheduler */ 2212 /* SCFCTST0 */ 2213 /* SCFCTST0 ACT-ACT */ 2214 tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; 2215 /* SCFCTST0 RDA-ACT */ 2216 tmp[2] = 2217 1UL * ((16 / 2) + js2[js2_trtp] - 8 + 2218 js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps; 2219 /* SCFCTST0 WRA-ACT */ 2220 tmp[1] = 2221 1UL * (WL + 1 + (16 / 2) + 2222 js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps; 2223 /* SCFCTST0 PRE-ACT */ 2224 tmp[0] = 1UL * js2[js2_trppb]; 2225 mmio_write_32(DBSC_SCFCTST0, 2226 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2227 2228 /* SCFCTST1 */ 2229 /* SCFCTST1 RD-WR */ 2230 tmp[3] = 2231 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / 2232 ddr_mbps; 2233 /* SCFCTST1 WR-RD */ 2234 tmp[2] = 2235 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / 2236 ddr_mbps; 2237 /* SCFCTST1 ACT-RD/WR */ 2238 tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps; 2239 /* SCFCTST1 ASYNCOFS */ 2240 tmp[0] = 12; 2241 mmio_write_32(DBSC_SCFCTST1, 2242 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); 2243 2244 /* DBSCHRW1 */ 2245 /* DBSCHRW1 SCTRFCAB */ 2246 tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps; 2247 data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) 2248 + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2249 + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; 2250 if (tmp[0] < data_l) 2251 tmp[0] = data_l; 2252 2253 if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { 2254 mmio_write_32(DBSC_DBSCHRW1, tmp[0] 2255 + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2256 * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / 2257 ddr_mbps - 3); 2258 } else { 2259 mmio_write_32(DBSC_DBSCHRW1, tmp[0] 2260 + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) 2261 * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / 2262 ddr_mbps); 2263 } 2264 2265 /* QOS and CAM */ 2266 #ifdef ddr_qos_init_setting /* only for non qos_init */ 2267 /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ 2268 mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); 2269 /*0(fillunit),8(dirtymax),4(dirtymin) */ 2270 mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); 2271 /*stop_tolerance */ 2272 mmio_write_32(DBSC_DBSCHRW0, 0x22421111); 2273 /*rd-wr/wr-rd toggle priority */ 2274 mmio_write_32(DBSC_SCFCTST2, 0x012F1123); 2275 mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); 2276 mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); 2277 2278 /* QoS Settings */ 2279 mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); 2280 mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); 2281 mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); 2282 mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); 2283 mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); 2284 mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); 2285 mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); 2286 mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); 2287 mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); 2288 mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); 2289 mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); 2290 mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); 2291 mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); 2292 mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); 2293 mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); 2294 mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); 2295 mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); 2296 mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); 2297 mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); 2298 mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); 2299 mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); 2300 mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); 2301 mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); 2302 mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); 2303 mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); 2304 mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); 2305 mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); 2306 mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); 2307 2308 mmio_write_32(QOSCTRL_RAEN, 0x00000001U); 2309 #endif /* ddr_qos_init_setting */ 2310 /* H3 Ver.1.1 need to set monitor function */ 2311 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { 2312 mmio_write_32(DBSC_DBMONCONF4, 0x00700000); 2313 } 2314 2315 if (prr_product == PRR_PRODUCT_H3) { 2316 if (prr_cut == PRR_PRODUCT_10) { 2317 /* resrdis, simple mode, sc off */ 2318 mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); 2319 } else if (prr_cut == PRR_PRODUCT_11) { 2320 /* resrdis, simple mode */ 2321 mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); 2322 } else if (prr_cut < PRR_PRODUCT_30) { 2323 /* H3 Ver.2.0 */ 2324 /* resrdis */ 2325 mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); 2326 } else { /* H3 Ver.3.0(include H3N) */ 2327 /* exprespque */ 2328 mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); 2329 } 2330 } else { /* M3-W/M3-N/V3H */ 2331 /* resrdis */ 2332 mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); 2333 } 2334 } 2335 2336 static void dbsc_regset_post(void) 2337 { 2338 uint32_t ch, cs; 2339 uint32_t data_l; 2340 uint32_t slice, rdlat_max, rdlat_min; 2341 2342 rdlat_max = 0; 2343 rdlat_min = 0xffff; 2344 foreach_vch(ch) { 2345 for (cs = 0; cs < CS_CNT; cs++) { 2346 if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { 2347 for (slice = 0; slice < SLICE_CNT; slice++) { 2348 ddr_setval_s(ch, slice, 2349 _reg_PHY_PER_CS_TRAINING_INDEX, 2350 cs); 2351 data_l = ddr_getval_s(ch, slice, 2352 _reg_PHY_RDDQS_LATENCY_ADJUST); 2353 if (data_l > rdlat_max) 2354 rdlat_max = data_l; 2355 if (data_l < rdlat_min) 2356 rdlat_min = data_l; 2357 } 2358 } 2359 } 2360 } 2361 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) { 2362 #if RCAR_DRAM_SPLIT == 2 2363 if (board_cnf->phyvalid == 0x05) { 2364 mmio_write_32(DBSC_DBTR(24), 2365 (rdlat_max << 24) + (rdlat_min << 16) + 2366 mmio_read_32(DBSC_DBTR(24))); 2367 } else { 2368 mmio_write_32(DBSC_DBTR(24), 2369 ((rdlat_max * 2 - rdlat_min + 4) << 24) + 2370 ((rdlat_min + 2) << 16) + 2371 mmio_read_32(DBSC_DBTR(24))); 2372 } 2373 #else /*RCAR_DRAM_SPLIT == 2 */ 2374 mmio_write_32(DBSC_DBTR(24), 2375 ((rdlat_max * 2 - rdlat_min + 4) << 24) + 2376 ((rdlat_min + 2) << 16) + 2377 mmio_read_32(DBSC_DBTR(24))); 2378 #endif /*RCAR_DRAM_SPLIT == 2 */ 2379 } else { 2380 mmio_write_32(DBSC_DBTR(24), 2381 ((rdlat_max + 2) << 24) + 2382 ((rdlat_max + 2) << 16) + 2383 mmio_read_32(DBSC_DBTR(24))); 2384 } 2385 2386 /* set ddr density information */ 2387 foreach_ech(ch) { 2388 for (cs = 0; cs < CS_CNT; cs++) { 2389 if (ddr_density[ch][cs] == 0xff) { 2390 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); 2391 } else { 2392 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 2393 DBMEMCONF_REGD(ddr_density[ch] 2394 [cs])); 2395 } 2396 } 2397 mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); 2398 mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); 2399 } 2400 2401 mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); 2402 2403 /*set DBI */ 2404 if (board_cnf->dbi_en) 2405 mmio_write_32(DBSC_DBDBICNT, 0x00000003); 2406 2407 /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ 2408 if ((((prr_product == PRR_PRODUCT_H3) && 2409 (prr_cut > PRR_PRODUCT_11)) || 2410 (prr_product == PRR_PRODUCT_M3N) || 2411 (prr_product == PRR_PRODUCT_V3H)) && 2412 board_cnf->dbi_en) 2413 reg_ddrphy_write_a(0x00001010, 0x01000000); 2414 2415 /*set REFCYCLE */ 2416 data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; 2417 mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff)); 2418 mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); 2419 2420 #if RCAR_REWT_TRAINING != 0 2421 /* Periodic-WriteDQ Training seeting */ 2422 if (((prr_product == PRR_PRODUCT_H3) && 2423 (prr_cut <= PRR_PRODUCT_11)) || 2424 ((prr_product == PRR_PRODUCT_M3) && 2425 (prr_cut == PRR_PRODUCT_10))) { 2426 /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ 2427 } else { 2428 /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ 2429 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); 2430 2431 ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); 2432 ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); 2433 ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); 2434 ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); 2435 2436 ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, 2437 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2438 _reg_PI_WDQLVL_CS_MAP)); 2439 ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); 2440 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); 2441 ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); 2442 ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); 2443 ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); 2444 ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); 2445 2446 if (prr_product == PRR_PRODUCT_M3) { 2447 ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); 2448 } else { 2449 ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); 2450 } 2451 ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); 2452 2453 /* DFI_PHYMSTR_ACK , WTmode setting */ 2454 /* DFI_PHYMSTR_ACK: WTmode =b'01 */ 2455 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); 2456 } 2457 #endif /* RCAR_REWT_TRAINING */ 2458 /* periodic dram zqcal enable */ 2459 mmio_write_32(DBSC_DBCALCNF, 0x01000010); 2460 2461 /* periodic phy ctrl update enable */ 2462 if (((prr_product == PRR_PRODUCT_H3) && 2463 (prr_cut <= PRR_PRODUCT_11)) || 2464 ((prr_product == PRR_PRODUCT_M3) && 2465 (prr_cut < PRR_PRODUCT_30))) { 2466 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 2467 } else { 2468 #if RCAR_DRAM_SPLIT == 2 2469 if ((prr_product == PRR_PRODUCT_H3) && 2470 (board_cnf->phyvalid == 0x05)) 2471 mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); 2472 else 2473 mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); 2474 #else /* RCAR_DRAM_SPLIT == 2 */ 2475 mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); 2476 #endif /* RCAR_DRAM_SPLIT == 2 */ 2477 } 2478 2479 #ifdef DDR_BACKUPMODE 2480 /* SRX */ 2481 if (ddr_backup == DRAM_BOOT_STATUS_WARM) { 2482 #ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */ 2483 NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n"); 2484 send_dbcmd(0x0A040001); 2485 if (Prr_Product == PRR_PRODUCT_H3) 2486 send_dbcmd(0x0A140001); 2487 #else /* DDR_BACKUPMODE_HALF */ /* for All channels */ 2488 send_dbcmd(0x0A840001); 2489 #endif /* DDR_BACKUPMODE_HALF */ 2490 } 2491 #endif /* DDR_BACKUPMODE */ 2492 2493 /* set Auto Refresh */ 2494 mmio_write_32(DBSC_DBRFEN, 0x00000001); 2495 2496 #if RCAR_REWT_TRAINING != 0 2497 /* Periodic WriteDQ Traning */ 2498 if (((prr_product == PRR_PRODUCT_H3) && 2499 (prr_cut <= PRR_PRODUCT_11)) || 2500 ((prr_product == PRR_PRODUCT_M3) && 2501 (prr_cut == PRR_PRODUCT_10))) { 2502 /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ 2503 } else { 2504 /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ 2505 ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); 2506 } 2507 #endif /* RCAR_REWT_TRAINING */ 2508 2509 /* dram access enable */ 2510 mmio_write_32(DBSC_DBACEN, 0x00000001); 2511 2512 MSG_LF(__func__ "(done)"); 2513 } 2514 2515 /* DFI_INIT_START */ 2516 static uint32_t dfi_init_start(void) 2517 { 2518 uint32_t ch; 2519 uint32_t phytrainingok; 2520 uint32_t retry; 2521 uint32_t data_l; 2522 const uint32_t RETRY_MAX = 0x10000; 2523 2524 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2525 /* PLL3 Disable */ 2526 /* protect register interface */ 2527 ddrphy_regif_idle(); 2528 2529 pll3_control(0); 2530 2531 /* init start */ 2532 /* dbdficnt0: 2533 * dfi_dram_clk_disable=1 2534 * dfi_frequency = 0 2535 * freq_ratio = 01 (2:1) 2536 * init_start =0 2537 */ 2538 foreach_vch(ch) 2539 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); 2540 dsb_sev(); 2541 2542 /* dbdficnt0: 2543 * dfi_dram_clk_disable=1 2544 * dfi_frequency = 0 2545 * freq_ratio = 01 (2:1) 2546 * init_start =1 2547 */ 2548 foreach_vch(ch) 2549 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); 2550 dsb_sev(); 2551 2552 } else { 2553 ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); 2554 dsb_sev(); 2555 ddrphy_regif_idle(); 2556 } 2557 2558 /* dll_rst negate */ 2559 foreach_vch(ch) 2560 mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); 2561 dsb_sev(); 2562 2563 /* wait init_complete */ 2564 phytrainingok = 0; 2565 retry = 0; 2566 while (retry++ < RETRY_MAX) { 2567 foreach_vch(ch) { 2568 data_l = mmio_read_32(DBSC_DBDFISTAT(ch)); 2569 if (data_l & 0x00000001) 2570 phytrainingok |= (1U << ch); 2571 } 2572 dsb_sev(); 2573 if (phytrainingok == ddr_phyvalid) 2574 break; 2575 if (retry % 256 == 0) 2576 ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); 2577 } 2578 2579 /* all ch ok? */ 2580 if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) 2581 return 0xff; 2582 2583 /* dbdficnt0: 2584 * dfi_dram_clk_disable=0 2585 * dfi_frequency = 0 2586 * freq_ratio = 01 (2:1) 2587 * init_start =0 2588 */ 2589 foreach_vch(ch) 2590 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); 2591 dsb_sev(); 2592 2593 return 0; 2594 } 2595 2596 /* drivablity setting : CMOS MODE ON/OFF */ 2597 static void change_lpddr4_en(uint32_t mode) 2598 { 2599 uint32_t ch; 2600 uint32_t i; 2601 uint32_t data_l; 2602 const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { 2603 _reg_PHY_PAD_ADDR_DRIVE, 2604 _reg_PHY_PAD_CLK_DRIVE, 2605 _reg_PHY_PAD_CS_DRIVE 2606 }; 2607 2608 foreach_vch(ch) { 2609 for (i = 0; i < 3; i++) { 2610 data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); 2611 if (mode) { 2612 data_l |= (1U << 14); 2613 } else { 2614 data_l &= ~(1U << 14); 2615 } 2616 ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l); 2617 } 2618 } 2619 } 2620 2621 /* drivablity setting */ 2622 static uint32_t set_term_code(void) 2623 { 2624 int32_t i; 2625 uint32_t ch, index; 2626 uint32_t data_l; 2627 uint32_t chip_id[2]; 2628 uint32_t term_code; 2629 uint32_t override; 2630 uint32_t pvtr; 2631 uint32_t pvtp; 2632 uint32_t pvtn; 2633 2634 term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 2635 _reg_PHY_PAD_DATA_TERM); 2636 override = 0; 2637 for (i = 0; i < 2; i++) 2638 chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); 2639 2640 index = 0; 2641 while (1) { 2642 if (termcode_by_sample[index][0] == 0xffffffff) { 2643 break; 2644 } 2645 if ((termcode_by_sample[index][0] == chip_id[0]) && 2646 (termcode_by_sample[index][1] == chip_id[1])) { 2647 term_code = termcode_by_sample[index][2]; 2648 override = 1; 2649 break; 2650 } 2651 index++; 2652 } 2653 2654 if (override) { 2655 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { 2656 data_l = 2657 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, 2658 _reg_PHY_PAD_TERM_X[index]); 2659 data_l = (data_l & 0xfffe0000) | term_code; 2660 ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); 2661 } 2662 } else if ((prr_product == PRR_PRODUCT_M3) && 2663 (prr_cut == PRR_PRODUCT_10)) { 2664 /* non */ 2665 } else { 2666 ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], 2667 (ddrtbl_getval 2668 (_cnf_DDR_PHY_ADR_G_REGSET, 2669 _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); 2670 ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); 2671 ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); 2672 foreach_vch(ch) { 2673 do { 2674 data_l = 2675 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); 2676 } while (!(data_l & 0x00800000)); 2677 } 2678 if ((prr_product == PRR_PRODUCT_H3) && 2679 (prr_cut <= PRR_PRODUCT_11)) { 2680 foreach_vch(ch) { 2681 data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); 2682 pvtr = (data_l >> 12) & 0x1f; 2683 pvtr += 8; 2684 if (pvtr > 0x1f) 2685 pvtr = 0x1f; 2686 data_l = 2687 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); 2688 pvtn = (data_l >> 6) & 0x03f; 2689 pvtp = (data_l >> 0) & 0x03f; 2690 2691 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; 2692 index++) { 2693 data_l = 2694 ddrtbl_getval 2695 (_cnf_DDR_PHY_ADR_G_REGSET, 2696 _reg_PHY_PAD_TERM_X[index]); 2697 data_l = (data_l & 0xfffe0000) 2698 | (pvtr << 12) 2699 | (pvtn << 6) 2700 | (pvtp); 2701 ddr_setval(ch, 2702 _reg_PHY_PAD_TERM_X[index], 2703 data_l); 2704 } 2705 } 2706 } else { 2707 /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ 2708 foreach_vch(ch) { 2709 for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; 2710 index++) { 2711 data_l = 2712 ddr_getval(ch, 2713 _reg_PHY_PAD_TERM_X 2714 [index]); 2715 ddr_setval(ch, 2716 _reg_PHY_PAD_TERM_X[index], 2717 (data_l & 0xFFFE0FFF) | 2718 0x00015000); 2719 } 2720 } 2721 } 2722 } 2723 2724 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2725 /* non */ 2726 } else { 2727 ddr_padcal_tcompensate_getinit(override); 2728 } 2729 2730 return 0; 2731 } 2732 2733 /* DDR mode register setting */ 2734 static void ddr_register_set(void) 2735 { 2736 int32_t fspwp; 2737 uint32_t tmp; 2738 2739 for (fspwp = 1; fspwp >= 0; fspwp--) { 2740 /*MR13, fspwp */ 2741 send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); 2742 2743 tmp = 2744 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2745 reg_pi_mr1_data_fx_csx[fspwp][0]); 2746 send_dbcmd(0x0e840100 | tmp); 2747 2748 tmp = 2749 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2750 reg_pi_mr2_data_fx_csx[fspwp][0]); 2751 send_dbcmd(0x0e840200 | tmp); 2752 2753 tmp = 2754 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2755 reg_pi_mr3_data_fx_csx[fspwp][0]); 2756 send_dbcmd(0x0e840300 | tmp); 2757 2758 tmp = 2759 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2760 reg_pi_mr11_data_fx_csx[fspwp][0]); 2761 send_dbcmd(0x0e840b00 | tmp); 2762 2763 tmp = 2764 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2765 reg_pi_mr12_data_fx_csx[fspwp][0]); 2766 send_dbcmd(0x0e840c00 | tmp); 2767 2768 tmp = 2769 ddrtbl_getval(_cnf_DDR_PI_REGSET, 2770 reg_pi_mr14_data_fx_csx[fspwp][0]); 2771 send_dbcmd(0x0e840e00 | tmp); 2772 /* MR22 */ 2773 send_dbcmd(0x0e841616); 2774 2775 /* ZQCAL start */ 2776 send_dbcmd(0x0d84004F); 2777 2778 /* ZQLAT */ 2779 send_dbcmd(0x0d840051); 2780 } 2781 2782 /* MR13, fspwp */ 2783 send_dbcmd(0x0e840d08); 2784 } 2785 2786 /* Training handshake functions */ 2787 static inline uint32_t wait_freqchgreq(uint32_t assert) 2788 { 2789 uint32_t data_l; 2790 uint32_t count; 2791 uint32_t ch; 2792 2793 count = 100000; 2794 2795 /* H3 Ver.1.x cannot see frqchg_req */ 2796 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2797 return 0; 2798 } 2799 2800 if (assert) { 2801 do { 2802 data_l = 1; 2803 foreach_vch(ch) { 2804 data_l &= mmio_read_32(DBSC_DBPDSTAT(ch)); 2805 } 2806 count = count - 1; 2807 } while (((data_l & 0x01) != 0x01) & (count != 0)); 2808 } else { 2809 do { 2810 data_l = 0; 2811 foreach_vch(ch) { 2812 data_l |= mmio_read_32(DBSC_DBPDSTAT(ch)); 2813 } 2814 count = count - 1; 2815 } while (((data_l & 0x01) != 0x00) & (count != 0)); 2816 } 2817 2818 return (count == 0); 2819 } 2820 2821 static inline void set_freqchgack(uint32_t assert) 2822 { 2823 uint32_t ch; 2824 uint32_t data_l; 2825 2826 if (assert) 2827 data_l = 0x0CF20000; 2828 else 2829 data_l = 0x00000000; 2830 2831 foreach_vch(ch) 2832 mmio_write_32(DBSC_DBPDCNT2(ch), data_l); 2833 } 2834 2835 static inline void set_dfifrequency(uint32_t freq) 2836 { 2837 uint32_t ch; 2838 2839 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 2840 foreach_vch(ch) 2841 mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); 2842 } else { 2843 foreach_vch(ch) { 2844 mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, 2845 (freq << 24)); 2846 } 2847 } 2848 dsb_sev(); 2849 } 2850 2851 static uint32_t pll3_freq(uint32_t on) 2852 { 2853 uint32_t timeout; 2854 2855 timeout = wait_freqchgreq(1); 2856 2857 if (timeout) { 2858 return 1; 2859 } 2860 2861 pll3_control(on); 2862 set_dfifrequency(on); 2863 2864 set_freqchgack(1); 2865 timeout = wait_freqchgreq(0); 2866 set_freqchgack(0); 2867 2868 if (timeout) { 2869 FATAL_MSG("BL2: Time out[2]\n"); 2870 return 1; 2871 } 2872 return 0; 2873 } 2874 2875 /* update dly */ 2876 static void update_dly(void) 2877 { 2878 ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); 2879 ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); 2880 } 2881 2882 /* training by pi */ 2883 static uint32_t pi_training_go(void) 2884 { 2885 uint32_t flag; 2886 uint32_t data_l; 2887 uint32_t retry; 2888 const uint32_t RETRY_MAX = 4096 * 16; 2889 uint32_t ch; 2890 2891 uint32_t mst_ch; 2892 uint32_t cur_frq; 2893 uint32_t complete; 2894 uint32_t frqchg_req; 2895 2896 /* pi_start */ 2897 ddr_setval_ach(_reg_PI_START, 0x01); 2898 foreach_vch(ch) 2899 ddr_getval(ch, _reg_PI_INT_STATUS); 2900 2901 /* set dfi_phymstr_ack = 1 */ 2902 mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); 2903 dsb_sev(); 2904 2905 /* wait pi_int_status[0] */ 2906 mst_ch = 0; 2907 flag = 0; 2908 complete = 0; 2909 cur_frq = 0; 2910 retry = RETRY_MAX; 2911 do { 2912 frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; 2913 2914 /* H3 Ver.1.x cannot see frqchg_req */ 2915 if ((prr_product == PRR_PRODUCT_H3) && 2916 (prr_cut <= PRR_PRODUCT_11)) { 2917 if ((retry % 4096) == 1) { 2918 frqchg_req = 1; 2919 } else { 2920 frqchg_req = 0; 2921 } 2922 } 2923 2924 if (frqchg_req) { 2925 if (cur_frq) { 2926 /* Low frequency */ 2927 flag = pll3_freq(0); 2928 cur_frq = 0; 2929 } else { 2930 /* High frequency */ 2931 flag = pll3_freq(1); 2932 cur_frq = 1; 2933 } 2934 if (flag) 2935 break; 2936 } else { 2937 if (cur_frq) { 2938 foreach_vch(ch) { 2939 if (complete & (1U << ch)) 2940 continue; 2941 data_l = 2942 ddr_getval(ch, _reg_PI_INT_STATUS); 2943 if (data_l & 0x01) { 2944 complete |= (1U << ch); 2945 } 2946 } 2947 if (complete == ddr_phyvalid) 2948 break; 2949 } 2950 } 2951 } while (--retry); 2952 foreach_vch(ch) { 2953 /* dummy read */ 2954 data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); 2955 data_l = ddr_getval(ch, _reg_PI_INT_STATUS); 2956 ddr_setval(ch, _reg_PI_INT_ACK, data_l); 2957 } 2958 if (ddrphy_regif_chk()) { 2959 return 0xfd; 2960 } 2961 return complete; 2962 } 2963 2964 /* Initialize DDR */ 2965 static uint32_t init_ddr(void) 2966 { 2967 int32_t i; 2968 uint32_t data_l; 2969 uint32_t phytrainingok; 2970 uint32_t ch, slice; 2971 uint32_t err; 2972 int16_t adj; 2973 2974 MSG_LF(__func__ ":0\n"); 2975 2976 #ifdef DDR_BACKUPMODE 2977 rcar_dram_get_boot_status(&ddr_backup); 2978 #endif 2979 2980 /* unlock phy */ 2981 /* Unlock DDRPHY register(AGAIN) */ 2982 foreach_vch(ch) 2983 mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); 2984 dsb_sev(); 2985 2986 if ((((prr_product == PRR_PRODUCT_H3) && 2987 (prr_cut > PRR_PRODUCT_11)) || 2988 (prr_product == PRR_PRODUCT_M3N) || 2989 (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en) 2990 reg_ddrphy_write_a(0x00001010, 0x01000001); 2991 else 2992 reg_ddrphy_write_a(0x00001010, 0x00000001); 2993 /* DBSC register pre-setting */ 2994 dbsc_regset_pre(); 2995 2996 /* load ddrphy registers */ 2997 2998 ddrtbl_load(); 2999 3000 /* configure ddrphy registers */ 3001 ddr_config(); 3002 3003 /* dfi_reset assert */ 3004 foreach_vch(ch) 3005 mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); 3006 dsb_sev(); 3007 3008 /* dbsc register set */ 3009 dbsc_regset(); 3010 MSG_LF(__func__ ":1\n"); 3011 3012 /* dfi_reset negate */ 3013 foreach_vch(ch) 3014 mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); 3015 dsb_sev(); 3016 3017 /* dfi_init_start (start ddrphy) */ 3018 err = dfi_init_start(); 3019 if (err) { 3020 return INITDRAM_ERR_I; 3021 } 3022 MSG_LF(__func__ ":2\n"); 3023 3024 /* ddr backupmode end */ 3025 #ifdef DDR_BACKUPMODE 3026 if (ddr_backup) { 3027 NOTICE("BL2: [WARM_BOOT]\n"); 3028 } else { 3029 NOTICE("BL2: [COLD_BOOT]\n"); 3030 } 3031 err = rcar_dram_update_boot_status(ddr_backup); 3032 if (err) { 3033 NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); 3034 return INITDRAM_ERR_I; 3035 } 3036 #endif 3037 MSG_LF(__func__ ":3\n"); 3038 3039 /* override term code after dfi_init_complete */ 3040 err = set_term_code(); 3041 if (err) { 3042 return INITDRAM_ERR_I; 3043 } 3044 MSG_LF(__func__ ":4\n"); 3045 3046 /* rx offset calibration */ 3047 if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || 3048 (prr_product == PRR_PRODUCT_V3H)) { 3049 err = rx_offset_cal_hw(); 3050 } else { 3051 err = rx_offset_cal(); 3052 } 3053 if (err) 3054 return INITDRAM_ERR_O; 3055 MSG_LF(__func__ ":5\n"); 3056 3057 /* Dummy PDE */ 3058 send_dbcmd(0x08840000); 3059 3060 /* PDX */ 3061 send_dbcmd(0x08840001); 3062 3063 /* check register i/f is alive */ 3064 err = ddrphy_regif_chk(); 3065 if (err) { 3066 return INITDRAM_ERR_O; 3067 } 3068 MSG_LF(__func__ ":6\n"); 3069 3070 /* phy initialize end */ 3071 3072 /* setup DDR mode registers */ 3073 /* CMOS MODE */ 3074 change_lpddr4_en(0); 3075 3076 /* MRS */ 3077 ddr_register_set(); 3078 3079 /* Thermal sensor setting */ 3080 /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ 3081 data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; 3082 mmio_write_32(THS1_THCTR, data_l); 3083 3084 /* LPDDR4 MODE */ 3085 change_lpddr4_en(1); 3086 3087 MSG_LF(__func__ ":7\n"); 3088 3089 /* mask CS_MAP if RANKx is not found */ 3090 foreach_vch(ch) { 3091 data_l = ddr_getval(ch, _reg_PI_CS_MAP); 3092 if (!(ch_have_this_cs[1] & (1U << ch))) 3093 data_l = data_l & 0x05; 3094 ddr_setval(ch, _reg_PI_CS_MAP, data_l); 3095 } 3096 3097 /* exec pi_training */ 3098 reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 3099 BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); 3100 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); 3101 3102 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3103 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); 3104 } else { 3105 foreach_vch(ch) { 3106 for (slice = 0; slice < SLICE_CNT; slice++) { 3107 ddr_setval_s(ch, slice, 3108 _reg_PHY_PER_CS_TRAINING_EN, 3109 ((ch_have_this_cs[1]) >> ch) 3110 & 0x01); 3111 } 3112 } 3113 } 3114 3115 phytrainingok = pi_training_go(); 3116 3117 if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { 3118 return INITDRAM_ERR_T | phytrainingok; 3119 } 3120 3121 MSG_LF(__func__ ":8\n"); 3122 3123 /* CACS DLY ADJUST */ 3124 data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); 3125 foreach_vch(ch) { 3126 for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { 3127 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); 3128 ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], 3129 data_l + adj); 3130 } 3131 3132 if (ddr_phycaslice == 1) { 3133 for (i = 0; i < 6; i++) { 3134 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj 3135 [i + 3136 _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); 3137 ddr_setval_s(ch, 2, 3138 _reg_PHY_CLK_CACS_SLAVE_DELAY_X 3139 [i], 3140 data_l + adj 3141 ); 3142 } 3143 } 3144 } 3145 3146 update_dly(); 3147 MSG_LF(__func__ ":9\n"); 3148 3149 /* H3 fix rd latency to avoid bug in elasitic buffer */ 3150 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) 3151 adjust_rddqs_latency(); 3152 3153 /* Adjust Write path latency */ 3154 if (ddrtbl_getval 3155 (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) 3156 adjust_wpath_latency(); 3157 3158 /* RDQLVL Training */ 3159 if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) 3160 ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); 3161 3162 err = rdqdm_man(); 3163 3164 if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) 3165 ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); 3166 3167 if (err) { 3168 return INITDRAM_ERR_T; 3169 } 3170 update_dly(); 3171 MSG_LF(__func__ ":10\n"); 3172 3173 /* WDQLVL Training */ 3174 err = wdqdm_man(); 3175 if (err) { 3176 return INITDRAM_ERR_T; 3177 } 3178 update_dly(); 3179 MSG_LF(__func__ ":11\n"); 3180 3181 /* training complete, setup DBSC */ 3182 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 3183 (prr_product == PRR_PRODUCT_M3N) || 3184 (prr_product == PRR_PRODUCT_V3H)) { 3185 ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); 3186 ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); 3187 } 3188 3189 dbsc_regset_post(); 3190 MSG_LF(__func__ ":12\n"); 3191 3192 return phytrainingok; 3193 } 3194 3195 /* SW LEVELING COMMON */ 3196 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) 3197 { 3198 uint32_t ch; 3199 uint32_t data_l; 3200 uint32_t retry; 3201 uint32_t waiting; 3202 uint32_t err; 3203 3204 const uint32_t RETRY_MAX = 0x1000; 3205 3206 err = 0; 3207 /* set EXIT -> OP_DONE is cleared */ 3208 ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); 3209 3210 /* kick */ 3211 foreach_vch(ch) { 3212 if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) { 3213 ddr_setval(ch, reg_cs, ddr_csn); 3214 ddr_setval(ch, reg_kick, 0x01); 3215 } 3216 } 3217 foreach_vch(ch) { 3218 /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */ 3219 ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); 3220 } 3221 waiting = ch_have_this_cs[ddr_csn % 2]; 3222 dsb_sev(); 3223 retry = RETRY_MAX; 3224 do { 3225 foreach_vch(ch) { 3226 if (!(waiting & (1U << ch))) 3227 continue; 3228 data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); 3229 if (data_l & 0x01) 3230 waiting &= ~(1U << ch); 3231 } 3232 retry--; 3233 } while (waiting && (retry > 0)); 3234 if (retry == 0) { 3235 err = 1; 3236 } 3237 3238 dsb_sev(); 3239 /* set EXIT -> OP_DONE is cleared */ 3240 ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); 3241 dsb_sev(); 3242 3243 return err; 3244 } 3245 3246 /* WDQ TRAINING */ 3247 #ifndef DDR_FAST_INIT 3248 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) 3249 { 3250 int32_t i, k; 3251 uint32_t cs, slice; 3252 uint32_t data_l; 3253 3254 /* clr of training results buffer */ 3255 cs = ddr_csn % 2; 3256 data_l = board_cnf->dqdm_dly_w; 3257 for (slice = 0; slice < SLICE_CNT; slice++) { 3258 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3259 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3260 continue; 3261 3262 for (i = 0; i <= 8; i++) { 3263 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) 3264 wdqdm_dly[ch][cs][slice][i] = 3265 wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; 3266 else 3267 wdqdm_dly[ch][cs][slice][i] = data_l; 3268 wdqdm_le[ch][cs][slice][i] = 0; 3269 wdqdm_te[ch][cs][slice][i] = 0; 3270 } 3271 wdqdm_st[ch][cs][slice] = 0; 3272 wdqdm_win[ch][cs][slice] = 0; 3273 } 3274 } 3275 3276 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) 3277 { 3278 int32_t i, k; 3279 uint32_t cs, slice; 3280 uint32_t data_l; 3281 uint32_t err; 3282 const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; 3283 3284 int32_t min_win; 3285 int32_t win; 3286 int8_t _adj; 3287 int16_t adj; 3288 uint32_t dq; 3289 3290 /* analysis of training results */ 3291 err = 0; 3292 for (slice = 0; slice < SLICE_CNT; slice += 1) { 3293 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3294 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3295 continue; 3296 3297 cs = ddr_csn % 2; 3298 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); 3299 for (i = 0; i < 9; i++) { 3300 dq = slice * 8 + i; 3301 if (i == 8) 3302 _adj = board_cnf->ch[ch].dm_adj_w[slice]; 3303 else 3304 _adj = board_cnf->ch[ch].dq_adj_w[dq]; 3305 adj = _f_scale_adj(_adj); 3306 3307 data_l = 3308 ddr_getval_s(ch, slice, 3309 _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; 3310 ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], 3311 data_l); 3312 wdqdm_dly[ch][cs][slice][i] = data_l; 3313 } 3314 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); 3315 data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); 3316 wdqdm_st[ch][cs][slice] = data_l; 3317 min_win = INT_LEAST32_MAX; 3318 for (i = 0; i <= 8; i++) { 3319 ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, 3320 i); 3321 3322 data_l = 3323 ddr_getval_s(ch, slice, 3324 _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); 3325 wdqdm_te[ch][cs][slice][i] = data_l; 3326 data_l = 3327 ddr_getval_s(ch, slice, 3328 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); 3329 wdqdm_le[ch][cs][slice][i] = data_l; 3330 win = 3331 (int32_t)wdqdm_te[ch][cs][slice][i] - 3332 wdqdm_le[ch][cs][slice][i]; 3333 if (min_win > win) 3334 min_win = win; 3335 if (data_l >= _par_WDQLVL_RETRY_THRES) 3336 err = 2; 3337 } 3338 wdqdm_win[ch][cs][slice] = min_win; 3339 if ((prr_product == PRR_PRODUCT_H3) && 3340 (prr_cut <= PRR_PRODUCT_11)) { 3341 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 3342 0x01); 3343 } else { 3344 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 3345 ((ch_have_this_cs[1]) >> ch) & 0x01); 3346 } 3347 } 3348 return err; 3349 } 3350 #endif/* DDR_FAST_INIT */ 3351 3352 static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) 3353 { 3354 uint32_t i; 3355 uint32_t ch, slice; 3356 uint32_t tgt_cs, src_cs; 3357 uint32_t tmp_r; 3358 3359 /* copy of training results */ 3360 foreach_vch(ch) { 3361 for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { 3362 for (slice = 0; slice < SLICE_CNT; slice++) { 3363 ddr_setval_s(ch, slice, 3364 _reg_PHY_PER_CS_TRAINING_INDEX, 3365 tgt_cs); 3366 src_cs = ddr_csn % 2; 3367 if (!(ch_have_this_cs[1] & (1U << ch))) 3368 src_cs = 0; 3369 for (i = 0; i <= 4; i += 4) { 3370 if (restore) 3371 tmp_r = 3372 rdqdm_dly[ch][tgt_cs][slice] 3373 [i]; 3374 else 3375 tmp_r = 3376 rdqdm_dly[ch][src_cs][slice] 3377 [i]; 3378 3379 ddr_setval_s(ch, slice, 3380 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY 3381 [i], tmp_r); 3382 } 3383 } 3384 } 3385 } 3386 } 3387 3388 static uint32_t wdqdm_man1(void) 3389 { 3390 int32_t k; 3391 uint32_t ch, cs, slice; 3392 uint32_t ddr_csn; 3393 uint32_t data_l; 3394 uint32_t err; 3395 uint32_t high_dq[DRAM_CH_CNT]; 3396 uint32_t mr14_csab0_bak[DRAM_CH_CNT]; 3397 #ifndef DDR_FAST_INIT 3398 uint32_t err_flg; 3399 #endif/* DDR_FAST_INIT */ 3400 3401 /* manual execution of training */ 3402 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3403 foreach_vch(ch) { 3404 high_dq[ch] = 0; 3405 for (slice = 0; slice < SLICE_CNT; slice++) { 3406 k = (board_cnf->ch[ch].dqs_swap >> 3407 (4 * slice)) & 0x0f; 3408 if (k >= 2) 3409 high_dq[ch] |= (1U << slice); 3410 } 3411 ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00); 3412 } 3413 } 3414 err = 0; 3415 /* CLEAR PREV RESULT */ 3416 for (cs = 0; cs < CS_CNT; cs++) { 3417 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); 3418 if (((prr_product == PRR_PRODUCT_H3) && 3419 (prr_cut > PRR_PRODUCT_11)) || 3420 (prr_product == PRR_PRODUCT_M3N) || 3421 (prr_product == PRR_PRODUCT_V3H)) { 3422 ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 3423 0x01); 3424 } else { 3425 ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 3426 0x01); 3427 } 3428 } 3429 ddrphy_regif_idle(); 3430 3431 #ifndef DDR_FAST_INIT 3432 err_flg = 0; 3433 #endif/* DDR_FAST_INIT */ 3434 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3435 if ((prr_product == PRR_PRODUCT_H3) && 3436 (prr_cut <= PRR_PRODUCT_11)) { 3437 foreach_vch(ch) { 3438 data_l = mmio_read_32(DBSC_DBDFICNT(ch)); 3439 data_l &= ~(0x00ffU << 16); 3440 3441 if (ddr_csn >= 2) 3442 k = (high_dq[ch] ^ 0x0f); 3443 else 3444 k = high_dq[ch]; 3445 data_l |= (k << 16); 3446 mmio_write_32(DBSC_DBDFICNT(ch), data_l); 3447 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); 3448 } 3449 } 3450 if (((prr_product == PRR_PRODUCT_H3) && 3451 (prr_cut <= PRR_PRODUCT_11)) || 3452 ((prr_product == PRR_PRODUCT_M3) && 3453 (prr_cut == PRR_PRODUCT_10))) { 3454 wdqdm_cp(ddr_csn, 0); 3455 } 3456 3457 foreach_vch(ch) { 3458 data_l = 3459 ddr_getval(ch, 3460 reg_pi_mr14_data_fx_csx[1][ddr_csn]); 3461 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l); 3462 } 3463 3464 /* KICK WDQLVL */ 3465 err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); 3466 if (err) 3467 goto err_exit; 3468 3469 if (ddr_csn == 0) 3470 foreach_vch(ch) { 3471 mr14_csab0_bak[ch] = 3472 ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]); 3473 } else 3474 foreach_vch(ch) { 3475 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], 3476 mr14_csab0_bak[ch]); 3477 } 3478 #ifndef DDR_FAST_INIT 3479 foreach_vch(ch) { 3480 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { 3481 wdqdm_clr1(ch, ddr_csn); 3482 continue; 3483 } 3484 err = wdqdm_ana1(ch, ddr_csn); 3485 if (err) 3486 err_flg |= (1U << (ddr_csn * 4 + ch)); 3487 ddrphy_regif_idle(); 3488 } 3489 #endif/* DDR_FAST_INIT */ 3490 } 3491 err_exit: 3492 #ifndef DDR_FAST_INIT 3493 err |= err_flg; 3494 #endif/* DDR_FAST_INIT */ 3495 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3496 ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); 3497 foreach_vch(ch) { 3498 data_l = mmio_read_32(DBSC_DBDFICNT(ch)); 3499 data_l &= ~(0x00ffU << 16); 3500 mmio_write_32(DBSC_DBDFICNT(ch), data_l); 3501 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); 3502 } 3503 } 3504 return err; 3505 } 3506 3507 static uint32_t wdqdm_man(void) 3508 { 3509 uint32_t err, retry_cnt; 3510 const uint32_t retry_max = 0x10; 3511 uint32_t datal, ch, ddr_csn, mr14_bkup[4][4]; 3512 3513 datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19; 3514 if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal) 3515 datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF; 3516 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal); 3517 3518 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || 3519 (prr_product == PRR_PRODUCT_M3N) || 3520 (prr_product == PRR_PRODUCT_V3H)) { 3521 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, 3522 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3523 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, 3524 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3525 } else { 3526 ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, 3527 (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); 3528 } 3529 ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); 3530 ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); 3531 3532 retry_cnt = 0; 3533 err = 0; 3534 do { 3535 if ((prr_product == PRR_PRODUCT_H3) && 3536 (prr_cut <= PRR_PRODUCT_11)) { 3537 err = wdqdm_man1(); 3538 } else { 3539 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); 3540 ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 3541 0x01); 3542 if ((prr_product == PRR_PRODUCT_M3N) || 3543 (prr_product == PRR_PRODUCT_V3H)) { 3544 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3545 0x0C); 3546 } else { 3547 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); 3548 } 3549 dsb_sev(); 3550 err = wdqdm_man1(); 3551 foreach_vch(ch) { 3552 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3553 mr14_bkup[ch][ddr_csn] = 3554 ddr_getval(ch, 3555 reg_pi_mr14_data_fx_csx 3556 [1][ddr_csn]); 3557 dsb_sev(); 3558 } 3559 } 3560 3561 if ((prr_product == PRR_PRODUCT_M3N) || 3562 (prr_product == PRR_PRODUCT_V3H)) { 3563 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3564 0x04); 3565 } else { 3566 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); 3567 } 3568 pvtcode_update(); 3569 err = wdqdm_man1(); 3570 foreach_vch(ch) { 3571 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3572 mr14_bkup[ch][ddr_csn] = 3573 (mr14_bkup[ch][ddr_csn] + 3574 ddr_getval(ch, 3575 reg_pi_mr14_data_fx_csx 3576 [1][ddr_csn])) / 2; 3577 ddr_setval(ch, 3578 reg_pi_mr14_data_fx_csx[1] 3579 [ddr_csn], 3580 mr14_bkup[ch][ddr_csn]); 3581 } 3582 } 3583 3584 ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 3585 0x00); 3586 if ((prr_product == PRR_PRODUCT_M3N) || 3587 (prr_product == PRR_PRODUCT_V3H)) { 3588 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 3589 0x00); 3590 ddr_setval_ach 3591 (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, 3592 0x00); 3593 ddr_setval_ach 3594 (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, 3595 0x00); 3596 } else { 3597 ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); 3598 ddr_setval_ach 3599 (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 3600 0x00); 3601 ddr_setval_ach 3602 (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 3603 0x00); 3604 } 3605 ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 3606 0x00); 3607 3608 pvtcode_update2(); 3609 err = wdqdm_man1(); 3610 ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); 3611 } 3612 } while (err && (++retry_cnt < retry_max)); 3613 3614 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 3615 ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { 3616 wdqdm_cp(0, 1); 3617 } 3618 3619 return (retry_cnt >= retry_max); 3620 } 3621 3622 /* RDQ TRAINING */ 3623 #ifndef DDR_FAST_INIT 3624 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) 3625 { 3626 int32_t i, k; 3627 uint32_t cs, slice; 3628 uint32_t data_l; 3629 3630 /* clr of training results buffer */ 3631 cs = ddr_csn % 2; 3632 data_l = board_cnf->dqdm_dly_r; 3633 for (slice = 0; slice < SLICE_CNT; slice++) { 3634 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3635 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3636 continue; 3637 3638 for (i = 0; i <= 8; i++) { 3639 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) { 3640 rdqdm_dly[ch][cs][slice][i] = 3641 rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; 3642 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = 3643 rdqdm_dly[ch][CS_CNT - 1 - cs][slice + 3644 SLICE_CNT] 3645 [i]; 3646 } else { 3647 rdqdm_dly[ch][cs][slice][i] = data_l; 3648 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = 3649 data_l; 3650 } 3651 rdqdm_le[ch][cs][slice][i] = 0; 3652 rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; 3653 rdqdm_te[ch][cs][slice][i] = 0; 3654 rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; 3655 rdqdm_nw[ch][cs][slice][i] = 0; 3656 rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; 3657 } 3658 rdqdm_st[ch][cs][slice] = 0; 3659 rdqdm_win[ch][cs][slice] = 0; 3660 } 3661 } 3662 3663 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) 3664 { 3665 int32_t i, k; 3666 uint32_t cs, slice; 3667 uint32_t data_l; 3668 uint32_t err; 3669 int8_t _adj; 3670 int16_t adj; 3671 uint32_t dq; 3672 int32_t min_win; 3673 int32_t win; 3674 uint32_t rdq_status_obs_select; 3675 3676 /* analysis of training results */ 3677 err = 0; 3678 for (slice = 0; slice < SLICE_CNT; slice++) { 3679 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; 3680 if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) 3681 continue; 3682 3683 cs = ddr_csn % 2; 3684 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); 3685 ddrphy_regif_idle(); 3686 3687 ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); 3688 ddrphy_regif_idle(); 3689 3690 for (i = 0; i <= 8; i++) { 3691 dq = slice * 8 + i; 3692 if (i == 8) 3693 _adj = board_cnf->ch[ch].dm_adj_r[slice]; 3694 else 3695 _adj = board_cnf->ch[ch].dq_adj_r[dq]; 3696 3697 adj = _f_scale_adj(_adj); 3698 3699 data_l = 3700 ddr_getval_s(ch, slice, 3701 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + 3702 adj; 3703 ddr_setval_s(ch, slice, 3704 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], 3705 data_l); 3706 rdqdm_dly[ch][cs][slice][i] = data_l; 3707 3708 data_l = 3709 ddr_getval_s(ch, slice, 3710 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + 3711 adj; 3712 ddr_setval_s(ch, slice, 3713 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], 3714 data_l); 3715 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; 3716 } 3717 min_win = INT_LEAST32_MAX; 3718 for (i = 0; i <= 8; i++) { 3719 data_l = 3720 ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); 3721 rdqdm_st[ch][cs][slice] = data_l; 3722 rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l; 3723 /* k : rise/fall */ 3724 for (k = 0; k < 2; k++) { 3725 if (i == 8) { 3726 rdq_status_obs_select = 16 + 8 * k; 3727 } else { 3728 rdq_status_obs_select = i + k * 8; 3729 } 3730 ddr_setval_s(ch, slice, 3731 _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, 3732 rdq_status_obs_select); 3733 3734 data_l = 3735 ddr_getval_s(ch, slice, 3736 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); 3737 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = 3738 data_l; 3739 3740 data_l = 3741 ddr_getval_s(ch, slice, 3742 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); 3743 rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = 3744 data_l; 3745 3746 data_l = 3747 ddr_getval_s(ch, slice, 3748 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); 3749 rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = 3750 data_l; 3751 3752 win = 3753 (int32_t)rdqdm_te[ch][cs][slice + 3754 SLICE_CNT * 3755 k][i] - 3756 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; 3757 if (i != 8) { 3758 if (min_win > win) 3759 min_win = win; 3760 } 3761 } 3762 } 3763 rdqdm_win[ch][cs][slice] = min_win; 3764 if (min_win <= 0) { 3765 err = 2; 3766 } 3767 } 3768 return err; 3769 } 3770 #endif/* DDR_FAST_INIT */ 3771 3772 static uint32_t rdqdm_man1(void) 3773 { 3774 uint32_t ch; 3775 uint32_t ddr_csn; 3776 #ifdef DDR_FAST_INIT 3777 uint32_t slice; 3778 uint32_t i, adj, data_l; 3779 #endif/* DDR_FAST_INIT */ 3780 uint32_t err; 3781 3782 /* manual execution of training */ 3783 err = 0; 3784 3785 for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { 3786 /* KICK RDQLVL */ 3787 err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); 3788 if (err) 3789 goto err_exit; 3790 #ifndef DDR_FAST_INIT 3791 foreach_vch(ch) { 3792 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { 3793 rdqdm_clr1(ch, ddr_csn); 3794 ddrphy_regif_idle(); 3795 continue; 3796 } 3797 err = rdqdm_ana1(ch, ddr_csn); 3798 ddrphy_regif_idle(); 3799 if (err) 3800 goto err_exit; 3801 } 3802 #else/* DDR_FAST_INIT */ 3803 foreach_vch(ch) { 3804 if (ch_have_this_cs[ddr_csn] & (1U << ch)) { 3805 for (slice = 0; slice < SLICE_CNT; slice++) { 3806 if (ddr_getval_s(ch, slice, 3807 _reg_PHY_RDLVL_STATUS_OBS) != 3808 0x0D00FFFF) { 3809 err = (1U << ch) | 3810 (0x10U << slice); 3811 goto err_exit; 3812 } 3813 } 3814 } 3815 if (((prr_product == PRR_PRODUCT_H3) && 3816 (prr_cut <= PRR_PRODUCT_11)) || 3817 ((prr_product == PRR_PRODUCT_M3) && 3818 (prr_cut <= PRR_PRODUCT_10))) { 3819 for (slice = 0; slice < SLICE_CNT; slice++) { 3820 for (i = 0; i <= 8; i++) { 3821 if (i == 8) 3822 adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]); 3823 else 3824 adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]); 3825 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); 3826 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; 3827 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l); 3828 rdqdm_dly[ch][ddr_csn][slice][i] = data_l; 3829 rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l; 3830 3831 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; 3832 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l); 3833 rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l; 3834 rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l; 3835 } 3836 } 3837 } 3838 } 3839 ddrphy_regif_idle(); 3840 3841 #endif/* DDR_FAST_INIT */ 3842 } 3843 3844 err_exit: 3845 return err; 3846 } 3847 3848 static uint32_t rdqdm_man(void) 3849 { 3850 uint32_t err, retry_cnt; 3851 const uint32_t retry_max = 0x01; 3852 3853 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, 3854 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3855 _reg_PHY_DQ_TSEL_ENABLE)); 3856 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, 3857 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3858 _reg_PHY_DQS_TSEL_ENABLE)); 3859 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, 3860 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3861 _reg_PHY_DQ_TSEL_SELECT)); 3862 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, 3863 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3864 _reg_PHY_DQS_TSEL_SELECT)); 3865 3866 retry_cnt = 0; 3867 do { 3868 err = rdqdm_man1(); 3869 ddrphy_regif_idle(); 3870 } while (err && (++retry_cnt < retry_max)); 3871 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, 3872 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3873 _reg_PHY_DQ_TSEL_ENABLE)); 3874 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, 3875 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3876 _reg_PHY_DQS_TSEL_ENABLE)); 3877 ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, 3878 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3879 _reg_PHY_DQ_TSEL_SELECT)); 3880 ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, 3881 ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, 3882 _reg_PHY_DQS_TSEL_SELECT)); 3883 3884 return (retry_cnt >= retry_max); 3885 } 3886 3887 /* rx offset calibration */ 3888 static int32_t _find_change(uint64_t val, uint32_t dir) 3889 { 3890 int32_t i; 3891 uint32_t startval; 3892 uint32_t curval; 3893 const int32_t VAL_END = 0x3f; 3894 3895 if (dir == 0) { 3896 startval = (val & 0x01); 3897 for (i = 1; i <= VAL_END; i++) { 3898 curval = (val >> i) & 0x01; 3899 if (curval != startval) 3900 return i; 3901 } 3902 return VAL_END; 3903 } 3904 3905 startval = (val >> dir) & 0x01; 3906 for (i = dir - 1; i >= 0; i--) { 3907 curval = (val >> i) & 0x01; 3908 if (curval != startval) 3909 return i; 3910 } 3911 return 0; 3912 } 3913 3914 static uint32_t _rx_offset_cal_updn(uint32_t code) 3915 { 3916 const uint32_t CODE_MAX = 0x40; 3917 uint32_t tmp; 3918 3919 if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { 3920 if (code == 0) 3921 tmp = (1U << 6) | (CODE_MAX - 1); 3922 else if (code <= 0x20) 3923 tmp = 3924 ((CODE_MAX - 1 - 3925 (0x20 - code) * 2) << 6) | (CODE_MAX - 1); 3926 else 3927 tmp = 3928 ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 - 3929 (code - 0x20) * 2); 3930 } else { 3931 if (code == 0) 3932 tmp = (1U << 6) | (CODE_MAX - 1); 3933 else 3934 tmp = (code << 6) | (CODE_MAX - code); 3935 } 3936 return tmp; 3937 } 3938 3939 static uint32_t rx_offset_cal(void) 3940 { 3941 uint32_t index; 3942 uint32_t code; 3943 const uint32_t CODE_MAX = 0x40; 3944 const uint32_t CODE_STEP = 2; 3945 uint32_t ch, slice; 3946 uint32_t tmp; 3947 uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; 3948 uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; 3949 uint64_t tmpval; 3950 int32_t lsb, msb; 3951 3952 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); 3953 foreach_vch(ch) { 3954 for (slice = 0; slice < SLICE_CNT; slice++) { 3955 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) 3956 val[ch][slice][index] = 0; 3957 } 3958 } 3959 3960 for (code = 0; code < CODE_MAX / CODE_STEP; code++) { 3961 tmp = _rx_offset_cal_updn(code * CODE_STEP); 3962 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { 3963 ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); 3964 } 3965 dsb_sev(); 3966 ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); 3967 3968 foreach_vch(ch) { 3969 for (slice = 0; slice < SLICE_CNT; slice++) { 3970 tmp = tmp_ach_as[ch][slice]; 3971 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; 3972 index++) { 3973 if (tmp & (1U << index)) { 3974 val[ch][slice][index] |= 3975 (1ULL << code); 3976 } else { 3977 val[ch][slice][index] &= 3978 ~(1ULL << code); 3979 } 3980 } 3981 } 3982 } 3983 } 3984 foreach_vch(ch) { 3985 for (slice = 0; slice < SLICE_CNT; slice++) { 3986 for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; 3987 index++) { 3988 tmpval = val[ch][slice][index]; 3989 lsb = _find_change(tmpval, 0); 3990 msb = 3991 _find_change(tmpval, 3992 (CODE_MAX / CODE_STEP) - 1); 3993 tmp = (lsb + msb) >> 1; 3994 3995 tmp = _rx_offset_cal_updn(tmp * CODE_STEP); 3996 ddr_setval_s(ch, slice, 3997 _reg_PHY_RX_CAL_X[index], tmp); 3998 } 3999 } 4000 } 4001 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); 4002 4003 return 0; 4004 } 4005 4006 static uint32_t rx_offset_cal_hw(void) 4007 { 4008 uint32_t ch, slice; 4009 uint32_t retry; 4010 uint32_t complete; 4011 uint32_t tmp; 4012 uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; 4013 4014 ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); 4015 ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); 4016 ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); 4017 4018 retry = 0; 4019 while (retry < 4096) { 4020 if ((retry & 0xff) == 0) { 4021 ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); 4022 } 4023 foreach_vch(ch) 4024 for (slice = 0; slice < SLICE_CNT; slice++) 4025 tmp_ach_as[ch][slice] = 4026 ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); 4027 4028 complete = 1; 4029 foreach_vch(ch) { 4030 for (slice = 0; slice < SLICE_CNT; slice++) { 4031 tmp = tmp_ach_as[ch][slice]; 4032 tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); 4033 if (((prr_product == PRR_PRODUCT_H3) && 4034 (prr_cut > PRR_PRODUCT_11)) || 4035 (prr_product == PRR_PRODUCT_M3N) || 4036 (prr_product == PRR_PRODUCT_V3H)) { 4037 if (tmp != 0x3E) 4038 complete = 0; 4039 } else { 4040 if (tmp != 0x40) 4041 complete = 0; 4042 } 4043 } 4044 } 4045 if (complete) 4046 break; 4047 4048 retry++; 4049 } 4050 4051 return (complete == 0); 4052 } 4053 4054 /* adjust rddqs latency */ 4055 static void adjust_rddqs_latency(void) 4056 { 4057 uint32_t ch, slice; 4058 uint32_t dly; 4059 uint32_t maxlatx2; 4060 uint32_t tmp; 4061 uint32_t rdlat_adjx2[SLICE_CNT]; 4062 4063 foreach_vch(ch) { 4064 maxlatx2 = 0; 4065 for (slice = 0; slice < SLICE_CNT; slice++) { 4066 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, 4067 0x00); 4068 4069 dly = 4070 ddr_getval_s(ch, slice, 4071 _reg_PHY_RDDQS_GATE_SLAVE_DELAY); 4072 tmp = 4073 ddr_getval_s(ch, slice, 4074 _reg_PHY_RDDQS_LATENCY_ADJUST); 4075 /* note gate_slave_delay[9] is always 0 */ 4076 tmp = (tmp << 1) + (dly >> 8); 4077 rdlat_adjx2[slice] = tmp; 4078 if (maxlatx2 < tmp) 4079 maxlatx2 = tmp; 4080 } 4081 maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; 4082 for (slice = 0; slice < SLICE_CNT; slice++) { 4083 tmp = maxlatx2 - rdlat_adjx2[slice]; 4084 tmp = (tmp >> 1); 4085 if (tmp) { 4086 ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, 4087 ddr_getval_s(ch, slice, 4088 _reg_PHY_RPTR_UPDATE) 4089 + 1); 4090 } 4091 } 4092 } 4093 } 4094 4095 /* adjust wpath latency */ 4096 static void adjust_wpath_latency(void) 4097 { 4098 uint32_t ch, cs, slice; 4099 uint32_t dly; 4100 uint32_t wpath_add; 4101 const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; 4102 4103 foreach_vch(ch) { 4104 for (slice = 0; slice < SLICE_CNT; slice += 1) { 4105 for (cs = 0; cs < CS_CNT; cs++) { 4106 ddr_setval_s(ch, slice, 4107 _reg_PHY_PER_CS_TRAINING_INDEX, 4108 cs); 4109 ddr_getval_s(ch, slice, 4110 _reg_PHY_PER_CS_TRAINING_INDEX); 4111 dly = 4112 ddr_getval_s(ch, slice, 4113 _reg_PHY_CLK_WRDQS_SLAVE_DELAY); 4114 if (dly <= _par_EARLY_THRESHOLD_VAL) 4115 continue; 4116 4117 wpath_add = 4118 ddr_getval_s(ch, slice, 4119 _reg_PHY_WRITE_PATH_LAT_ADD); 4120 ddr_setval_s(ch, slice, 4121 _reg_PHY_WRITE_PATH_LAT_ADD, 4122 wpath_add - 1); 4123 } 4124 } 4125 } 4126 } 4127 4128 /* DDR Initialize entry */ 4129 int32_t rcar_dram_init(void) 4130 { 4131 uint32_t ch, cs; 4132 uint32_t data_l; 4133 uint32_t bus_mbps, bus_mbpsdiv; 4134 uint32_t tmp_tccd; 4135 uint32_t failcount; 4136 uint32_t cnf_boardtype; 4137 4138 /* Thermal sensor setting */ 4139 data_l = mmio_read_32(CPG_MSTPSR5); 4140 if (data_l & BIT(22)) { /* case THS/TSC Standby */ 4141 data_l &= ~BIT(22); 4142 cpg_write_32(CPG_SMSTPCR5, data_l); 4143 while (mmio_read_32(CPG_MSTPSR5) & BIT(22)) 4144 ; /* wait bit=0 */ 4145 } 4146 4147 /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ 4148 data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; 4149 mmio_write_32(THS1_THCTR, data_l); 4150 4151 /* Judge product and cut */ 4152 #ifdef RCAR_DDR_FIXED_LSI_TYPE 4153 #if (RCAR_LSI == RCAR_AUTO) 4154 prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; 4155 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4156 #else /* RCAR_LSI */ 4157 #ifndef RCAR_LSI_CUT 4158 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4159 #endif /* RCAR_LSI_CUT */ 4160 #endif /* RCAR_LSI */ 4161 #else /* RCAR_DDR_FIXED_LSI_TYPE */ 4162 prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; 4163 prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; 4164 #endif /* RCAR_DDR_FIXED_LSI_TYPE */ 4165 4166 if (prr_product == PRR_PRODUCT_H3) { 4167 if (prr_cut <= PRR_PRODUCT_11) { 4168 p_ddr_regdef_tbl = 4169 (const uint32_t *)&DDR_REGDEF_TBL[0][0]; 4170 } else { 4171 p_ddr_regdef_tbl = 4172 (const uint32_t *)&DDR_REGDEF_TBL[2][0]; 4173 } 4174 } else if (prr_product == PRR_PRODUCT_M3) { 4175 p_ddr_regdef_tbl = 4176 (const uint32_t *)&DDR_REGDEF_TBL[1][0]; 4177 } else if ((prr_product == PRR_PRODUCT_M3N) || 4178 (prr_product == PRR_PRODUCT_V3H)) { 4179 p_ddr_regdef_tbl = 4180 (const uint32_t *)&DDR_REGDEF_TBL[3][0]; 4181 } else { 4182 FATAL_MSG("BL2: DDR:Unknown Product\n"); 4183 return 0xff; 4184 } 4185 4186 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 4187 ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { 4188 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 4189 } else { 4190 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); 4191 } 4192 4193 /* Judge board type */ 4194 cnf_boardtype = boardcnf_get_brd_type(); 4195 if (cnf_boardtype >= BOARDNUM) { 4196 FATAL_MSG("BL2: DDR:Unknown Board\n"); 4197 return 0xff; 4198 } 4199 board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype]; 4200 4201 /* RCAR_DRAM_SPLIT_2CH (2U) */ 4202 #if RCAR_DRAM_SPLIT == 2 4203 /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */ 4204 if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { 4205 mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); 4206 ddr_phyvalid = 0x03; 4207 } else { 4208 ddr_phyvalid = board_cnf->phyvalid; 4209 } 4210 #else /* RCAR_DRAM_SPLIT_2CH */ 4211 ddr_phyvalid = board_cnf->phyvalid; 4212 #endif /* RCAR_DRAM_SPLIT_2CH */ 4213 4214 max_density = 0; 4215 4216 for (cs = 0; cs < CS_CNT; cs++) { 4217 ch_have_this_cs[cs] = 0; 4218 } 4219 4220 foreach_ech(ch) 4221 for (cs = 0; cs < CS_CNT; cs++) 4222 ddr_density[ch][cs] = 0xff; 4223 4224 foreach_vch(ch) { 4225 for (cs = 0; cs < CS_CNT; cs++) { 4226 data_l = board_cnf->ch[ch].ddr_density[cs]; 4227 ddr_density[ch][cs] = data_l; 4228 4229 if (data_l == 0xff) 4230 continue; 4231 if (data_l > max_density) 4232 max_density = data_l; 4233 if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) && 4234 (prr_cut <= PRR_PRODUCT_11)) 4235 continue; 4236 ch_have_this_cs[cs] |= (1U << ch); 4237 } 4238 } 4239 4240 /* Judge board clock frequency (in MHz) */ 4241 boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); 4242 if ((brd_clk / brd_clkdiv) > 25) { 4243 brd_clkdiva = 1; 4244 } else { 4245 brd_clkdiva = 0; 4246 } 4247 4248 /* Judge ddr operating frequency clock(in Mbps) */ 4249 boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); 4250 4251 ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); 4252 4253 ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, 4254 brd_clkdiv * (brd_clkdiva + 1)); 4255 4256 /* Adjust tccd */ 4257 data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; 4258 bus_mbps = 0; 4259 bus_mbpsdiv = 0; 4260 switch (data_l) { 4261 case 0: 4262 bus_mbps = brd_clk * 0x60 * 2; 4263 bus_mbpsdiv = brd_clkdiv * 1; 4264 break; 4265 case 1: 4266 bus_mbps = brd_clk * 0x50 * 2; 4267 bus_mbpsdiv = brd_clkdiv * 1; 4268 break; 4269 case 2: 4270 bus_mbps = brd_clk * 0x40 * 2; 4271 bus_mbpsdiv = brd_clkdiv * 1; 4272 break; 4273 case 3: 4274 bus_mbps = brd_clk * 0x60 * 2; 4275 bus_mbpsdiv = brd_clkdiv * 2; 4276 break; 4277 default: 4278 bus_mbps = brd_clk * 0x60 * 2; 4279 bus_mbpsdiv = brd_clkdiv * 2; 4280 break; 4281 } 4282 tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); 4283 if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) 4284 tmp_tccd = tmp_tccd + 1; 4285 4286 if (tmp_tccd < 8) 4287 ddr_tccd = 8; 4288 else 4289 ddr_tccd = tmp_tccd; 4290 4291 NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); 4292 4293 MSG_LF("Start\n"); 4294 4295 /* PLL Setting */ 4296 pll3_control(1); 4297 4298 /* initialize DDR */ 4299 data_l = init_ddr(); 4300 if (data_l == ddr_phyvalid) { 4301 failcount = 0; 4302 } else { 4303 failcount = 1; 4304 } 4305 4306 foreach_vch(ch) 4307 mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); 4308 if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || 4309 ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { 4310 /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ 4311 } else { 4312 mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); 4313 } 4314 4315 if (failcount == 0) { 4316 return INITDRAM_OK; 4317 } else { 4318 return INITDRAM_NG; 4319 } 4320 } 4321 4322 void pvtcode_update(void) 4323 { 4324 uint32_t ch; 4325 uint32_t data_l; 4326 uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; 4327 int32_t pvtp_tmp, pvtn_tmp; 4328 4329 foreach_vch(ch) { 4330 pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; 4331 pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; 4332 4333 if (8912 * pvtp_init > 44230) { 4334 pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; 4335 } else { 4336 pvtp_tmp = 4337 -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); 4338 } 4339 pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; 4340 4341 pvtn[ch] = pvtn_tmp + pvtn_init; 4342 pvtp[ch] = pvtp_tmp + pvtp_init; 4343 4344 if (pvtn[ch] > 63) { 4345 pvtn[ch] = 63; 4346 pvtp[ch] = 4347 (pvtp_tmp) * (63 - 6 * pvtn_tmp - 4348 pvtn_init) / (pvtn_tmp) + 4349 6 * pvtp_tmp + pvtp_init; 4350 } 4351 if ((prr_product == PRR_PRODUCT_H3) && 4352 (prr_cut <= PRR_PRODUCT_11)) { 4353 data_l = pvtp[ch] | (pvtn[ch] << 6) | 4354 (tcal.tcomp_cal[ch] & 0xfffff000); 4355 reg_ddrphy_write(ch, 4356 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4357 data_l | 0x00020000); 4358 reg_ddrphy_write(ch, 4359 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4360 data_l); 4361 reg_ddrphy_write(ch, 4362 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4363 data_l); 4364 reg_ddrphy_write(ch, 4365 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4366 data_l); 4367 reg_ddrphy_write(ch, 4368 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4369 data_l); 4370 } else { 4371 data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; 4372 reg_ddrphy_write(ch, 4373 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4374 data_l | 0x00020000); 4375 reg_ddrphy_write(ch, 4376 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4377 data_l); 4378 reg_ddrphy_write(ch, 4379 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4380 data_l); 4381 reg_ddrphy_write(ch, 4382 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4383 data_l); 4384 reg_ddrphy_write(ch, 4385 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4386 data_l); 4387 } 4388 } 4389 } 4390 4391 void pvtcode_update2(void) 4392 { 4393 uint32_t ch; 4394 4395 foreach_vch(ch) { 4396 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), 4397 tcal.init_cal[ch] | 0x00020000); 4398 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), 4399 tcal.init_cal[ch]); 4400 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), 4401 tcal.init_cal[ch]); 4402 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), 4403 tcal.init_cal[ch]); 4404 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), 4405 tcal.init_cal[ch]); 4406 } 4407 } 4408 4409 void ddr_padcal_tcompensate_getinit(uint32_t override) 4410 { 4411 uint32_t ch; 4412 uint32_t data_l; 4413 uint32_t pvtp, pvtn; 4414 4415 tcal.init_temp = 0; 4416 for (ch = 0; ch < 4; ch++) { 4417 tcal.init_cal[ch] = 0; 4418 tcal.tcomp_cal[ch] = 0; 4419 } 4420 4421 foreach_vch(ch) { 4422 tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); 4423 tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); 4424 } 4425 4426 if (!override) { 4427 data_l = mmio_read_32(THS1_TEMP); 4428 if (data_l < 2800) { 4429 tcal.init_temp = 4430 (143 * (int32_t)data_l - 359000) / 1000; 4431 } else { 4432 tcal.init_temp = 4433 (121 * (int32_t)data_l - 296300) / 1000; 4434 } 4435 4436 foreach_vch(ch) { 4437 pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; 4438 pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; 4439 if ((int32_t)pvtp > 4440 ((tcal.init_temp * 29 - 3625) / 1000)) 4441 pvtp = 4442 (int32_t)pvtp + 4443 ((3625 - tcal.init_temp * 29) / 1000); 4444 else 4445 pvtp = 0; 4446 4447 if ((int32_t)pvtn > 4448 ((tcal.init_temp * 54 - 6750) / 1000)) 4449 pvtn = 4450 (int32_t)pvtn + 4451 ((6750 - tcal.init_temp * 54) / 1000); 4452 else 4453 pvtn = 0; 4454 4455 if ((prr_product == PRR_PRODUCT_H3) && 4456 (prr_cut <= PRR_PRODUCT_11)) { 4457 tcal.init_cal[ch] = 4458 (tcal.init_cal[ch] & 0xfffff000) | 4459 (pvtn << 6) | 4460 pvtp; 4461 } else { 4462 tcal.init_cal[ch] = 4463 0x00015000 | (pvtn << 6) | pvtp; 4464 } 4465 } 4466 tcal.init_temp = 125; 4467 } 4468 } 4469 4470 #ifndef ddr_qos_init_setting 4471 /* For QoS init */ 4472 uint8_t get_boardcnf_phyvalid(void) 4473 { 4474 return ddr_phyvalid; 4475 } 4476 #endif /* ddr_qos_init_setting */ 4477