1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <bl31/interrupt_mgmt.h> 12 #include <caam.h> 13 #include <cassert.h> 14 #include <ccn.h> 15 #include <common/debug.h> 16 #include <dcfg.h> 17 #ifdef I2C_INIT 18 #include <i2c.h> 19 #endif 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <ls_interconnect.h> 23 #ifdef POLICY_FUSE_PROVISION 24 #include <nxp_gpio.h> 25 #endif 26 #if TRUSTED_BOARD_BOOT 27 #include <nxp_smmu.h> 28 #endif 29 #include <nxp_timer.h> 30 #include <plat_console.h> 31 #include <plat_gic.h> 32 #include <plat_tzc400.h> 33 #include <pmu.h> 34 #if defined(NXP_SFP_ENABLED) 35 #include <sfp.h> 36 #endif 37 38 #include <errata.h> 39 #include <ls_interrupt_mgmt.h> 40 #include "plat_common.h" 41 #ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA 42 #include <plat_nv_storage.h> 43 #endif 44 #ifdef NXP_WARM_BOOT 45 #include <plat_warm_rst.h> 46 #endif 47 #include "platform_def.h" 48 #include "soc.h" 49 50 static struct soc_type soc_list[] = { 51 SOC_ENTRY(LX2160A, LX2160A, 8, 2), 52 SOC_ENTRY(LX2080A, LX2080A, 8, 1), 53 SOC_ENTRY(LX2120A, LX2120A, 6, 2), 54 }; 55 56 static dcfg_init_info_t dcfg_init_data = { 57 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 58 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 59 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 60 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 61 }; 62 static const unsigned char master_to_6rn_id_map[] = { 63 PLAT_6CLUSTER_TO_CCN_ID_MAP 64 }; 65 66 static const unsigned char master_to_rn_id_map[] = { 67 PLAT_CLUSTER_TO_CCN_ID_MAP 68 }; 69 70 CASSERT(ARRAY_SIZE(master_to_rn_id_map) == NUMBER_OF_CLUSTERS, 71 assert_invalid_cluster_count_for_ccn_variant); 72 73 static const ccn_desc_t plat_six_cluster_ccn_desc = { 74 .periphbase = NXP_CCN_ADDR, 75 .num_masters = ARRAY_SIZE(master_to_6rn_id_map), 76 .master_to_rn_id_map = master_to_6rn_id_map 77 }; 78 79 static const ccn_desc_t plat_ccn_desc = { 80 .periphbase = NXP_CCN_ADDR, 81 .num_masters = ARRAY_SIZE(master_to_rn_id_map), 82 .master_to_rn_id_map = master_to_rn_id_map 83 }; 84 85 /******************************************************************************* 86 * This function returns the number of clusters in the SoC 87 ******************************************************************************/ 88 static unsigned int get_num_cluster(void) 89 { 90 const soc_info_t *soc_info = get_soc_info(); 91 uint32_t num_clusters = NUMBER_OF_CLUSTERS; 92 unsigned int i; 93 94 for (i = 0U; i < ARRAY_SIZE(soc_list); i++) { 95 if (soc_list[i].personality == soc_info->personality) { 96 num_clusters = soc_list[i].num_clusters; 97 break; 98 } 99 } 100 101 VERBOSE("NUM of cluster = 0x%x\n", num_clusters); 102 103 return num_clusters; 104 } 105 106 107 /****************************************************************************** 108 * Function returns the base counter frequency 109 * after reading the first entry at CNTFID0 (0x20 offset). 110 * 111 * Function is used by: 112 * 1. ARM common code for PSCI management. 113 * 2. ARM Generic Timer init. 114 * 115 *****************************************************************************/ 116 unsigned int plat_get_syscnt_freq2(void) 117 { 118 unsigned int counter_base_frequency; 119 /* 120 * Below register specifies the base frequency of the system counter. 121 * As per NXP Board Manuals: 122 * The system counter always works with SYS_REF_CLK/4 frequency clock. 123 * 124 * 125 */ 126 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 127 128 return counter_base_frequency; 129 } 130 131 #ifdef IMAGE_BL2 132 133 #ifdef POLICY_FUSE_PROVISION 134 static gpio_init_info_t gpio_init_data = { 135 .gpio1_base_addr = NXP_GPIO1_ADDR, 136 .gpio2_base_addr = NXP_GPIO2_ADDR, 137 .gpio3_base_addr = NXP_GPIO3_ADDR, 138 .gpio4_base_addr = NXP_GPIO4_ADDR, 139 }; 140 #endif 141 142 static void soc_interconnect_config(void) 143 { 144 unsigned long long val = 0x0U; 145 146 uint32_t num_clusters = get_num_cluster(); 147 148 if (num_clusters == 6U) { 149 ccn_init(&plat_six_cluster_ccn_desc); 150 } else { 151 ccn_init(&plat_ccn_desc); 152 } 153 154 /* 155 * Enable Interconnect coherency for the primary CPU's cluster. 156 */ 157 plat_ls_interconnect_enter_coherency(num_clusters); 158 159 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET); 160 val |= (1 << 17); 161 ccn_write_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET, val); 162 163 /* PCIe is Connected to RN-I 17 which is connected to HN-I 13. */ 164 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET); 165 val |= (1 << 17); 166 ccn_write_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET, val); 167 168 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); 169 val |= SERIALIZE_DEV_nGnRnE_WRITES; 170 ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); 171 172 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); 173 val &= ~(ENABLE_RESERVE_BIT53); 174 val |= SERIALIZE_DEV_nGnRnE_WRITES; 175 ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); 176 177 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET); 178 val &= ~(HNI_POS_EN); 179 ccn_write_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET, val); 180 181 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET); 182 val &= ~(HNI_POS_EN); 183 ccn_write_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET, val); 184 185 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); 186 val &= ~(POS_EARLY_WR_COMP_EN); 187 ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); 188 189 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); 190 val &= ~(POS_EARLY_WR_COMP_EN); 191 ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); 192 193 #if POLICY_PERF_WRIOP 194 uint16_t wriop_rni = 0U; 195 196 if (POLICY_PERF_WRIOP == 1) { 197 wriop_rni = 7U; 198 } else if (POLICY_PERF_WRIOP == 2) { 199 wriop_rni = 23U; 200 } else { 201 ERROR("Incorrect WRIOP selected.\n"); 202 panic(); 203 } 204 205 val = ccn_read_node_reg(NODE_TYPE_RNI, wriop_rni, 206 SA_AUX_CTRL_REG_OFFSET); 207 val |= ENABLE_WUO; 208 ccn_write_node_reg(NODE_TYPE_HNI, wriop_rni, SA_AUX_CTRL_REG_OFFSET, 209 val); 210 #else 211 val = ccn_read_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET); 212 val |= ENABLE_WUO; 213 ccn_write_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET, val); 214 #endif 215 } 216 217 218 void soc_preload_setup(void) 219 { 220 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 221 #if defined(NXP_WARM_BOOT) 222 bool warm_reset = is_warm_boot(); 223 #endif 224 info_dram_regions->total_dram_size = 225 #if defined(NXP_WARM_BOOT) 226 init_ddr(warm_reset); 227 #else 228 init_ddr(); 229 #endif 230 } 231 232 /******************************************************************************* 233 * This function implements soc specific erratas 234 * This is called before DDR is initialized or MMU is enabled 235 ******************************************************************************/ 236 void soc_early_init(void) 237 { 238 dcfg_init(&dcfg_init_data); 239 #ifdef POLICY_FUSE_PROVISION 240 gpio_init(&gpio_init_data); 241 sec_init(NXP_CAAM_ADDR); 242 #endif 243 #if LOG_LEVEL > 0 244 /* Initialize the console to provide early debug support */ 245 plat_console_init(NXP_CONSOLE_ADDR, 246 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 247 #endif 248 249 enable_timer_base_to_cluster(NXP_PMU_ADDR); 250 soc_interconnect_config(); 251 252 enum boot_device dev = get_boot_dev(); 253 /* Mark the buffer for SD in OCRAM as non secure. 254 * The buffer is assumed to be at end of OCRAM for 255 * the logic below to calculate TZPC programming 256 */ 257 if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { 258 /* Calculate the region in OCRAM which is secure 259 * The buffer for SD needs to be marked non-secure 260 * to allow SD to do DMA operations on it 261 */ 262 uint32_t secure_region = (NXP_OCRAM_SIZE 263 - NXP_SD_BLOCK_BUF_SIZE); 264 uint32_t mask = secure_region/TZPC_BLOCK_SIZE; 265 266 mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); 267 268 /* Add the entry for buffer in MMU Table */ 269 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 270 NXP_SD_BLOCK_BUF_SIZE, 271 MT_DEVICE | MT_RW | MT_NS); 272 } 273 274 #ifdef ERRATA_SOC_A050426 275 erratum_a050426(); 276 #endif 277 278 #if (TRUSTED_BOARD_BOOT) || defined(POLICY_FUSE_PROVISION) 279 sfp_init(NXP_SFP_ADDR); 280 #endif 281 282 #if TRUSTED_BOARD_BOOT 283 uint32_t mode; 284 285 /* For secure boot disable SMMU. 286 * Later when platform security policy comes in picture, 287 * this might get modified based on the policy 288 */ 289 if (check_boot_mode_secure(&mode) == true) { 290 bypass_smmu(NXP_SMMU_ADDR); 291 } 292 293 /* For Mbedtls currently crypto is not supported via CAAM 294 * enable it when that support is there. In tbbr.mk 295 * the CAAM_INTEG is set as 0. 296 */ 297 298 #ifndef MBEDTLS_X509 299 /* Initialize the crypto accelerator if enabled */ 300 if (is_sec_enabled() == false) 301 INFO("SEC is disabled.\n"); 302 else 303 sec_init(NXP_CAAM_ADDR); 304 #endif 305 #endif 306 307 /* 308 * Initialize system level generic timer for Layerscape Socs. 309 */ 310 delay_timer_init(NXP_TIMER_ADDR); 311 i2c_init(NXP_I2C_ADDR); 312 } 313 314 void soc_bl2_prepare_exit(void) 315 { 316 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 317 set_sfp_wr_disable(); 318 #endif 319 } 320 321 /***************************************************************************** 322 * This function returns the boot device based on RCW_SRC 323 ****************************************************************************/ 324 enum boot_device get_boot_dev(void) 325 { 326 enum boot_device src = BOOT_DEVICE_NONE; 327 uint32_t porsr1; 328 uint32_t rcw_src; 329 330 porsr1 = read_reg_porsr1(); 331 332 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 333 334 switch (rcw_src) { 335 case FLEXSPI_NOR: 336 src = BOOT_DEVICE_FLEXSPI_NOR; 337 INFO("RCW BOOT SRC is FLEXSPI NOR\n"); 338 break; 339 case FLEXSPI_NAND2K_VAL: 340 case FLEXSPI_NAND4K_VAL: 341 INFO("RCW BOOT SRC is FLEXSPI NAND\n"); 342 src = BOOT_DEVICE_FLEXSPI_NAND; 343 break; 344 case SDHC1_VAL: 345 src = BOOT_DEVICE_EMMC; 346 INFO("RCW BOOT SRC is SD\n"); 347 break; 348 case SDHC2_VAL: 349 src = BOOT_DEVICE_SDHC2_EMMC; 350 INFO("RCW BOOT SRC is EMMC\n"); 351 break; 352 default: 353 break; 354 } 355 356 return src; 357 } 358 359 360 void soc_mem_access(void) 361 { 362 const devdisr5_info_t *devdisr5_info = get_devdisr5_info(); 363 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 364 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 365 int dram_idx, index = 0U; 366 367 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions; 368 dram_idx++) { 369 if (info_dram_regions->region[dram_idx].size == 0) { 370 ERROR("DDR init failure, or"); 371 ERROR("DRAM regions not populated correctly.\n"); 372 break; 373 } 374 375 index = populate_tzc400_reg_list(tzc400_reg_list, 376 dram_idx, index, 377 info_dram_regions->region[dram_idx].addr, 378 info_dram_regions->region[dram_idx].size, 379 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 380 } 381 382 if (devdisr5_info->ddrc1_present != 0) { 383 INFO("DDR Controller 1.\n"); 384 mem_access_setup(NXP_TZC_ADDR, index, 385 tzc400_reg_list); 386 mem_access_setup(NXP_TZC3_ADDR, index, 387 tzc400_reg_list); 388 } 389 if (devdisr5_info->ddrc2_present != 0) { 390 INFO("DDR Controller 2.\n"); 391 mem_access_setup(NXP_TZC2_ADDR, index, 392 tzc400_reg_list); 393 mem_access_setup(NXP_TZC4_ADDR, index, 394 tzc400_reg_list); 395 } 396 } 397 398 #else 399 const unsigned char _power_domain_tree_desc[] = {1, 8, 2, 2, 2, 2, 2, 2, 2, 2}; 400 401 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 402 assert_invalid_lx2160a_cluster_count); 403 404 /****************************************************************************** 405 * This function returns the SoC topology 406 ****************************************************************************/ 407 408 const unsigned char *plat_get_power_domain_tree_desc(void) 409 { 410 411 return _power_domain_tree_desc; 412 } 413 414 /******************************************************************************* 415 * This function returns the core count within the cluster corresponding to 416 * `mpidr`. 417 ******************************************************************************/ 418 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 419 { 420 return CORES_PER_CLUSTER; 421 } 422 423 424 void soc_early_platform_setup2(void) 425 { 426 dcfg_init(&dcfg_init_data); 427 /* 428 * Initialize system level generic timer for Socs 429 */ 430 delay_timer_init(NXP_TIMER_ADDR); 431 432 #if LOG_LEVEL > 0 433 /* Initialize the console to provide early debug support */ 434 plat_console_init(NXP_CONSOLE_ADDR, 435 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 436 #endif 437 } 438 439 void soc_platform_setup(void) 440 { 441 /* Initialize the GIC driver, cpu and distributor interfaces */ 442 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 443 static interrupt_prop_t ls_interrupt_props[] = { 444 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 445 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 446 }; 447 448 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 449 PLATFORM_CORE_COUNT, 450 ls_interrupt_props, 451 ARRAY_SIZE(ls_interrupt_props), 452 target_mask_array, 453 plat_core_pos); 454 455 plat_ls_gic_init(); 456 enable_init_timer(); 457 #ifdef LS_SYS_TIMCTL_BASE 458 ls_configure_sys_timer(LS_SYS_TIMCTL_BASE, 459 LS_CONFIG_CNTACR, 460 PLAT_LS_NSTIMER_FRAME_ID); 461 #endif 462 } 463 464 /******************************************************************************* 465 * This function initializes the soc from the BL31 module 466 ******************************************************************************/ 467 void soc_init(void) 468 { 469 /* low-level init of the soc */ 470 soc_init_start(); 471 soc_init_percpu(); 472 _init_global_data(); 473 _initialize_psci(); 474 475 if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) { 476 ERROR("Unrecognized CCN variant detected."); 477 ERROR("Only CCN-508 is supported\n"); 478 panic(); 479 } 480 481 uint32_t num_clusters = get_num_cluster(); 482 483 if (num_clusters == 6U) { 484 ccn_init(&plat_six_cluster_ccn_desc); 485 } else { 486 ccn_init(&plat_ccn_desc); 487 } 488 489 plat_ls_interconnect_enter_coherency(num_clusters); 490 491 /* Set platform security policies */ 492 _set_platform_security(); 493 494 /* make sure any parallel init tasks are finished */ 495 soc_init_finish(); 496 497 /* Initialize the crypto accelerator if enabled */ 498 if (is_sec_enabled() == false) { 499 INFO("SEC is disabled.\n"); 500 } else { 501 sec_init(NXP_CAAM_ADDR); 502 } 503 504 } 505 506 #ifdef NXP_WDOG_RESTART 507 static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, 508 void *handle, void *cookie) 509 { 510 uint8_t data = WDOG_RESET_FLAG; 511 512 wr_nv_app_data(WDT_RESET_FLAG_OFFSET, 513 (uint8_t *)&data, sizeof(data)); 514 515 mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); 516 517 return 0; 518 } 519 #endif 520 521 void soc_runtime_setup(void) 522 { 523 524 #ifdef NXP_WDOG_RESTART 525 request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); 526 #endif 527 } 528 #endif 529