1# 2# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include plat/renesas/common/common.mk 8 9ifndef LSI 10 $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI") 11else 12 ifeq (${LSI},AUTO) 13 RCAR_LSI:=${RCAR_AUTO} 14 else ifeq (${LSI},G2M) 15 RCAR_LSI:=${RZ_G2M} 16 ifndef LSI_CUT 17 # enable compatible function. 18 RCAR_LSI_CUT_COMPAT := 1 19 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 20 else 21 # disable compatible function. 22 ifeq (${LSI_CUT},10) 23 RCAR_LSI_CUT:=0 24 else ifeq (${LSI_CUT},11) 25 RCAR_LSI_CUT:=1 26 else ifeq (${LSI_CUT},13) 27 RCAR_LSI_CUT:=3 28 else ifeq (${LSI_CUT},30) 29 RCAR_LSI_CUT:=20 30 else 31 $(error "Error: ${LSI_CUT} is not supported.") 32 endif 33 $(eval $(call add_define,RCAR_LSI_CUT)) 34 endif 35 else 36 $(error "Error: ${LSI} is not supported.") 37 endif 38 $(eval $(call add_define,RCAR_LSI)) 39endif 40 41# Process RZG_LCS_STATE_DETECTION_ENABLE flag 42# Enable to get LCS state information 43ifndef RZG_LCS_STATE_DETECTION_ENABLE 44RZG_LCS_STATE_DETECTION_ENABLE := 0 45endif 46$(eval $(call add_define,RZG_LCS_STATE_DETECTION_ENABLE)) 47 48# Process RCAR_SECURE_BOOT flag 49ifndef RCAR_SECURE_BOOT 50RCAR_SECURE_BOOT := 0 51endif 52$(eval $(call add_define,RCAR_SECURE_BOOT)) 53 54# LCS state of RZ/G2 Chip is all CM. 55# However certain chips(RZ/G2M and RZ/G2E) have incorrect factory Fuse settings 56# which results in getting incorrect LCS states 57# if need to enable RCAR_SECURE_BOOT, make sure the chip has proper factory Fuse settings. 58ifeq (${RCAR_SECURE_BOOT},1) 59 ifeq (${RZG_LCS_STATE_DETECTION_ENABLE},0) 60 $(error "Error: Please check the chip has proper factory Fuse settings and set RZG_LCS_STATE_DETECTION_ENABLE to enable.") 61 endif 62endif 63 64# lock RPC HYPERFLASH access by default 65# unlock to repogram the ATF firmware from u-boot 66ifndef RCAR_RPC_HYPERFLASH_LOCKED 67RCAR_RPC_HYPERFLASH_LOCKED := 1 68endif 69$(eval $(call add_define,RCAR_RPC_HYPERFLASH_LOCKED)) 70 71# Process RCAR_QOS_TYPE flag 72ifndef RCAR_QOS_TYPE 73RCAR_QOS_TYPE := 0 74endif 75$(eval $(call add_define,RCAR_QOS_TYPE)) 76 77# Process RCAR_DRAM_SPLIT flag 78ifndef RCAR_DRAM_SPLIT 79RCAR_DRAM_SPLIT := 0 80endif 81$(eval $(call add_define,RCAR_DRAM_SPLIT)) 82 83# Process RCAR_BL33_EXECUTION_EL flag 84ifndef RCAR_BL33_EXECUTION_EL 85RCAR_BL33_EXECUTION_EL := 0 86endif 87$(eval $(call add_define,RCAR_BL33_EXECUTION_EL)) 88 89# Process RCAR_AVS_SETTING_ENABLE flag 90ifndef AVS_SETTING_ENABLE 91AVS_SETTING_ENABLE := 0 92endif 93$(eval $(call add_define,AVS_SETTING_ENABLE)) 94 95# Process RCAR_LOSSY_ENABLE flag 96ifndef RCAR_LOSSY_ENABLE 97RCAR_LOSSY_ENABLE := 0 98endif 99$(eval $(call add_define,RCAR_LOSSY_ENABLE)) 100 101# Process LIFEC_DBSC_PROTECT_ENABLE flag 102ifndef LIFEC_DBSC_PROTECT_ENABLE 103LIFEC_DBSC_PROTECT_ENABLE := 1 104endif 105$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE)) 106 107# Process RCAR_GEN3_ULCB flag 108ifndef RCAR_GEN3_ULCB 109RCAR_GEN3_ULCB := 0 110endif 111 112# Process RCAR_REF_INT flag 113ifndef RCAR_REF_INT 114RCAR_REF_INT :=0 115endif 116$(eval $(call add_define,RCAR_REF_INT)) 117 118# Process RCAR_REWT_TRAINING flag 119ifndef RCAR_REWT_TRAINING 120RCAR_REWT_TRAINING := 1 121endif 122$(eval $(call add_define,RCAR_REWT_TRAINING)) 123 124# Process RCAR_SYSTEM_SUSPEND flag 125ifndef RCAR_SYSTEM_SUSPEND 126RCAR_SYSTEM_SUSPEND := 0 127endif 128$(eval $(call add_define,RCAR_SYSTEM_SUSPEND)) 129 130# Process RCAR_DRAM_LPDDR4_MEMCONF flag 131ifndef RCAR_DRAM_LPDDR4_MEMCONF 132RCAR_DRAM_LPDDR4_MEMCONF :=1 133endif 134$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF)) 135 136# Process RCAR_DRAM_DDR3L_MEMCONF flag 137ifndef RCAR_DRAM_DDR3L_MEMCONF 138RCAR_DRAM_DDR3L_MEMCONF :=1 139endif 140$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMCONF)) 141 142# Process RCAR_DRAM_DDR3L_MEMDUAL flag 143ifndef RCAR_DRAM_DDR3L_MEMDUAL 144RCAR_DRAM_DDR3L_MEMDUAL :=1 145endif 146$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMDUAL)) 147 148# Process RCAR_BL33_ARG0 flag 149ifdef RCAR_BL33_ARG0 150$(eval $(call add_define,RCAR_BL33_ARG0)) 151endif 152 153#Process RCAR_BL2_DCACHE flag 154ifndef RCAR_BL2_DCACHE 155RCAR_BL2_DCACHE := 0 156endif 157$(eval $(call add_define,RCAR_BL2_DCACHE)) 158 159# Process RCAR_DRAM_CHANNEL flag 160ifndef RCAR_DRAM_CHANNEL 161RCAR_DRAM_CHANNEL :=15 162endif 163$(eval $(call add_define,RCAR_DRAM_CHANNEL)) 164 165#Process RCAR_SYSTEM_RESET_KEEPON_DDR flag 166ifndef RCAR_SYSTEM_RESET_KEEPON_DDR 167RCAR_SYSTEM_RESET_KEEPON_DDR := 0 168endif 169$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR)) 170 171RZG_SOC :=1 172$(eval $(call add_define,RZG_SOC)) 173 174include drivers/renesas/common/ddr/ddr.mk 175include drivers/renesas/rzg/qos/qos.mk 176include drivers/renesas/rzg/pfc/pfc.mk 177include lib/libfdt/libfdt.mk 178 179PLAT_INCLUDES += -Idrivers/renesas/common/ddr \ 180 -Idrivers/renesas/rzg/qos \ 181 -Idrivers/renesas/rzg/board \ 182 -Idrivers/renesas/common \ 183 -Idrivers/renesas/common/iic_dvfs \ 184 -Idrivers/renesas/common/avs \ 185 -Idrivers/renesas/common/delay \ 186 -Idrivers/renesas/common/rom \ 187 -Idrivers/renesas/common/scif \ 188 -Idrivers/renesas/common/emmc \ 189 -Idrivers/renesas/common/pwrc \ 190 -Idrivers/renesas/common/io 191 192BL2_SOURCES += plat/renesas/rzg/bl2_plat_setup.c \ 193 drivers/renesas/rzg/board/board.c 194 195# build the layout images for the bootrom and the necessary srecords 196rzg: rzg_layout_create rzg_srecord 197distclean realclean clean: clean_layout_tool clean_srecord 198 199# layout images 200LAYOUT_TOOLPATH ?= tools/renesas/rzg_layout_create 201 202clean_layout_tool: 203 @echo "clean layout tool" 204 ${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean 205 206.PHONY: rzg_layout_create 207rzg_layout_create: 208 @echo "generating layout srecs" 209 ${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH} 210 211# srecords 212SREC_PATH = ${BUILD_PLAT} 213BL2_ELF_SRC = ${SREC_PATH}/bl2/bl2.elf 214BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf 215 216clean_srecord: 217 @echo "clean bl2 and bl31 srecs" 218 rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec 219 220.PHONY: rzg_srecord 221rzg_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC) 222 @echo "generating srec: ${SREC_PATH}/bl2.srec" 223 $(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec 224 @echo "generating srec: ${SREC_PATH}/bl31.srec" 225 $(Q)$(OC) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec 226