1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <sunxi_mmap.h> 15 16 /* The SCP firmware is allocated the last 16KiB of SRAM A2. */ 17 #define SUNXI_SCP_SIZE 0x4000 18 19 #ifdef SUNXI_BL31_IN_DRAM 20 21 #define BL31_BASE SUNXI_DRAM_BASE 22 #define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000) 23 24 #define MAX_XLAT_TABLES 4 25 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 26 27 #define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE 28 29 #else /* !SUNXI_BL31_IN_DRAM */ 30 31 #define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) 32 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ 33 SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) 34 #define SUNXI_SCP_BASE BL31_LIMIT 35 36 /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ 37 #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) 38 #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) 39 40 #define MAX_XLAT_TABLES 1 41 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 42 #define SUNXI_BL33_VIRT_BASE (SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE) 43 44 #endif /* SUNXI_BL31_IN_DRAM */ 45 46 /* How much memory to reserve as secure for BL32, if configured */ 47 #define SUNXI_DRAM_SEC_SIZE (32U << 20) 48 49 /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 50 #define SUNXI_DRAM_MAP_SIZE (64U << 20) 51 52 #define CACHE_WRITEBACK_SHIFT 6 53 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 54 55 #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 56 57 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ 58 (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) 59 60 #define PLAT_MAX_PWR_LVL_STATES U(2) 61 #define PLAT_MAX_RET_STATE U(1) 62 #define PLAT_MAX_OFF_STATE U(2) 63 64 #define PLAT_MAX_PWR_LVL U(2) 65 #define PLAT_NUM_PWR_DOMAINS (U(1) + \ 66 PLATFORM_CLUSTER_COUNT + \ 67 PLATFORM_CORE_COUNT) 68 69 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 70 71 #define PLATFORM_CLUSTER_COUNT U(1) 72 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 73 PLATFORM_MAX_CPUS_PER_CLUSTER) 74 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 75 #define PLATFORM_MMAP_REGIONS 5 76 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 77 78 #ifndef SPD_none 79 #ifndef BL32_BASE 80 #define BL32_BASE SUNXI_DRAM_BASE 81 #endif 82 #endif 83 84 #endif /* PLATFORM_DEF_H */ 85