1# 2# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include plat/renesas/common/common.mk 8 9ifndef LSI 10 $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI") 11else 12 ifeq (${LSI},AUTO) 13 RCAR_LSI:=${RCAR_AUTO} 14 else ifeq (${LSI},G2M) 15 RCAR_LSI:=${RZ_G2M} 16 ifndef LSI_CUT 17 # enable compatible function. 18 RCAR_LSI_CUT_COMPAT := 1 19 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 20 else 21 # disable compatible function. 22 ifeq (${LSI_CUT},10) 23 RCAR_LSI_CUT:=0 24 else ifeq (${LSI_CUT},11) 25 RCAR_LSI_CUT:=1 26 else ifeq (${LSI_CUT},13) 27 RCAR_LSI_CUT:=3 28 else ifeq (${LSI_CUT},30) 29 RCAR_LSI_CUT:=20 30 else 31 $(error "Error: ${LSI_CUT} is not supported.") 32 endif 33 $(eval $(call add_define,RCAR_LSI_CUT)) 34 endif 35 else ifeq (${LSI},G2H) 36 RCAR_LSI:=${RZ_G2H} 37 ifndef LSI_CUT 38 # enable compatible function. 39 RCAR_LSI_CUT_COMPAT := 1 40 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 41 else 42 # disable compatible function. 43 ifeq (${LSI_CUT},30) 44 RCAR_LSI_CUT:=20 45 else 46 $(error "Error: ${LSI_CUT} is not supported.") 47 endif 48 $(eval $(call add_define,RCAR_LSI_CUT)) 49 endif 50 else ifeq (${LSI},G2N) 51 RCAR_LSI:=${RZ_G2N} 52 ifndef LSI_CUT 53 # enable compatible function. 54 RCAR_LSI_CUT_COMPAT := 1 55 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 56 else 57 # disable compatible function. 58 ifeq (${LSI_CUT},10) 59 RCAR_LSI_CUT:=0 60 else ifeq (${LSI_CUT},11) 61 RCAR_LSI_CUT:=1 62 else 63 $(error "Error: ${LSI_CUT} is not supported.") 64 endif 65 $(eval $(call add_define,RCAR_LSI_CUT)) 66 endif 67 else 68 $(error "Error: ${LSI} is not supported.") 69 endif 70 $(eval $(call add_define,RCAR_LSI)) 71endif 72 73# Process RZG_LCS_STATE_DETECTION_ENABLE flag 74# Enable to get LCS state information 75ifndef RZG_LCS_STATE_DETECTION_ENABLE 76RZG_LCS_STATE_DETECTION_ENABLE := 0 77endif 78$(eval $(call add_define,RZG_LCS_STATE_DETECTION_ENABLE)) 79 80# Process RCAR_SECURE_BOOT flag 81ifndef RCAR_SECURE_BOOT 82RCAR_SECURE_BOOT := 0 83endif 84$(eval $(call add_define,RCAR_SECURE_BOOT)) 85 86# LCS state of RZ/G2 Chip is all CM. 87# However certain chips(RZ/G2M and RZ/G2E) have incorrect factory Fuse settings 88# which results in getting incorrect LCS states 89# if need to enable RCAR_SECURE_BOOT, make sure the chip has proper factory Fuse settings. 90ifeq (${RCAR_SECURE_BOOT},1) 91 ifeq (${RZG_LCS_STATE_DETECTION_ENABLE},0) 92 $(error "Error: Please check the chip has proper factory Fuse settings and set RZG_LCS_STATE_DETECTION_ENABLE to enable.") 93 endif 94endif 95 96# lock RPC HYPERFLASH access by default 97# unlock to repogram the ATF firmware from u-boot 98ifndef RCAR_RPC_HYPERFLASH_LOCKED 99RCAR_RPC_HYPERFLASH_LOCKED := 1 100endif 101$(eval $(call add_define,RCAR_RPC_HYPERFLASH_LOCKED)) 102 103# Process RCAR_QOS_TYPE flag 104ifndef RCAR_QOS_TYPE 105RCAR_QOS_TYPE := 0 106endif 107$(eval $(call add_define,RCAR_QOS_TYPE)) 108 109# Process RCAR_DRAM_SPLIT flag 110ifndef RCAR_DRAM_SPLIT 111RCAR_DRAM_SPLIT := 0 112endif 113$(eval $(call add_define,RCAR_DRAM_SPLIT)) 114 115# Process RCAR_BL33_EXECUTION_EL flag 116ifndef RCAR_BL33_EXECUTION_EL 117RCAR_BL33_EXECUTION_EL := 0 118endif 119$(eval $(call add_define,RCAR_BL33_EXECUTION_EL)) 120 121# Process RCAR_AVS_SETTING_ENABLE flag 122ifndef AVS_SETTING_ENABLE 123AVS_SETTING_ENABLE := 0 124endif 125$(eval $(call add_define,AVS_SETTING_ENABLE)) 126 127# Process RCAR_LOSSY_ENABLE flag 128ifndef RCAR_LOSSY_ENABLE 129RCAR_LOSSY_ENABLE := 0 130endif 131$(eval $(call add_define,RCAR_LOSSY_ENABLE)) 132 133# Process LIFEC_DBSC_PROTECT_ENABLE flag 134ifndef LIFEC_DBSC_PROTECT_ENABLE 135LIFEC_DBSC_PROTECT_ENABLE := 1 136endif 137$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE)) 138 139# Process RCAR_GEN3_ULCB flag 140ifndef RCAR_GEN3_ULCB 141RCAR_GEN3_ULCB := 0 142endif 143 144# Process RCAR_REF_INT flag 145ifndef RCAR_REF_INT 146RCAR_REF_INT :=0 147endif 148$(eval $(call add_define,RCAR_REF_INT)) 149 150# Process RCAR_REWT_TRAINING flag 151ifndef RCAR_REWT_TRAINING 152RCAR_REWT_TRAINING := 1 153endif 154$(eval $(call add_define,RCAR_REWT_TRAINING)) 155 156# Process RCAR_SYSTEM_SUSPEND flag 157ifndef RCAR_SYSTEM_SUSPEND 158RCAR_SYSTEM_SUSPEND := 0 159endif 160$(eval $(call add_define,RCAR_SYSTEM_SUSPEND)) 161 162# Process RCAR_DRAM_LPDDR4_MEMCONF flag 163ifndef RCAR_DRAM_LPDDR4_MEMCONF 164RCAR_DRAM_LPDDR4_MEMCONF :=1 165endif 166$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF)) 167 168# Process RCAR_DRAM_DDR3L_MEMCONF flag 169ifndef RCAR_DRAM_DDR3L_MEMCONF 170RCAR_DRAM_DDR3L_MEMCONF :=1 171endif 172$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMCONF)) 173 174# Process RCAR_DRAM_DDR3L_MEMDUAL flag 175ifndef RCAR_DRAM_DDR3L_MEMDUAL 176RCAR_DRAM_DDR3L_MEMDUAL :=1 177endif 178$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMDUAL)) 179 180# Process RCAR_BL33_ARG0 flag 181ifdef RCAR_BL33_ARG0 182$(eval $(call add_define,RCAR_BL33_ARG0)) 183endif 184 185#Process RCAR_BL2_DCACHE flag 186ifndef RCAR_BL2_DCACHE 187RCAR_BL2_DCACHE := 0 188endif 189$(eval $(call add_define,RCAR_BL2_DCACHE)) 190 191# Process RCAR_DRAM_CHANNEL flag 192ifndef RCAR_DRAM_CHANNEL 193RCAR_DRAM_CHANNEL :=15 194endif 195$(eval $(call add_define,RCAR_DRAM_CHANNEL)) 196 197#Process RCAR_SYSTEM_RESET_KEEPON_DDR flag 198ifndef RCAR_SYSTEM_RESET_KEEPON_DDR 199RCAR_SYSTEM_RESET_KEEPON_DDR := 0 200endif 201$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR)) 202 203RZG_SOC :=1 204$(eval $(call add_define,RZG_SOC)) 205 206include drivers/renesas/common/ddr/ddr.mk 207include drivers/renesas/rzg/qos/qos.mk 208include drivers/renesas/rzg/pfc/pfc.mk 209include lib/libfdt/libfdt.mk 210 211PLAT_INCLUDES += -Idrivers/renesas/common/ddr \ 212 -Idrivers/renesas/rzg/qos \ 213 -Idrivers/renesas/rzg/board \ 214 -Idrivers/renesas/common \ 215 -Idrivers/renesas/common/iic_dvfs \ 216 -Idrivers/renesas/common/avs \ 217 -Idrivers/renesas/common/delay \ 218 -Idrivers/renesas/common/rom \ 219 -Idrivers/renesas/common/scif \ 220 -Idrivers/renesas/common/emmc \ 221 -Idrivers/renesas/common/pwrc \ 222 -Idrivers/renesas/common/io 223 224BL2_SOURCES += plat/renesas/rzg/bl2_plat_setup.c \ 225 drivers/renesas/rzg/board/board.c 226 227# build the layout images for the bootrom and the necessary srecords 228rzg: rzg_layout_create rzg_srecord 229distclean realclean clean: clean_layout_tool clean_srecord 230 231# layout images 232LAYOUT_TOOLPATH ?= tools/renesas/rzg_layout_create 233 234clean_layout_tool: 235 @echo "clean layout tool" 236 ${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean 237 238.PHONY: rzg_layout_create 239rzg_layout_create: 240 @echo "generating layout srecs" 241 ${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH} 242 243# srecords 244SREC_PATH = ${BUILD_PLAT} 245BL2_ELF_SRC = ${SREC_PATH}/bl2/bl2.elf 246BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf 247 248clean_srecord: 249 @echo "clean bl2 and bl31 srecs" 250 rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec 251 252.PHONY: rzg_srecord 253rzg_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC) 254 @echo "generating srec: ${SREC_PATH}/bl2.srec" 255 $(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec 256 @echo "generating srec: ${SREC_PATH}/bl31.srec" 257 $(Q)$(OC) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec 258