1# 2# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include plat/renesas/common/common.mk 8 9ifndef LSI 10 $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI") 11else 12 ifeq (${LSI},AUTO) 13 RCAR_LSI:=${RCAR_AUTO} 14 else ifeq (${LSI},G2M) 15 RCAR_LSI:=${RZ_G2M} 16 ifndef LSI_CUT 17 # enable compatible function. 18 RCAR_LSI_CUT_COMPAT := 1 19 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 20 else 21 # disable compatible function. 22 ifeq (${LSI_CUT},10) 23 RCAR_LSI_CUT:=0 24 else ifeq (${LSI_CUT},11) 25 RCAR_LSI_CUT:=1 26 else ifeq (${LSI_CUT},13) 27 RCAR_LSI_CUT:=3 28 else ifeq (${LSI_CUT},30) 29 RCAR_LSI_CUT:=20 30 else 31 $(error "Error: ${LSI_CUT} is not supported.") 32 endif 33 $(eval $(call add_define,RCAR_LSI_CUT)) 34 endif 35 else ifeq (${LSI},G2H) 36 RCAR_LSI:=${RZ_G2H} 37 ifndef LSI_CUT 38 # enable compatible function. 39 RCAR_LSI_CUT_COMPAT := 1 40 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 41 else 42 # disable compatible function. 43 ifeq (${LSI_CUT},30) 44 RCAR_LSI_CUT:=20 45 else 46 $(error "Error: ${LSI_CUT} is not supported.") 47 endif 48 $(eval $(call add_define,RCAR_LSI_CUT)) 49 endif 50 else 51 $(error "Error: ${LSI} is not supported.") 52 endif 53 $(eval $(call add_define,RCAR_LSI)) 54endif 55 56# Process RZG_LCS_STATE_DETECTION_ENABLE flag 57# Enable to get LCS state information 58ifndef RZG_LCS_STATE_DETECTION_ENABLE 59RZG_LCS_STATE_DETECTION_ENABLE := 0 60endif 61$(eval $(call add_define,RZG_LCS_STATE_DETECTION_ENABLE)) 62 63# Process RCAR_SECURE_BOOT flag 64ifndef RCAR_SECURE_BOOT 65RCAR_SECURE_BOOT := 0 66endif 67$(eval $(call add_define,RCAR_SECURE_BOOT)) 68 69# LCS state of RZ/G2 Chip is all CM. 70# However certain chips(RZ/G2M and RZ/G2E) have incorrect factory Fuse settings 71# which results in getting incorrect LCS states 72# if need to enable RCAR_SECURE_BOOT, make sure the chip has proper factory Fuse settings. 73ifeq (${RCAR_SECURE_BOOT},1) 74 ifeq (${RZG_LCS_STATE_DETECTION_ENABLE},0) 75 $(error "Error: Please check the chip has proper factory Fuse settings and set RZG_LCS_STATE_DETECTION_ENABLE to enable.") 76 endif 77endif 78 79# lock RPC HYPERFLASH access by default 80# unlock to repogram the ATF firmware from u-boot 81ifndef RCAR_RPC_HYPERFLASH_LOCKED 82RCAR_RPC_HYPERFLASH_LOCKED := 1 83endif 84$(eval $(call add_define,RCAR_RPC_HYPERFLASH_LOCKED)) 85 86# Process RCAR_QOS_TYPE flag 87ifndef RCAR_QOS_TYPE 88RCAR_QOS_TYPE := 0 89endif 90$(eval $(call add_define,RCAR_QOS_TYPE)) 91 92# Process RCAR_DRAM_SPLIT flag 93ifndef RCAR_DRAM_SPLIT 94RCAR_DRAM_SPLIT := 0 95endif 96$(eval $(call add_define,RCAR_DRAM_SPLIT)) 97 98# Process RCAR_BL33_EXECUTION_EL flag 99ifndef RCAR_BL33_EXECUTION_EL 100RCAR_BL33_EXECUTION_EL := 0 101endif 102$(eval $(call add_define,RCAR_BL33_EXECUTION_EL)) 103 104# Process RCAR_AVS_SETTING_ENABLE flag 105ifndef AVS_SETTING_ENABLE 106AVS_SETTING_ENABLE := 0 107endif 108$(eval $(call add_define,AVS_SETTING_ENABLE)) 109 110# Process RCAR_LOSSY_ENABLE flag 111ifndef RCAR_LOSSY_ENABLE 112RCAR_LOSSY_ENABLE := 0 113endif 114$(eval $(call add_define,RCAR_LOSSY_ENABLE)) 115 116# Process LIFEC_DBSC_PROTECT_ENABLE flag 117ifndef LIFEC_DBSC_PROTECT_ENABLE 118LIFEC_DBSC_PROTECT_ENABLE := 1 119endif 120$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE)) 121 122# Process RCAR_GEN3_ULCB flag 123ifndef RCAR_GEN3_ULCB 124RCAR_GEN3_ULCB := 0 125endif 126 127# Process RCAR_REF_INT flag 128ifndef RCAR_REF_INT 129RCAR_REF_INT :=0 130endif 131$(eval $(call add_define,RCAR_REF_INT)) 132 133# Process RCAR_REWT_TRAINING flag 134ifndef RCAR_REWT_TRAINING 135RCAR_REWT_TRAINING := 1 136endif 137$(eval $(call add_define,RCAR_REWT_TRAINING)) 138 139# Process RCAR_SYSTEM_SUSPEND flag 140ifndef RCAR_SYSTEM_SUSPEND 141RCAR_SYSTEM_SUSPEND := 0 142endif 143$(eval $(call add_define,RCAR_SYSTEM_SUSPEND)) 144 145# Process RCAR_DRAM_LPDDR4_MEMCONF flag 146ifndef RCAR_DRAM_LPDDR4_MEMCONF 147RCAR_DRAM_LPDDR4_MEMCONF :=1 148endif 149$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF)) 150 151# Process RCAR_DRAM_DDR3L_MEMCONF flag 152ifndef RCAR_DRAM_DDR3L_MEMCONF 153RCAR_DRAM_DDR3L_MEMCONF :=1 154endif 155$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMCONF)) 156 157# Process RCAR_DRAM_DDR3L_MEMDUAL flag 158ifndef RCAR_DRAM_DDR3L_MEMDUAL 159RCAR_DRAM_DDR3L_MEMDUAL :=1 160endif 161$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMDUAL)) 162 163# Process RCAR_BL33_ARG0 flag 164ifdef RCAR_BL33_ARG0 165$(eval $(call add_define,RCAR_BL33_ARG0)) 166endif 167 168#Process RCAR_BL2_DCACHE flag 169ifndef RCAR_BL2_DCACHE 170RCAR_BL2_DCACHE := 0 171endif 172$(eval $(call add_define,RCAR_BL2_DCACHE)) 173 174# Process RCAR_DRAM_CHANNEL flag 175ifndef RCAR_DRAM_CHANNEL 176RCAR_DRAM_CHANNEL :=15 177endif 178$(eval $(call add_define,RCAR_DRAM_CHANNEL)) 179 180#Process RCAR_SYSTEM_RESET_KEEPON_DDR flag 181ifndef RCAR_SYSTEM_RESET_KEEPON_DDR 182RCAR_SYSTEM_RESET_KEEPON_DDR := 0 183endif 184$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR)) 185 186RZG_SOC :=1 187$(eval $(call add_define,RZG_SOC)) 188 189include drivers/renesas/common/ddr/ddr.mk 190include drivers/renesas/rzg/qos/qos.mk 191include drivers/renesas/rzg/pfc/pfc.mk 192include lib/libfdt/libfdt.mk 193 194PLAT_INCLUDES += -Idrivers/renesas/common/ddr \ 195 -Idrivers/renesas/rzg/qos \ 196 -Idrivers/renesas/rzg/board \ 197 -Idrivers/renesas/common \ 198 -Idrivers/renesas/common/iic_dvfs \ 199 -Idrivers/renesas/common/avs \ 200 -Idrivers/renesas/common/delay \ 201 -Idrivers/renesas/common/rom \ 202 -Idrivers/renesas/common/scif \ 203 -Idrivers/renesas/common/emmc \ 204 -Idrivers/renesas/common/pwrc \ 205 -Idrivers/renesas/common/io 206 207BL2_SOURCES += plat/renesas/rzg/bl2_plat_setup.c \ 208 drivers/renesas/rzg/board/board.c 209 210# build the layout images for the bootrom and the necessary srecords 211rzg: rzg_layout_create rzg_srecord 212distclean realclean clean: clean_layout_tool clean_srecord 213 214# layout images 215LAYOUT_TOOLPATH ?= tools/renesas/rzg_layout_create 216 217clean_layout_tool: 218 @echo "clean layout tool" 219 ${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean 220 221.PHONY: rzg_layout_create 222rzg_layout_create: 223 @echo "generating layout srecs" 224 ${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH} 225 226# srecords 227SREC_PATH = ${BUILD_PLAT} 228BL2_ELF_SRC = ${SREC_PATH}/bl2/bl2.elf 229BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf 230 231clean_srecord: 232 @echo "clean bl2 and bl31 srecs" 233 rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec 234 235.PHONY: rzg_srecord 236rzg_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC) 237 @echo "generating srec: ${SREC_PATH}/bl2.srec" 238 $(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec 239 @echo "generating srec: ${SREC_PATH}/bl31.srec" 240 $(Q)$(OC) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec 241