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Searched refs:reg_val (Results 1 – 25 of 97) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBT/
H A DINTERN_DVBT.c272 U8 reg_val, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
284 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
286 reg_val = MDrv_ReadByte(MBRegBase + 0x1C); in INTERN_DVBT_Cmd_Packet_Send()
288 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
302 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
303 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
304 status &= INTERN_DVBT_WriteReg(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
306 reg_val = MDrv_ReadByte(MBRegBase + 0x1C); in INTERN_DVBT_Cmd_Packet_Send()
307 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
308 MDrv_WriteByte(MBRegBase + 0x1C, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBC/
H A DINTERN_DVBC.c254 U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
265 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
266 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
279 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
280 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
281 status &= INTERN_DVBC_WriteReg(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
287 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
288 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
306 status &= INTERN_DVBC_ReadReg(REG_CMD_ADDR, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
311 status &= INTERN_DVBC_ReadReg(REG_DTA_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBC.c538 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
549 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
550 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
564 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
565 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
566 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
573 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
574 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
593 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
598 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
H A DhalDMD_INTERN_DVBT.c429 MS_U8 reg_val=0, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
441 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
442 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
456 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
457 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
466 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBT_Cmd_Packet_Send()
485 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBT_Cmd_Packet_Send()
490 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBC.c398 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
410 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
434 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBC.c398 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
410 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
434 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
H A DhalDMD_INTERN_DVBT.c429 MS_U8 reg_val=0, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
441 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
442 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
456 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
457 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
466 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBT_Cmd_Packet_Send()
485 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBT_Cmd_Packet_Send()
490 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBC.c399 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
410 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
411 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
426 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
435 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
459 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBC.c398 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
410 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
434 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBC.c399 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
410 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
411 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
426 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
435 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
459 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
H A DhalDMD_INTERN_DVBT.c429 MS_U8 reg_val=0, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
441 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
442 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
456 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
457 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
466 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBT_Cmd_Packet_Send()
485 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBT_Cmd_Packet_Send()
490 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBC.c398 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
410 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
434 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
H A DhalDMD_INTERN_DVBT.c429 MS_U8 reg_val=0, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
441 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
442 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
456 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
457 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
466 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBT_Cmd_Packet_Send()
485 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBT_Cmd_Packet_Send()
490 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBC.c398 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
410 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
434 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/audio/hal/k6lite/audio/
H A Dmbox_decR2.h4 #define RIU_WR_REG8(reg_addr, reg_val) *((volatile unsigned char *)(reg_addr)) = reg_val argument
6 #define RIU_WR_REG16(reg_addr, reg_val) *((volatile unsigned short *)(reg_addr)) = reg_val argument
8 #define RIU_WR_REG32(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = reg_val argument
12 #define DSP_WR_REG24(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = (reg_val&0xFFFFFF) argument
/utopia/UTPA2-700.0.x/modules/audio/hal/curry/audio/
H A Dmbox_decR2.h4 #define RIU_WR_REG8(reg_addr, reg_val) *((volatile unsigned char *)(reg_addr)) = reg_val argument
6 #define RIU_WR_REG16(reg_addr, reg_val) *((volatile unsigned short *)(reg_addr)) = reg_val argument
8 #define RIU_WR_REG32(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = reg_val argument
12 #define DSP_WR_REG24(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = (reg_val&0xFFFFFF) argument
/utopia/UTPA2-700.0.x/modules/audio/hal/kano/audio/
H A Dmbox_decR2.h4 #define RIU_WR_REG8(reg_addr, reg_val) *((volatile unsigned char *)(reg_addr)) = reg_val argument
6 #define RIU_WR_REG16(reg_addr, reg_val) *((volatile unsigned short *)(reg_addr)) = reg_val argument
8 #define RIU_WR_REG32(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = reg_val argument
12 #define DSP_WR_REG24(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = (reg_val&0xFFFFFF) argument
/utopia/UTPA2-700.0.x/modules/audio/hal/k6/audio/
H A Dmbox_decR2.h4 #define RIU_WR_REG8(reg_addr, reg_val) *((volatile unsigned char *)(reg_addr)) = reg_val argument
6 #define RIU_WR_REG16(reg_addr, reg_val) *((volatile unsigned short *)(reg_addr)) = reg_val argument
8 #define RIU_WR_REG32(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = reg_val argument
12 #define DSP_WR_REG24(reg_addr, reg_val) *((volatile unsigned int *)(reg_addr)) = (reg_val&0xFFFFFF) argument
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBC.c398 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
410 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
434 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
H A DhalDMD_INTERN_DVBT.c428 MS_U8 reg_val=0, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
440 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
441 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
455 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
456 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
457 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
464 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
465 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBT_Cmd_Packet_Send()
484 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBT_Cmd_Packet_Send()
489 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBC.c399 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
410 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
411 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
426 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
435 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
459 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
H A DhalDMD_INTERN_DVBT.c418 MS_U8 reg_val=0, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
430 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
431 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
445 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
446 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
447 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
455 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBT_Cmd_Packet_Send()
474 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBT_Cmd_Packet_Send()
479 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBC.c410 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
421 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
422 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
436 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
437 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
438 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
445 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
446 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
470 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBC.c408 MS_U8 reg_val, timeout = 0; in INTERN_DVBC_Cmd_Packet_Send() local
419 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
420 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBC_Cmd_Packet_Send()
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
435 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBC_Cmd_Packet_Send()
436 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
443 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
444 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBC_Cmd_Packet_Send()
463 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
468 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
[all …]
H A DhalDMD_INTERN_DVBT.c417 MS_U8 reg_val=0, timeout = 0; in INTERN_DVBT_Cmd_Packet_Send() local
429 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
430 if((reg_val & _BIT_END) != _BIT_END) in INTERN_DVBT_Cmd_Packet_Send()
444 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
445 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START; in INTERN_DVBT_Cmd_Packet_Send()
446 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
454 if((reg_val & _BIT_START) != _BIT_START) in INTERN_DVBT_Cmd_Packet_Send()
473 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBT_Cmd_Packet_Send()
478 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBT_Cmd_Packet_Send()
[all …]

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