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93 ////////////////////////////////////////////////////////////////////////////////
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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #define TEST_EMBEDED_DEMOD 0
129 //U8 load_data_variable=1;
130 //-----------------------------------------------------------------------
131 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
132
133 #define TDE_REG_BASE 0x2400UL
134 #define DIV_REG_BASE 0x2500UL
135 #define TR_REG_BASE 0x2600UL
136 #define FTN_REG_BASE 0x2700UL
137 #define FTNEXT_REG_BASE 0x2800UL
138
139
140
141 #if 0//ENABLE_SCAN_ONELINE_MSG
142 #define DBG_INTERN_DVBT_ONELINE(x) x
143 #else
144 #define DBG_INTERN_DVBT_ONELINE(x) // x
145 #endif
146
147 #ifdef MS_DEBUG
148 #define DBG_INTERN_DVBT(x) x
149 #define DBG_GET_SIGNAL(x) x
150 #define DBG_INTERN_DVBT_TIME(x) x
151 #define DBG_INTERN_DVBT_LOCK(x) x
152 #else
153 #define DBG_INTERN_DVBT(x) //x
154 #define DBG_GET_SIGNAL(x) //x
155 #define DBG_INTERN_DVBT_TIME(x) // x
156 #define DBG_INTERN_DVBT_LOCK(x) //x
157 #endif
158 #define DBG_DUMP_LOAD_DSP_TIME 0
159
160 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
161 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
162 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
163 #define INTERN_DVBT_INTERNAL_DEBUG 1
164
165 #define SIGNAL_LEVEL_OFFSET 0.00
166 #define TAKEOVERPOINT -59.0
167 #define TAKEOVERRANGE 0.5
168 #define LOG10_OFFSET -0.21
169 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
170 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
171
172
173 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
174 #define TUNER_VPP 2
175 #define IF_AGC_VPP 2
176 #else
177 #define TUNER_VPP 1
178 #define IF_AGC_VPP 2
179 #endif
180
181 #if (TUNER_VPP == 1)
182 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
183 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
185 #endif
186
187 /*BEG INTERN_DVBT_DSPREG_TABLE*/
188 #define D_DMD_DVBT_PARAM_VERSION 0x01
189 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
190 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
191 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
192 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
193 #define D_DMD_DVBT_OP_DCR_EN 0x01
194 #define D_DMD_DVBT_OP_IIS_EN 0x01
195 #define D_DMD_DVBT_OP_IQB_EN 0x00
196 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
197 #define D_DMD_DVBT_OP_ACI_EN 0x01
198 #define D_DMD_DVBT_OP_CCI_EN 0x01
199 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
200 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
201 #define D_DMD_DVBT_CFG_BW 0x00 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
202 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
203 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
204 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
205 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
206 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
207 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
208 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
209 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
210 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
211 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
212 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
213 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
214 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
215 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
216 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
217 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
218 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
219 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
220 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
221
222 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
223 #define D_DMD_DVBT_CFG_FC_H 0x4E
224 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
225 #define D_DMD_DVBT_CFG_FS_H 0x5D
226 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
227
228 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
229 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
230 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
231 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
232 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
233 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
234 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
235 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
236 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
237 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
238 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
239 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
240
241 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
242 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
243 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
244 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
245 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
246 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
247 #else
248 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
249 #endif
250 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
251 //#define DMD_DVBT_CHECKSUM 0x00
252 /*END INTERN_DVBT_DSPREG_TABLE*/
253 #define DVBT_FS 45474 // 24000
254 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
255 #define FC_L 0x20 // 0323 jason
256 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
257 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
258 #define SET_ZIF 0x00
259 #define IQB_EN 0x00
260
261 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
262 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
263 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
264 #define CSTL 0x02 //0:QPSK 1:16 2: 64
265 #define HIER 0x00
266 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
267 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
268 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
269 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
270 #define LP_SEL 0x00 // LP select
271 #define IQ_SWAP 0x00 //0x01
272 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
273 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
274 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
275 #define TS_SER 0
276 #define TS_INV 0
277 #define FIF_H (MS_U8)(( (((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))>>8)
278 #define FIF_L (MS_U8)(( ((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))
279 #define IF_INV_PWM 0x00
280 #define T_LOWIF 1
281
282 MS_U8 INTERN_DVBT_DSPREG[] =
283 {
284 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
285 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
286 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
287 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
288 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
289 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
290 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
292 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
293 /*
294 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
295 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
296 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
297 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
298 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
299 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
300 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
301 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
302 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
303 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
304 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
305 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
306 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
307 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
308 */
309 };
310 /*END INTERN_DVBT_DSPREG_TABLE*/
311 //-----------------------------------------------------------------------
312 /****************************************************************
313 *Local Variables *
314 ****************************************************************/
315 static MS_BOOL bFECLock=0;
316 static MS_BOOL bTPSLock = 0;
317 static MS_U32 u32ChkScanTimeStart = 0;
318 static MS_U32 u32FecFirstLockTime=0;
319 static MS_U32 u32FecLastLockTime=0;
320 static float fViterbiBerFiltered=-1;
321 //Global Variables
322 S_CMDPKTREG gsCmdPacket;
323 //U8 gCalIdacCh0, gCalIdacCh1;
324
325 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
326 MS_U8 INTERN_DVBT_table[] = {
327 #include "fwDMD_INTERN_DVBT.dat"
328 };
329
330 #endif
331
332 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
333 {
334 { _QPSK , _CR1Y2, -93},
335 { _QPSK , _CR2Y3, -91},
336 { _QPSK , _CR3Y4, -90},
337 { _QPSK , _CR5Y6, -89},
338 { _QPSK , _CR7Y8, -88},
339
340 { _16QAM , _CR1Y2, -87},
341 { _16QAM , _CR2Y3, -85},
342 { _16QAM , _CR3Y4, -84},
343 { _16QAM , _CR5Y6, -83},
344 { _16QAM , _CR7Y8, -82},
345
346 { _64QAM , _CR1Y2, -82},
347 { _64QAM , _CR2Y3, -80},
348 { _64QAM , _CR3Y4, -78},
349 { _64QAM , _CR5Y6, -77},
350 { _64QAM , _CR7Y8, -76},
351 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
352 };
353
354
355
356 static void INTERN_DVBT_SignalQualityReset(void);
357 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
358
INTERN_DVBT_SignalQualityReset(void)359 static void INTERN_DVBT_SignalQualityReset(void)
360 {
361 u32FecFirstLockTime=0;
362 fViterbiBerFiltered=-1;
363 }
364
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)365 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
366 {
367 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
368 MS_BOOL status = TRUE;
369 MS_U16 u16DspAddr = 0;
370
371 DBG_INTERN_DVBT(printf("INTERN_DVBT_DSPReg_Init\n"));
372
373 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
374 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
375
376 if (u8DVBT_DSPReg != NULL)
377 {
378 /*temp solution until new dsp table applied.*/
379 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
380 if (u8DVBT_DSPReg[0] >= 1)
381 {
382 u8DVBT_DSPReg+=2;
383 for (idx = 0; idx<u8Size; idx++)
384 {
385 u16DspAddr = *u8DVBT_DSPReg;
386 u8DVBT_DSPReg++;
387 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
388 u8DVBT_DSPReg++;
389 u8Mask = *u8DVBT_DSPReg;
390 u8DVBT_DSPReg++;
391 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
392 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
393 u8DVBT_DSPReg++;
394 DBG_INTERN_DVBT(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
395 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
396 }
397 }
398 else
399 {
400 printf("FATAL: parameter version incorrect\n");
401 }
402 }
403
404 return status;
405 }
406
407 /***********************************************************************************
408 Subject: Command Packet Interface
409 Function: INTERN_DVBT_Cmd_Packet_Send
410 Parmeter:
411 Return: MS_BOOL
412 Remark:
413 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)414 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
415 {
416 MS_U8 status = true, indx;
417 MS_U8 reg_val=0, timeout = 0;
418 return TRUE;
419 //MsOS_ObtainMutex(_s32_Demod_DVBT_Mutex, MSOS_WAIT_FOREVER);
420 // ==== Command Phase ===================
421 DBG_INTERN_DVBT(printf("--->INTERN_DVBT (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
422 pCmdPacket->param[0],pCmdPacket->param[1],
423 pCmdPacket->param[2],pCmdPacket->param[3],
424 pCmdPacket->param[4],pCmdPacket->param[5] ));
425
426 // wait _BIT_END clear
427 do
428 {
429 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
430 if((reg_val & _BIT_END) != _BIT_END)
431 {
432 break;
433 }
434 MsOS_DelayTask(5);
435 if (timeout++ > 200)
436 {
437 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
438 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
439 return false;
440 }
441 } while (1);
442
443 // set cmd_3:0 and _BIT_START
444 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
445 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
446 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
447
448
449 //DBG_INTERN_DVBT(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
450 // wait _BIT_START clear
451 do
452 {
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
454 if((reg_val & _BIT_START) != _BIT_START)
455 {
456 break;
457 }
458 MsOS_DelayTask(5);
459 if (timeout++ > 200)
460 {
461 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
462 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
463 return false;
464 }
465 } while (1);
466
467 // ==== Data Phase ======================
468
469 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
470
471 for (indx = 0; indx < param_cnt; indx++)
472 {
473 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
474 //DBG_INTERN_DVBT(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
475
476 // set param[indx] and _BIT_DRQ
477 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
478 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
479 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
480
481 // wait _BIT_DRQ clear
482 do
483 {
484 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
485 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
486 {
487 break;
488 }
489 MsOS_DelayTask(5);
490 if (timeout++ > 200)
491 {
492 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
493 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
494 return false;
495 }
496 } while (1);
497 }
498
499 // ==== End Phase =======================
500
501 // set _BIT_END to finish command
502 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
503 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
504 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
505 return status;
506 }
507
508
509 /***********************************************************************************
510 Subject: Command Packet Interface
511 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
512 Parmeter:
513 Return: MS_BOOL
514 Remark:
515 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)516 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
517 {
518 return TRUE;
519 }
520
521 /***********************************************************************************
522 Subject: SoftStop
523 Function: INTERN_DVBT_SoftStop
524 Parmeter:
525 Return: MS_BOOL
526 Remark:
527 ************************************************************************************/
528
INTERN_DVBT_SoftStop(void)529 MS_BOOL INTERN_DVBT_SoftStop ( void )
530 {
531 #if 1
532 MS_U16 u8WaitCnt=0;
533
534 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
535 {
536 printf(">> MB Busy!\n");
537 return FALSE;
538 }
539
540 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
541
542 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
543 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
544
545 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
546 {
547 #if TEST_EMBEDED_DEMOD
548 MsOS_DelayTask(1); // << Ken 20090629
549 #endif
550 if (u8WaitCnt++ >= 0xFF)
551 {
552 printf(">> DVBT SoftStop Fail!\n");
553 return FALSE;
554 }
555 }
556
557 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
558 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
559 #endif
560 return TRUE;
561 }
562
563
564 /***********************************************************************************
565 Subject: Reset
566 Function: INTERN_DVBT_Reset
567 Parmeter:
568 Return: MS_BOOL
569 Remark:
570 ************************************************************************************/
571 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)572 MS_BOOL INTERN_DVBT_Reset ( void )
573 {
574 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_reset\n"));
575
576 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime()));
577
578 INTERN_DVBT_SoftStop();
579
580
581 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
582 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
583 MsOS_DelayTask(5);
584 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
585 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
586 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
587 MsOS_DelayTask(5);
588
589 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
590 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
591
592 bFECLock = FALSE;
593 bTPSLock = FALSE;
594 u32ChkScanTimeStart = MsOS_GetSystemTime();
595 return TRUE;
596 }
597
598 /***********************************************************************************
599 Subject: Exit
600 Function: INTERN_DVBT_Exit
601 Parmeter:
602 Return: MS_BOOL
603 Remark:
604 ************************************************************************************/
INTERN_DVBT_Exit(void)605 MS_BOOL INTERN_DVBT_Exit ( void )
606 {
607
608 INTERN_DVBT_SoftStop();
609
610
611 //diable clk gen
612 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
613 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
614
615 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
616 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
617
618 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
619 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
620
621 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
622 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
623
624 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
625 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
626
627 HAL_DMD_RIU_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
628 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
629
630 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
631 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
632
633 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
634 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
635
636 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
637 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
638
639 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
640 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
641
642 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
643
644 return TRUE;
645 }
646
647 /***********************************************************************************
648 Subject: Load DSP code to chip
649 Function: INTERN_DVBT_LoadDSPCode
650 Parmeter:
651 Return: MS_BOOL
652 Remark:
653 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)654 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
655 {
656 MS_U8 udata = 0x00;
657 MS_U16 i;
658 MS_U16 fail_cnt=0;
659
660 #if (DBG_DUMP_LOAD_DSP_TIME==1)
661 MS_U32 u32Time;
662 #endif
663
664
665 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
666 BININFO BinInfo;
667 MS_BOOL bResult;
668 MS_U32 u32GEAddr;
669 MS_U8 Data;
670 MS_S8 op;
671 MS_U32 srcaddr;
672 MS_U32 len;
673 MS_U32 SizeBy4K;
674 MS_U16 u16Counter=0;
675 MS_U8 *pU8Data;
676 #endif
677
678 #if 0
679 if(HAL_DMD_RIU_ReadByte(0x101E3E))
680 {
681 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
682 return FALSE;
683 }
684 #endif
685
686 // MDrv_Sys_DisableWatchDog();
687
688
689 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
690 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
691 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
692 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
693 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
694 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
695
696 //// Load code thru VDMCU_IF ////
697 DBG_INTERN_DVBT(printf(">Load Code...\n"));
698 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
699 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
700 {
701 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
702 }
703 #else
704 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
705 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
706 if ( bResult != PASS )
707 {
708 return FALSE;
709 }
710 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
711
712 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
713 InfoBlock_Flash_2_Checking_Start(&BinInfo);
714 #endif
715
716 #if OBA2
717 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
718 #else
719 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
720 #endif
721
722 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
723 InfoBlock_Flash_2_Checking_End(&BinInfo);
724 #endif
725
726 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
727 SizeBy4K=BinInfo.B_Len/0x1000;
728 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
729
730 #if (DBG_DUMP_LOAD_DSP_TIME==1)
731 u32Time = msAPI_Timer_GetTime0();
732 #endif
733
734 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
735
736 for (i=0;i<=SizeBy4K;i++)
737 {
738 if(i==SizeBy4K)
739 len=BinInfo.B_Len%0x1000;
740 else
741 len=0x1000;
742
743 srcaddr = u32GEAddr+(0x1000*i);
744 //printf("\t i = %08X\n", i);
745 //printf("\t len = %08X\n", len);
746 op = 1;
747 u16Counter = 0 ;
748 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
749 while(len--)
750 {
751 u16Counter ++ ;
752 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
753 //pU8Data = (U8 *)(srcaddr|0x80000000);
754 #if OBA2
755 pU8Data = (U8 *)(srcaddr);
756 #else
757 pU8Data = (U8 *)(srcaddr|0x80000000);
758 #endif
759 Data = *pU8Data;
760
761 #if 0
762 if(u16Counter < 0x100)
763 printf("0x%bx,", Data);
764 #endif
765 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
766
767 srcaddr += op;
768 }
769 // printf("\n\n\n");
770 }
771
772 #if (DBG_DUMP_LOAD_DSP_TIME==1)
773 printf("------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
774 #endif
775
776 #endif
777
778 //// Content verification ////
779 DBG_INTERN_DVBT(printf(">Verify Code...\n"));
780
781 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
782 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
783
784 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
785 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
786 {
787 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
788 if (udata != INTERN_DVBT_table[i])
789 {
790 printf(">fail add = 0x%x\n", i);
791 printf(">code = 0x%x\n", INTERN_DVBT_table[i]);
792 printf(">data = 0x%x\n", udata);
793
794 if (fail_cnt++ > 10)
795 {
796 printf(">DVB-T DSP Loadcode fail!");
797 return false;
798 }
799 }
800 }
801 #else
802 for (i=0;i<=SizeBy4K;i++)
803 {
804 if(i==SizeBy4K)
805 len=BinInfo.B_Len%0x1000;
806 else
807 len=0x1000;
808
809 srcaddr = u32GEAddr+(0x1000*i);
810 //printf("\t i = %08LX\n", i);
811 //printf("\t len = %08LX\n", len);
812 op = 1;
813 u16Counter = 0 ;
814 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
815 while(len--)
816 {
817 u16Counter ++ ;
818 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
819 //pU8Data = (U8 *)(srcaddr|0x80000000);
820 #if OBA2
821 pU8Data = (U8 *)(srcaddr);
822 #else
823 pU8Data = (U8 *)(srcaddr|0x80000000);
824 #endif
825 Data = *pU8Data;
826
827 #if 0
828 if(u16Counter < 0x100)
829 printf("0x%bx,", Data);
830 #endif
831 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
832 if (udata != Data)
833 {
834 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
835 printf(">code = 0x%x\n", Data);
836 printf(">data = 0x%x\n", udata);
837
838 if (fail_cnt++ > 10)
839 {
840 printf(">DVB-T DSP Loadcode fail!");
841 return false;
842 }
843 }
844
845 srcaddr += op;
846 }
847 // printf("\n\n\n");
848 }
849 #endif
850
851 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
852 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
853 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
854 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
855
856 DBG_INTERN_DVBT(printf(">DSP Loadcode done."));
857 //while(load_data_variable);
858
859 HAL_DMD_RIU_WriteByte(0x101E3E, 0x02); // DVBT = BIT1 -> 0x02
860
861 return TRUE;
862 }
863
864 /***********************************************************************************
865 Subject: DVB-T CLKGEN initialized function
866 Function: INTERN_DVBT_Power_On_Initialization
867 Parmeter:
868 Return: MS_BOOL
869 Remark:
870 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)871 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
872 {
873 MS_U8 temp_val;
874 MS_U8 udatatemp = 0x00;
875 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
876 // HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
877
878 // Release vivaldi2mi_bridge reset
879 // [0] reg_vivaldi2mi_bridge_rst
880 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
881 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
882 // HAL_DMD_RIU_WriteByte(0x11208E, (HAL_DMD_RIU_ReadByte(0x11208E)&(~(BIT(0)))));
883
884 // ----------------------------------------------
885 // start demod CLKGEN setting
886 // ----------------------------------------------
887 // *** Set register at CLKGEN1
888 // enable DMD MCU clock "bit[0] set 0"
889 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
890 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
891 // CLK_DMDMCU clock setting
892 // [0] disable clock
893 // [1] invert clock
894 // [4:2]
895 // 000:170 MHz(MPLL_DIV_BUf)
896 // 001:160MHz
897 // 010:144MHz
898 // 011:123MHz
899 // 100:108MHz
900 // 101:mem_clcok
901 // 110:mem_clock div 2
902 // 111:select XTAL
903 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
904 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
905
906 // set parallet ts clock
907 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
908 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
909
910 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b
911 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
912 temp_val|=0x07;
913 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
914
915 HAL_DMD_RIU_WriteByte(0x103300,0x17);
916
917 // enable atsc, DVBTC ts clock
918 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
919 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
920 HAL_DMD_RIU_WriteByte(0x103309,0x00);
921 HAL_DMD_RIU_WriteByte(0x103308,0x00);
922
923 // enable dvbc adc clock
924 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
925 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
926 HAL_DMD_RIU_WriteByte(0x103315,0x00);
927 HAL_DMD_RIU_WriteByte(0x103314,0x00);
928
929 udatatemp = HAL_DMD_RIU_ReadByte(0x111f2a);
930 HAL_DMD_RIU_WriteByte(0x111f2a,udatatemp&0xF8);
931
932 // Reset TS divider
933 HAL_DMD_RIU_WriteByte(0x103302,0x01);
934 HAL_DMD_RIU_WriteByte(0x103302,0x00);
935
936 // enable vif DAC clock
937 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
938 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
939 // HAL_DMD_RIU_WriteByte(0x10331b,0x00);
940 // HAL_DMD_RIU_WriteByte(0x10331a,0x00);
941
942 // Select MPLLDIV17
943 // [0] : reg_atsc_adc_sel_mplldiv2
944 // [1] : reg_atsc_eq_sel_mplldiv2
945 // [2] : reg_eq25_sel_mplldiv3
946 // [3] : reg_p4_cfo_sel_eq25
947 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
948 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
949 // HAL_DMD_RIU_WriteByte(0x111f28,0x03);
950
951 // *** Set register at CLKGEN_DMD
952 // enable atsc clock
953 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
954 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
955 // HAL_DMD_RIU_WriteByte(0x111f03,0x04);
956 // HAL_DMD_RIU_WriteByte(0x111f02,0x04);
957 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
958 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
959 // HAL_DMD_RIU_WriteByte(0x111f05,0x00);
960 // HAL_DMD_RIU_WriteByte(0x111f04,0x00);
961 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
962 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
963 // HAL_DMD_RIU_WriteByte(0x111f07,0x04);
964 // HAL_DMD_RIU_WriteByte(0x111f06,0x04);
965
966 // enable clk_atsc_adcd_sync
967 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
968 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
969 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
970 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
971
972 // enable dvbt inner clock
973 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
974 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
975 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
976 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
977
978 // enable dvbt inner clock
979 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
980 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
981 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
982 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
983
984 // enable dvbt inner clock
985 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
986 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
987 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
988 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
989
990 // enable dvbc outer clock
991 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
992 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
993 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
994 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
995
996 // enable dvbc inner-c clock
997 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
998 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
999 // HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1000 // HAL_DMD_RIU_WriteByte(0x111f14,0x00);
1001
1002 // enable dvbc eq clock
1003 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1004 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1005 // HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1006 // HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1007
1008 // enable sram clock
1009 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1010 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1011 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1012 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1013
1014 // select clock
1015 // [3:0] : reg_ckg_frontend
1016 // [0] : disable clock
1017 // [1] : invert clock
1018 // [3:2]: Select clock source
1019 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
1020 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1021 // 10: reserved
1022 // 11: select DFT_CLK
1023 // [7:4] : reg_ckg_tr
1024 // [0] : disable clock
1025 // [1] : invert clock
1026 // [3:2]: Select clock source
1027 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
1028 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1029 // 10: reserved
1030 // 11: select DFT_CLK
1031 // [11:8]: reg_ckg_acifir
1032 // [0] : disable clock
1033 // [1] : invert clock
1034 // [3:2]: Select clock source
1035 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
1036 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1037 // 10: clk_vif_ssc_mux (43.2~50.82 MHz, VIF)
1038 // 11: select DFT_CLK
1039 // [15:12]: reg_ckg_frontend_d2
1040 // [0] : disable clock
1041 // [1] : invert clock
1042 // [3:2]: Select clock source
1043 // 00: clk_dmdadc_div2
1044 // 01: clk_dmplldiv17_div4(12.705 MHz)
1045 // 10: reserved
1046 // 11: select DFT_CLK
1047 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1048 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1049 // HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1050 // HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1051
1052 // enable isdbt clock
1053 // [2:0] : reg_ckg_isdbt_inner1x
1054 // [0] : disable clock
1055 // [1] : invert clock
1056 // [3:2]: Select clock source
1057 // 00: clk_dmplldiv10_div4(21.6MHz, ISDBT only)
1058 // 01: reserved
1059 // 10: reserved
1060 // 11: DFT_CLK
1061 // [6:4]: reg_ckg_isdbt_inner2x
1062 // [0] : disable clock
1063 // [1] : invert clock
1064 // [2]: Select clock source
1065 // 00: clk_dmplldiv10_div2(43.2MHz,ISDBT only)
1066 // 01: reserved
1067 // 10: reserved
1068 // 11: DFT_CLK
1069 // [10:8] : reg_ckg_isdbt_inner4x
1070 // [0] : disable clock
1071 // [1] : invert clock
1072 // [3:2]: Select clock source
1073 // 00: clk_dmplldiv10(86.4 MHz, DVBT only)
1074 // 01: reserved
1075 // 10: reserved
1076 // 11: DFT_CLK
1077 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1078 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1079 // HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1080 // HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1081
1082
1083 // enable isdbt outer clock
1084 // [3:0] : reg_ckg_isdbt_outer1x
1085 // [0] : disable clock
1086 // [1] : invert clock
1087 // [3:2]: Select clock source
1088 // 00: isdbt_clk6_lat (6 MHz)
1089 // 01: isdbt_clk8_lat (8 MHz)
1090 // 10: reserved
1091 // 11: DFT_CLK
1092 // [6:4]: reg_ckg_isdbt_outer4x
1093 // [0] : disable clock
1094 // [1] : invert clock
1095 // [3:2]: Select clock source
1096 // 00: isdbt_clk24_lat(24 MHz)
1097 // 01: isdbt_clk32_lat(32 MHz)
1098 // 10: reserved
1099 // 11: DFT_CLK
1100 // [10:8]: reg_ckg_isdbt_outer6x
1101 // [0] : disable clock
1102 // [1] : invert clock
1103 // [2] : Select clock source
1104 // 00: isdbt_clk36_lat(36 MHz)
1105 // 01: isdbt_clk48_lat(48 MHz)
1106 // 10: reserved
1107 // 11: DFT_CLK
1108 // [14:12]: reg_ckg_isdbt_outer12x
1109 // [0] : disable clock
1110 // [1] : invert clock
1111 // [2] : Select clock source
1112 // 00: isdbt_clk72_lat(72 MHz)
1113 // 01: isdbt_clk96_lat(96 MHz)
1114 // 10: reserved
1115 // 11: DFT_CLK
1116 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1117 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1118 // HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1119 // HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1120
1121 // Enable ISDBT clk_outer_div
1122 // reg_clk_isdbt_outer_div_en[0]
1123 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1124 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1125 // HAL_DMD_RIU_WriteByte(0x111f46,0x01);
1126
1127 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1128 // [1:0] : reg_ckg_dvbtc_sram4_isdbt_inner4x
1129 // [0]: disable clock
1130 // [1]: invert clock
1131 // [5:4] : reg_ckg_dvbtc_sram4_isdbt_outer6x
1132 // [0]: disable clock
1133 // [1]: invert clock
1134 // [9:8] : reg_ckg_adc1x_eq1x
1135 // [0]: disable clock
1136 // [1]: invert clock
1137 // [13:12] : reg_ckg_adc0p5x_eq0p5x
1138 // [0]: disable clock
1139 // [1]: invert clock
1140 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1141 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1142 HAL_DMD_RIU_WriteByte(0x111f49,0x00);
1143 HAL_DMD_RIU_WriteByte(0x111f48,0x00);
1144
1145 // [1:0] : reg_ckg_isdbt_outer6x_dvbt_inner1x
1146 // [0]: disable clock
1147 // [1]: invert clock
1148 // [5:4] : reg_ckg_isdbt_outer6x_dvbt_inner2x
1149 // [0]: disable clock
1150 // [1]: invert clock
1151 // [9:8] : reg_ckg_isdbt_outer6x_dvbt_outer2x
1152 // [0]: disable clock
1153 // [1]: invert clock
1154 // [13:12]: reg_ckg_isdbt_outer6x_dvbt_outer2x_c
1155 // [0]: disable clock
1156 // [1]: invert clock
1157 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1158 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1159 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
1160 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
1161
1162 // enable isdbt outer clock_rs
1163 // [7:4] : reg_ckg_isdbt_outer_rs
1164 // [0] : disable clock
1165 // [1] : invert clock
1166 // [3:2]: Select clock source
1167 // 00: isdbt_clk36_lat (36 MHz)
1168 // 01: isdbt_clk48_lat (48 MHz)
1169 // 10: clk_dmplldiv3_div4(72 MHz)
1170 // 11: isdbt_clk96_buf (96 MHz)
1171 // enable share isdbt &dvbt logic clock
1172 // [1:0] : reg_ckg_isdbt_inner2x_dvbt_inner2x
1173 // [0]: disable clock
1174 // [1]: invert clock
1175 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1176 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1177 // HAL_DMD_RIU_WriteByte(0x111f4c,0x00);
1178 HAL_DMD_RIU_WriteByte(0x111f4d,0x00);
1179 HAL_DMD_RIU_WriteByte(0x111f4c,0x10);
1180
1181 // enable vif clock
1182 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1183 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1184 // HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
1185 // HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
1186
1187 // enable DEMODE-DMA clock
1188 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1189 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1190 // HAL_DMD_RIU_WriteByte(0x111f21,0x00);
1191 // HAL_DMD_RIU_WriteByte(0x111f20,0x00);
1192
1193 // select clock
1194 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1195 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1196 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1197 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1198
1199
1200 // [15:12]: reg_ckg_dtmb_sram_dump
1201 // [0] : disable clock
1202 // [1] : invert clock
1203 // [3:2]: Select clock source
1204 // 00: dtmb_clk18_buf(16 MHz)
1205 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1206 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1207 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1208 HAL_DMD_RIU_WriteByte(0x111f71,0x18);
1209 HAL_DMD_RIU_WriteByte(0x111f70,0x81);
1210
1211 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1212 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1213
1214 HAL_DMD_RIU_WriteByte(0x111f4f,0x0c);
1215 HAL_DMD_RIU_WriteByte(0x111f4e,0x40);
1216
1217 HAL_DMD_RIU_WriteByte(0x111f51,0x48);
1218 HAL_DMD_RIU_WriteByte(0x111f50,0x44);
1219
1220 // Enable SAWLESS clock
1221 // reg_ckg_adcd_d2 @0x12[3:0]
1222 // reg_ckg_adcd_d4 @0x12[7:4]
1223 // reg_ckg_adcd_d6 @0x12[11:8]
1224 // reg_ckg_adcd_d12@0x12[15:12]
1225 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1226 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1227 // wriu 0x111f25 0x00
1228 // wriu 0x111f24 0x00
1229 // HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1230 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1231
1232 // ----------------------------------------------
1233 // start demod CLKGEN setting
1234 // ----------------------------------------------
1235
1236 // reg_allpad_in=0
1237 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1238 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1239 // HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1240 // HAL_DMD_RIU_WriteByte(0x101ea0,0x00);
1241
1242 // reg_ts1config=2
1243 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1244 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1245 //HAL_DMD_RIU_WriteByte(0x101eaf,0x10);
1246 //HAL_DMD_RIU_WriteByte(0x101eae,0x00);
1247
1248 // select DMD MCU
1249 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1250 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1251 // begin BY temp patch
1252 // HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1253 // HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1254 // end
1255 // HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1256 // ----------------------------------------------
1257 // Turn TSP
1258 // ----------------------------------------------
1259 // turn on ts1_clk, ts0_clk
1260 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1261 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1262 // check TSP work or not
1263 //HAL_DMD_RIU_WriteByte(0x100b51,0x00);
1264 //HAL_DMD_RIU_WriteByte(0x100b50,0x00);
1265
1266 // stream2miu_en, activate rst_wadr
1267 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1268 // HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1269 // stream2miu_en, turn off rst_wadr
1270 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1271 // wriu 0x000e13 0x01
1272 //HAL_DMD_RIU_WriteByte(0x000e13,0x01);
1273 // udatatemp = HAL_DMD_RIU_ReadByte(0x000e13);
1274 // HAL_DMD_RIU_WriteByte(0x000e13, udatatemp&0xFB);//Set 0e12,Bit10=0,
1275 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1276 }
1277
1278 /***********************************************************************************
1279 Subject: Power on initialized function
1280 Function: INTERN_DVBT_Power_On_Initialization
1281 Parmeter:
1282 Return: MS_BOOL
1283 Remark:
1284 ************************************************************************************/
1285
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)1286 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
1287 {
1288 MS_U16 status = true;
1289 MS_U8 cData = 0;
1290 //U8 cal_done;
1291 DBG_INTERN_DVBT(printf("INTERN_DVBT_Power_On_Initialization\n"));
1292
1293 #if defined(PWS_ENABLE)
1294 Mapi_PWS_Stop_VDMCU();
1295 #endif
1296
1297 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
1298 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1299 //// Firmware download //////////
1300 DBG_INTERN_DVBT(printf("INTERN_DVBT Load DSP...\n"));
1301 //MsOS_DelayTask(100);
1302
1303 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1304 {
1305 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1306 {
1307 printf("DVB-T Load DSP Code Fail\n");
1308 return FALSE;
1309 }
1310 else
1311 {
1312 DBG_INTERN_DVBT(printf("DVB-T Load DSP Code OK\n"));
1313 }
1314 }
1315
1316
1317 //// MCU Reset //////////
1318 DBG_INTERN_DVBT(printf("INTERN_DVBT Reset...\n"));
1319 if (INTERN_DVBT_Reset() == FALSE)
1320 {
1321 DBG_INTERN_DVBT(printf("Fail\n"));
1322 return FALSE;
1323 }
1324 else
1325 {
1326 DBG_INTERN_DVBT(printf("OK\n"));
1327 }
1328
1329 // reset FDP
1330 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1331 // SRAM setting, DVB-T use it.
1332 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1333 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1334 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1335
1336 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1337 return status;
1338 }
1339
1340 /************************************************************************************************
1341 Subject: Driving control
1342 Function: INTERN_DVBT_Driving_Control
1343 Parmeter: bInversionEnable : TRUE For High
1344 Return: void
1345 Remark:
1346 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1347 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1348 {
1349 MS_U8 u8Temp;
1350
1351 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1352
1353 if (bEnable)
1354 {
1355 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1356 }
1357 else
1358 {
1359 u8Temp = u8Temp & (~0x01);
1360 }
1361
1362 DBG_INTERN_DVBT(printf("---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1363 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1364 }
1365 /************************************************************************************************
1366 Subject: Clk Inversion control
1367 Function: INTERN_DVBT_Clk_Inversion_Control
1368 Parmeter: bInversionEnable : TRUE For Inversion Action
1369 Return: void
1370 Remark:
1371 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1372 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1373 {
1374 MS_U8 u8Temp;
1375
1376 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1377
1378 if (bInversionEnable)
1379 {
1380 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1381 }
1382 else
1383 {
1384 u8Temp = u8Temp & (~0x02);
1385 }
1386
1387 DBG_INTERN_DVBT(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1388 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1389 }
1390 /************************************************************************************************
1391 Subject: Transport stream serial/parallel control
1392 Function: INTERN_DVBT_Serial_Control
1393 Parmeter: bEnable : TRUE For serial
1394 Return: MS_BOOL :
1395 Remark:
1396 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1397 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1398 {
1399 MS_U8 status = true;
1400 MS_U8 temp_val;
1401 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_ts... u8TSClk=%d\n",u8TSClk));
1402
1403 if (u8TSClk == 0xFF) u8TSClk=0x13;
1404 if (bEnable) //Serial mode for TS pad
1405 {
1406 // serial
1407 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1408 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1409
1410 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1411 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1412 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1413
1414 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1415 temp_val|=0x04;
1416 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1417 #else
1418 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1419 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1420 temp_val|=0x07;
1421 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1422 #endif
1423 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1424 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1425
1426 //// INTERN_DVBT TS Control: Serial //////////
1427 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1428
1429 gsCmdPacket.param[0] = TS_SERIAL;
1430 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1431 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1432 #else
1433 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1434 #endif
1435 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1436 }
1437 else
1438 {
1439 //parallel
1440 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1441 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1442
1443 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1444 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1445 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1446 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1447 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1448 temp_val|=0x05;
1449 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1450 #else
1451 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1452 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1453 temp_val|=0x07;
1454 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1455 #endif
1456
1457 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1458 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1459
1460 //// INTERN_DVBT TS Control: Parallel //////////
1461 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1462
1463 gsCmdPacket.param[0] = TS_PARALLEL;
1464 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1465 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1466 #else
1467 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1468 #endif
1469 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1470 }
1471
1472 DBG_INTERN_DVBT(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1473
1474 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1475 return status;
1476 }
1477
1478 /************************************************************************************************
1479 Subject: TS1 output control
1480 Function: INTERN_DVBT_PAD_TS1_Enable
1481 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1482 Return: void
1483 Remark:
1484 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1485 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1486 {
1487 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_TS1_Enable... \n"));
1488
1489 if(flag) // PAD_TS1 Enable TS CLK PAD
1490 {
1491 //printf("=== TS1_Enable ===\n");
1492 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1493 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1494 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1495 }
1496 else // PAD_TS1 Disable TS CLK PAD
1497 {
1498 //printf("=== TS1_Disable ===\n");
1499 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1500 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1501 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1502 }
1503 }
1504
1505 /************************************************************************************************
1506 Subject: channel change config
1507 Function: INTERN_DVBT_Config
1508 Parmeter: BW: bandwidth
1509 Return: MS_BOOL :
1510 Remark:
1511 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1512 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1513 {
1514 MS_U8 bandwidth;
1515 MS_U8 status = true;
1516 MS_U8 temp_val;
1517 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_config %d %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap));
1518 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime()));
1519
1520 if (u8TSClk == 0xFF) u8TSClk=0x13;
1521 switch(BW)
1522 {
1523 case E_DMD_RF_CH_BAND_6MHz:
1524 bandwidth = 1;
1525 break;
1526 case E_DMD_RF_CH_BAND_7MHz:
1527 bandwidth = 2;
1528 break;
1529 case E_DMD_RF_CH_BAND_8MHz:
1530 default:
1531 bandwidth = 3;
1532 break;
1533 }
1534
1535 status &= INTERN_DVBT_Reset();
1536
1537 // BW mode
1538 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1539 // TS mode
1540 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1541 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1542 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1543 // Hierarchy mode
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1545 // FC
1546 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1547 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1548 // FS
1549 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1550 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1551 // IQSwap
1552 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1553
1554 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1555 // Fif
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1557 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1558
1559 //// INTERN_DVBT system init: DVB-T //////////
1560 gsCmdPacket.cmd_code = CMD_SYSTEM_INIT;
1561
1562 gsCmdPacket.param[0] = E_SYS_DVBT;
1563 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1564
1565 if(bSerialTS)
1566 {
1567 // serial
1568 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1569 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1570
1571 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1572 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1573 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1574 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1575 temp_val|=0x04;
1576 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1577 #else
1578 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1579 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1580 temp_val|=0x07;
1581 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1582 #endif
1583 }
1584 else
1585 {
1586 //parallel
1587 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1588 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1589
1590 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1591 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1592 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1593 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1594 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1595 temp_val|=0x05;
1596 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1597 #else
1598 HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1599 #endif
1600 }
1601 return status;
1602 }
1603 /************************************************************************************************
1604 Subject: enable hw to lock channel
1605 Function: INTERN_DVBT_Active
1606 Parmeter: bEnable
1607 Return: MS_BOOL
1608 Remark:
1609 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1610 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1611 {
1612 MS_U8 status = true;
1613
1614 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_active\n"));
1615
1616 //// INTERN_DVBT Finite State Machine on/off //////////
1617 #if 0
1618 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1619
1620 gsCmdPacket.param[0] = (MS_U8)bEnable;
1621 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1622 #else
1623 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1624 #endif
1625 INTERN_DVBT_SignalQualityReset();
1626
1627 return status;
1628 }
1629 /************************************************************************************************
1630 Subject: Return lock status
1631 Function: INTERN_DVBT_Lock
1632 Parmeter: eStatus :
1633 Return: MS_BOOL
1634 Remark:
1635 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1636 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1637 {
1638 float fBER=0.0f;
1639
1640 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1641 {
1642 if (bFECLock == FALSE)
1643 {
1644 u32FecFirstLockTime = MsOS_GetSystemTime();
1645 DBG_INTERN_DVBT(printf("++++++++[utopia]dvbt lock\n"));
1646 }
1647
1648 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1649 {
1650 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1651 {
1652 if(fViterbiBerFiltered <= 0.0)
1653 fViterbiBerFiltered = fBER;
1654 else
1655 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1656 }
1657 DBG_INTERN_DVBT(printf("[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered));
1658 }
1659 u32FecLastLockTime = MsOS_GetSystemTime();
1660 bFECLock = TRUE;
1661 return E_DMD_LOCK;
1662 }
1663 else
1664 {
1665 INTERN_DVBT_SignalQualityReset();
1666 if (bFECLock == TRUE)
1667 {
1668 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1669 {
1670 return E_DMD_LOCK;
1671 }
1672 }
1673 bFECLock = FALSE;
1674 }
1675
1676 if(!bTPSLock)
1677 {
1678 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1679 {
1680 DBG_INTERN_DVBT(printf("==> INTERN_DVBT_Lock -- TPSLock \n"););
1681 bTPSLock = TRUE;
1682 }
1683 }
1684 if(bTPSLock)
1685 {
1686 DBG_INTERN_DVBT(printf("TPSLock %ld\n",MsOS_GetSystemTime()));
1687 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1688 {
1689 return E_DMD_CHECKING;
1690 }
1691 }
1692 else
1693 {
1694 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1695 {
1696 return E_DMD_CHECKING;
1697 }
1698 }
1699 return E_DMD_UNLOCK;
1700
1701 }
1702
1703
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1704 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1705 {
1706 MS_U16 u16Address = 0;
1707 MS_U8 cData = 0;
1708 MS_U8 cBitMask = 0;
1709
1710 switch( eStatus )
1711 {
1712 case E_DMD_COFDM_FEC_LOCK:
1713 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1714
1715 if (cData == 0x0B)
1716 {
1717 return TRUE;
1718 }
1719 else
1720 {
1721 return FALSE; // continuously un-lock
1722 }
1723 break;
1724
1725 case E_DMD_COFDM_PSYNC_LOCK:
1726 u16Address = 0x232C; //FEC: P-sync Lock,
1727 cBitMask = BIT(1);
1728 break;
1729
1730 case E_DMD_COFDM_TPS_LOCK:
1731 u16Address = 0x2222; //TPS HW Lock,
1732 cBitMask = BIT(1);
1733 break;
1734
1735 case E_DMD_COFDM_DCR_LOCK:
1736 u16Address = 0x2145; //DCR Lock,
1737 cBitMask = BIT(0);
1738 break;
1739
1740 case E_DMD_COFDM_AGC_LOCK:
1741 u16Address = 0x212F; //AGC Lock,
1742 cBitMask = BIT(0);
1743 break;
1744
1745 case E_DMD_COFDM_MODE_DET:
1746 u16Address = 0x24CF; //Mode CP Detect,
1747 cBitMask = BIT(4);
1748 break;
1749
1750 case E_DMD_COFDM_TPS_EVER_LOCK:
1751 u16Address = 0x20C0; //TPS Ever Lock,
1752 cBitMask = BIT(3);
1753 break;
1754
1755 default:
1756 return FALSE;
1757 }
1758
1759 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1760 return FALSE;
1761
1762 if ((cData & cBitMask) == cBitMask)
1763 {
1764 return TRUE;
1765 }
1766
1767 return FALSE;
1768
1769 }
1770
1771 /****************************************************************************
1772 Subject: To get the Post viterbi BER
1773 Function: INTERN_DVBT_GetPostViterbiBer
1774 Parmeter: Quility
1775 Return: E_RESULT_SUCCESS
1776 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1777 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1778 We will not read the Period, and have the "/256/8"
1779 *****************************************************************************/
INTERN_DVBT_GetPostViterbiBer(float * ber)1780 MS_BOOL INTERN_DVBT_GetPostViterbiBer(float *ber)
1781 {
1782 MS_BOOL status = true;
1783 MS_U8 reg=0, reg_frz=0;
1784 MS_U16 BitErrPeriod;
1785 MS_U32 BitErr;
1786 MS_U16 PktErr;
1787
1788 /////////// Post-Viterbi BER /////////////
1789
1790 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1791 {
1792 *ber = (float)-1.0;
1793 return false;
1794 }
1795 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1796 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1797 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1798
1799 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1800 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1802 BitErrPeriod = reg;
1803
1804 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1805 BitErrPeriod = (BitErrPeriod << 8)|reg;
1806
1807 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1808 // 0x6b [15:8] reg_bit_err_num_15_8
1809 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1810 // 0x6d [15:8] reg_bit_err_num_31_24
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1812 BitErr = reg;
1813
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1815 BitErr = (BitErr << 8)|reg;
1816
1817 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1818 BitErr = (BitErr << 8)|reg;
1819
1820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1821 BitErr = (BitErr << 8)|reg;
1822
1823 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1824 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1826 PktErr = reg;
1827
1828 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1829 PktErr = (PktErr << 8)|reg;
1830
1831 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1832 reg_frz=reg_frz&(~0x03);
1833 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1834
1835 if (BitErrPeriod == 0 ) //protect 0
1836 BitErrPeriod = 1;
1837
1838 if (BitErr <=0 )
1839 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1840 else
1841 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1842
1843
1844 DBG_GET_SIGNAL(printf("INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1845 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1846
1847 return status;
1848 }
1849
1850 /****************************************************************************
1851 Subject: To get the Pre viterbi BER
1852 Function: INTERN_DVBT_GetPreViterbiBer
1853 Parmeter: ber
1854 Return: E_RESULT_SUCCESS
1855 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1856 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1857 We will not read the Period, and have the "/256/8"
1858 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1859 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1860 {
1861 MS_U8 status = true;
1862 MS_U8 reg=0, reg_frz=0;
1863 MS_U16 BitErrPeriod;
1864 MS_U32 BitErr;
1865 MS_BOOL BEROver;
1866
1867 // bank 7 0x10 [3] reg_rd_freezeber
1868 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1869 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1870
1871 // bank 7 0x16 [7:0] reg_ber_timerl
1872 // [15:8] reg_ber_timerm
1873 // bank 7 0x18 [5:0] reg_ber_timerh
1874 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1875 BitErrPeriod = reg&0x3f;
1876
1877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1878 BitErrPeriod = (BitErrPeriod << 8)|reg;
1879
1880 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1881 BitErrPeriod = (BitErrPeriod << 8)|reg;
1882
1883 // bank 7 0x1e [7:0] reg_ber_7_0
1884 // [15:8] reg_ber_15_8
1885 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1886 BitErr = reg;
1887
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1889 BitErr = (BitErr << 8)|reg;
1890
1891 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1892 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1893 if (reg & 0x10)
1894 BEROver = true;
1895 else
1896 BEROver = false;
1897
1898 if (BitErrPeriod ==0 )//protect 0
1899 BitErrPeriod=1;
1900
1901 if (BEROver)
1902 {
1903 *ber = 1;
1904 printf("BER is over\n");
1905 }
1906 else
1907 {
1908 if (BitErr <=0 )
1909 *ber=0.5 / (float)(BitErrPeriod * 256);
1910 else
1911 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1912 }
1913
1914 // bank 7 0x10 [3] reg_rd_freezeber
1915 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1916
1917 return status;
1918 }
1919
1920 /****************************************************************************
1921 Subject: To get the Packet error
1922 Function: INTERN_DVBT_GetPacketErr
1923 Parmeter: pktErr
1924 Return: E_RESULT_SUCCESS
1925 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1926 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1927 We will not read the Period, and have the "/256/8"
1928 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1929 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1930 {
1931 MS_BOOL status = true;
1932 MS_U8 reg = 0, reg_frz = 0;
1933 MS_U16 PktErr;
1934
1935 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1936 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1937 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1938
1939 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1940 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1942 PktErr = reg;
1943
1944 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1945 PktErr = (PktErr << 8)|reg;
1946
1947 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1948 reg_frz=reg_frz&(~0x03);
1949 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1950
1951 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1952
1953 *u16PktErr = PktErr;
1954
1955 return status;
1956 }
1957
1958 /****************************************************************************
1959 Subject: To get the DVBT parameter
1960 Function: INTERN_DVBT_Get_TPS_Info
1961 Parmeter: point to return parameter
1962 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1963 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1964 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1965 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1966 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1967 FFT ( b14) : 0~1 => 2K, 8K
1968 Priority(bit 15) : 0~1=> HP,LP
1969 Return: TRUE
1970 FALSE
1971 Remark: The TPS parameters will be available after TPS lock
1972 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1973 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1974 {
1975 MS_U8 u8Temp;
1976
1977 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1978 return FALSE;
1979
1980 if ((u8Temp& 0x02) != 0x02)
1981 {
1982 return FALSE; //TPS unlock
1983 }
1984 else
1985 {
1986 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1987 return FALSE;
1988
1989 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1990 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1991
1992 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1993 return FALSE;
1994
1995 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1996 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1997
1998 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1999 return FALSE;
2000
2001 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
2002 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
2003
2004 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
2005 return FALSE;
2006
2007 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
2008
2009 }
2010 return TRUE;
2011 }
2012
2013
2014 /****************************************************************************
2015 Subject: Read the signal to noise ratio (SNR)
2016 Function: INTERN_DVBT_GetSNR
2017 Parmeter: None
2018 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2019 Remark:
2020 *****************************************************************************/
INTERN_DVBT_GetSNR(void)2021 float INTERN_DVBT_GetSNR (void)
2022 {
2023 MS_U8 status = true;
2024 MS_U8 reg=0, reg_frz=0;
2025 MS_U32 noise_power;
2026 float snr;
2027
2028 // bank 6 0xfe [0] reg_fdp_freeze
2029 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2030 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2031
2032 // bank 6 0xff [0] reg_fdp_load
2033 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2034
2035 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
2036 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x4d, ®);
2037 noise_power = reg & 0x07;
2038
2039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x4c, ®);
2040 noise_power = (noise_power << 8)|reg;
2041
2042 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x4b, ®);
2043 noise_power = (noise_power << 8)|reg;
2044
2045 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x4a, ®);
2046 noise_power = (noise_power << 8)|reg;
2047
2048 noise_power = noise_power/2;
2049
2050 // bank 6 0x26 [5:4] reg_transmission_mode
2051 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2052
2053 // bank 6 0xfe [0] reg_fdp_freeze
2054 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
2055
2056 // bank 6 0xff [0] reg_fdp_load
2057 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2058
2059
2060 if ((reg&0x30)==0x00) //2K
2061 {
2062 if (noise_power<1512)
2063 snr = 0;
2064 else
2065 #ifdef MSOS_TYPE_LINUX
2066 snr = 10*log10f((float)noise_power/1512);
2067 #else
2068 snr = 10*Log10Approx((float)noise_power/1512);
2069 #endif
2070 }
2071 //else if ((reg&0x30)==0x10)//8K
2072 else
2073 {
2074 if (noise_power<6048)
2075 snr = 0;
2076 else
2077 #ifdef MSOS_TYPE_LINUX
2078 snr = 10*log10f((float)noise_power/6048);
2079 #else
2080 snr = 10*Log10Approx((float)noise_power/6048);
2081 #endif
2082 }
2083 /* ignore 4K
2084 else //4K
2085 {
2086 if (noise_power<3024)
2087 snr = 0;
2088 else
2089 snr = 10*Log10Approx(noise_power/3024);
2090 }
2091 */
2092
2093 if (status == true)
2094 return snr;
2095 else
2096 return -1;
2097
2098 }
2099
2100 /****************************************************************************
2101 Subject: To check if Hierarchy on
2102 Function: INTERN_DVBT_Is_HierarchyOn
2103 Parmeter:
2104 Return: BOOLEAN
2105 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)2106 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
2107 {
2108 MS_U16 u16_tmp;
2109
2110 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
2111 return FALSE;
2112 //printf("u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
2113 if(u16_tmp&0x38)
2114 {
2115 return TRUE;
2116 }
2117 return FALSE;
2118 }
2119
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2120 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2121 {
2122 MS_U8 status = true;
2123 float ch_power_db = 0.0f;
2124 float ch_power_ref = 11.0f;
2125 float ch_power_rel = 0.0f;
2126 MS_U8 u8_index = 0;
2127 MS_U16 tps_info_qam,tps_info_cr;
2128
2129 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2130 {
2131 *strength = 0;
2132 return TRUE;
2133 }
2134 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2135
2136 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
2137 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
2138 /* Actually, it's more reasonable, that signal level depended on cable input power level
2139 * thougth the signal isn't dvb-t signal.
2140 */
2141
2142 // use pointer of IFAGC table to identify
2143 // case 1: RFAGC from SAR, IFAGC controlled by demod
2144 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2145 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2146 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
2147 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2148 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2149 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
2150 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
2151
2152
2153 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
2154 printf("[dvbt]TPS qam parameter retrieve failure\n");
2155
2156 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
2157 printf("[dvbt]TPS cr parameter retrieve failure\n");
2158
2159
2160 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2161 {
2162 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
2163 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
2164 {
2165 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2166 break;
2167 }
2168 else
2169 {
2170 u8_index++;
2171 }
2172 }
2173
2174 if (ch_power_ref > 10.0f)
2175 *strength = 0;
2176 else
2177 {
2178 ch_power_rel = ch_power_db - ch_power_ref;
2179
2180 if ( ch_power_rel < -15.0f )
2181 {
2182 *strength = 0;
2183 }
2184 else if ( ch_power_rel < 0.0f )
2185 {
2186 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2187 }
2188 else if ( ch_power_rel < 20 )
2189 {
2190 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2191 }
2192 else if ( ch_power_rel < 35.0f )
2193 {
2194 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2195 }
2196 else
2197 {
2198 *strength = 100;
2199 }
2200 }
2201
2202 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2203 {
2204 *strength = 0;
2205 return TRUE;
2206 }
2207
2208 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2209 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2210
2211 return status;
2212 }
2213
2214 /****************************************************************************
2215 Subject: To get the DVT Signal quility
2216 Function: INTERN_DVBT_GetSignalQuality
2217 Parmeter: Quility
2218 Return: E_RESULT_SUCCESS
2219 E_RESULT_FAILURE
2220 Remark: Here we have 4 level range
2221 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2222 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2223 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2224 <4>.4th Range => Quality <10
2225 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2226 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2227 {
2228 float ber_sqi;
2229 float fber;
2230 float cn_rec = 0;
2231 float cn_nordig_p1 = 0;
2232 float cn_rel = 0;
2233
2234 MS_U8 status = true;
2235 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
2236 MS_U16 u16_tmp;
2237
2238 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2239
2240 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
2241 {
2242
2243 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2244 {
2245 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2246 }
2247 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
2248 if(fViterbiBerFiltered<= 0.0)
2249 {
2250 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
2251 {
2252 DBG_INTERN_DVBT(printf("GetPostViterbiBer Fail!\n"));
2253 return FALSE;
2254 }
2255 fViterbiBerFiltered = fber;
2256 }
2257 else
2258 {
2259 fber = fViterbiBerFiltered;
2260 }
2261
2262 if (fber > 1.0E-3)
2263 ber_sqi = 0.0;
2264 else if (fber > 8.5E-7)
2265 #ifdef MSOS_TYPE_LINUX
2266 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2267 #else
2268 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2269 #endif
2270 else
2271 ber_sqi = 100.0;
2272
2273 cn_rec = INTERN_DVBT_GetSNR();
2274
2275 if (cn_rec == -1) //get SNR return fail
2276 status = false;
2277
2278 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2279 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2280 tps_cnstl = 0xff;
2281 tps_cr = 0xff;
2282 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
2283 tps_cnstl = (MS_U8)u16_tmp&0x07;
2284 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
2285 tps_cr = (MS_U8)u16_tmp&0x07;
2286
2287 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
2288 {
2289 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
2290 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
2291 {
2292 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
2293 break;
2294 }
2295 }
2296
2297 // 0,5, snr offset
2298 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
2299
2300 // patch....
2301 // Noridg SQI,
2302 // 64QAM, CR34, GI14, SNR 22dB.
2303 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
2304 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
2305 {
2306 cn_rel += 1.5f;
2307 }
2308
2309 if (cn_rel < -7.0f)
2310 {
2311 *quality = 0;
2312 }
2313 else if (cn_rel < 3.0)
2314 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
2315 else
2316 *quality = (MS_U16)ber_sqi;
2317 }
2318 else
2319 {
2320 *quality = 0;
2321 }
2322
2323 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2324 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2325 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2326 return status;
2327 }
2328
2329 /****************************************************************************
2330 Subject: To get the Cell ID
2331 Function: INTERN_DVBT_Get_CELL_ID
2332 Parmeter: point to return parameter cell_id
2333
2334 Return: TRUE
2335 FALSE
2336 Remark:
2337 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2338 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2339 {
2340 MS_U8 status = true;
2341 MS_U8 value1=0;
2342 MS_U8 value2=0;
2343
2344 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2345 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2346
2347 *cell_id = ((MS_U16)value1<<8)|value2;
2348 return status;
2349 }
2350 /*
2351 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2352 {
2353 #define SQI_LOOP_NUM 50
2354 U8 inn = 0;
2355 WORD sqi = 0;
2356 WORD ave_sqi = 0;
2357 WORD ave_num = 0;
2358 while(inn++<SQI_LOOP_NUM)
2359 {
2360 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2361 {
2362 printf("[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2363 ave_sqi+=sqi;
2364 ave_num++;
2365 }
2366 MsOS_DelayTask(50);
2367 }
2368
2369 if(ave_num != 0 )
2370 *quality = ave_sqi/ave_num;
2371
2372 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2373 }
2374 */
2375 /****************************************************************************
2376 Subject: To get the DVBT Carrier Freq Offset
2377 Function: INTERN_DVBT_Get_FreqOffset
2378 Parmeter: Frequency offset (in KHz), bandwidth
2379 Return: E_RESULT_SUCCESS
2380 E_RESULT_FAILURE
2381 Remark:
2382 *****************************************************************************/
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2383 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2384 {
2385 float N, FreqB;
2386 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2387 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2388 MS_U8 reg_frz=0, reg=0;
2389 MS_U8 status;
2390
2391 FreqB = (float)u8BW * 8 / 7;
2392
2393 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2394
2395 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2396
2397 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2398 RegCfoTd = reg;
2399
2400 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2401 RegCfoTd = (RegCfoTd << 8)|reg;
2402
2403 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2404 RegCfoTd = (RegCfoTd << 8)|reg;
2405
2406 FreqCfoTd = (float)RegCfoTd;
2407
2408 if (RegCfoTd & 0x800000)
2409 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2410
2411 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2412
2413 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2414
2415 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2416 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2417
2418 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2419
2420 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2421 RegCfoFd = reg;
2422
2423 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2424 RegCfoFd = (RegCfoFd << 8)|reg;
2425
2426 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2427 RegCfoFd = (RegCfoFd << 8)|reg;
2428
2429 FreqCfoFd = (float)RegCfoFd;
2430
2431 if (RegCfoFd & 0x800000)
2432 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2433
2434 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2435
2436 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2437 RegIcfo = reg & 0x07;
2438
2439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2440 RegIcfo = (RegIcfo << 8)|reg;
2441
2442 FreqIcfo = (float)RegIcfo;
2443
2444 if (RegIcfo & 0x400)
2445 FreqIcfo = FreqIcfo - (float)0x800;
2446
2447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2448 reg = reg & 0x30;
2449
2450 switch (reg)
2451 {
2452 case 0x00: N = 2048; break;
2453 case 0x20: N = 4096; break;
2454 case 0x10:
2455 default: N = 8192; break;
2456 }
2457
2458 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2459 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2460 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2461 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2462 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2463 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2464 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2465 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2466 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2467 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2468
2469 if (status == TRUE)
2470 return TRUE;
2471 else
2472 return FALSE;
2473 }
2474
2475
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2476 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2477 {
2478
2479 bPowerOn = bPowerOn;
2480 }
2481
INTERN_DVBT_Power_Save(void)2482 MS_BOOL INTERN_DVBT_Power_Save(void)
2483 {
2484
2485 return TRUE;
2486 }
2487
2488 /****************************************************************************
2489 Subject: To get the DVBT constellation parameter
2490 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2491 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2492 Return: TRUE
2493 FALSE
2494 Remark: The TPS parameters will be available after TPS lock
2495 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2496 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2497 {
2498 MS_U8 tps_param;
2499
2500 //@@++ Arki 20100125
2501 if (eSignalType == TS_MODUL_MODE)
2502 {
2503 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2504 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2505 }
2506
2507 if (eSignalType == TS_CODE_RATE)
2508 {
2509 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2510 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2511 }
2512
2513 if (eSignalType == TS_GUARD_INTERVAL)
2514 {
2515 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2516 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2517 }
2518
2519 if (eSignalType == TS_FFX_VALUE)
2520 {
2521 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2522 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2523 }
2524 //@@-- Arki 20100125
2525 return TRUE;
2526 }
2527
INTERN_DVBT_Version(MS_U16 * ver)2528 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2529 {
2530
2531 MS_U8 status = true;
2532 MS_U8 tmp = 0;
2533 MS_U16 u16_INTERN_DVBT_Version;
2534
2535 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2536 u16_INTERN_DVBT_Version = tmp;
2537 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2538 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2539 *ver = u16_INTERN_DVBT_Version;
2540
2541 return status;
2542 }
2543
INTERN_DVBT_Version_minor(MS_U8 * ver2)2544 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2545 {
2546
2547 MS_U8 status = true;
2548
2549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2550
2551 return status;
2552 }
2553
2554
INTERN_DVBT_Show_Demod_Version(void)2555 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2556 {
2557
2558 MS_BOOL status = true;
2559 MS_U16 u16_INTERN_DVBT_Version;
2560 MS_U8 u8_minor_ver;
2561
2562 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2563 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2564 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2565
2566 return status;
2567 }
2568
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2569 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2570 {
2571 MS_U8 u8_index = 0;
2572 MS_BOOL bRet = false;
2573
2574 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2575 {
2576 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2577 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2578 {
2579 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2580 bRet = true;
2581 break;
2582 }
2583 else
2584 {
2585 u8_index++;
2586 }
2587 }
2588 return bRet;
2589 }
2590
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2591 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2592 {
2593 MS_U8 u8_index = 0;
2594 MS_BOOL bRet = false;
2595
2596 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2597 {
2598 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2599 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2600 {
2601 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2602 bRet = true;
2603 break;
2604 }
2605 else
2606 {
2607 u8_index++;
2608 }
2609 }
2610 return bRet;
2611 }
2612
2613
2614 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2615 void INTERN_DVBT_get_demod_state(MS_U8* state)
2616 {
2617 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2618 return;
2619 }
2620
INTERN_DVBT_Show_ChannelLength(void)2621 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2622 {
2623 MS_U8 status = true;
2624 MS_U8 tmp = 0;
2625 MS_U16 len = 0;
2626 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2627 len = tmp;
2628 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2629 len = (len<<8)|tmp;
2630 printf("[dvbt]Hw_channel=%d\n",len);
2631 return status;
2632 }
2633
INTERN_DVBT_Show_SW_ChannelLength(void)2634 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2635 {
2636 MS_U8 status = true;
2637 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2638 MS_U16 sw_len = 0;
2639 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2640 sw_len = tmp;
2641 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2642 sw_len = (sw_len<<8)|tmp;
2643 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2644 peak_num = tmp;
2645 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2646 insideGI = tmp&0x01;
2647 stoptracking = (tmp&0x02)>>1;
2648 flag_short_echo = (tmp&0x0C)>>2;
2649 fsa_mode = (tmp&0x30)>>4;
2650
2651 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2652 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2653
2654 return status;
2655 }
2656
INTERN_DVBT_Show_ACI_CI(void)2657 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2658 {
2659
2660 #define BIT4 0x10
2661 MS_U8 status = true;
2662 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2663
2664 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2665 digACI = (tmp&BIT4)>>4;
2666
2667 // get flag_CI
2668 // 0: No interference
2669 // 1: CCI
2670 // 2: in-band ACI
2671 // 3: N+1 ACI
2672 // flag_ci = (tmp&0xc0)>>6;
2673 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2674 flag_CI = (tmp&0xC0)>>6;
2675 td_coef = (tmp&0x0C)>>2;
2676
2677 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2678
2679 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2680
2681 return status;
2682 }
2683
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2684 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2685 {
2686 MS_U8 status = true;
2687 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2688 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2689 fd = tmp;
2690 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2691 ch_len = tmp;
2692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2693 snr_sel = (tmp>>4)&0x03;
2694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2695 pertone_num = tmp;
2696
2697 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2698
2699 return status;
2700 }
2701
INTERN_DVBT_Get_CFO(void)2702 MS_BOOL INTERN_DVBT_Get_CFO(void)
2703 {
2704
2705 float N = 0, FreqB = 0;
2706 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2707 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2708 MS_U8 reg_frz = 0, reg = 0;
2709 MS_U8 status = 0;
2710 MS_U8 u8BW = 8;
2711
2712 FreqB = (float)u8BW * 8 / 7;
2713
2714 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2715
2716 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2717
2718 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2719 RegCfoTd = reg;
2720
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2722 RegCfoTd = (RegCfoTd << 8)|reg;
2723
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2725 RegCfoTd = (RegCfoTd << 8)|reg;
2726
2727 FreqCfoTd = (float)RegCfoTd;
2728
2729 if (RegCfoTd & 0x800000)
2730 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2731
2732 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2733
2734 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2735
2736 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2737 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2738
2739 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2740
2741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2742 RegCfoFd = reg;
2743
2744 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2745 RegCfoFd = (RegCfoFd << 8)|reg;
2746
2747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2748 RegCfoFd = (RegCfoFd << 8)|reg;
2749
2750 FreqCfoFd = (float)RegCfoFd;
2751
2752 if (RegCfoFd & 0x800000)
2753 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2754
2755 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2756
2757 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2758 RegIcfo = reg & 0x07;
2759
2760 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2761 RegIcfo = (RegIcfo << 8)|reg;
2762
2763 FreqIcfo = (float)RegIcfo;
2764
2765 if (RegIcfo & 0x400)
2766 FreqIcfo = FreqIcfo - (float)0x800;
2767
2768 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2769 reg = reg & 0x30;
2770
2771 switch (reg)
2772 {
2773 case 0x00: N = 2048; break;
2774 case 0x20: N = 4096; break;
2775 case 0x10:
2776 default: N = 8192; break;
2777 }
2778
2779 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2780 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2781 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2782 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2783 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2784
2785 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2786
2787 return status;
2788
2789 }
INTERN_DVBT_Get_SFO(void)2790 MS_BOOL INTERN_DVBT_Get_SFO(void)
2791 {
2792 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2793 MS_BOOL status = true;
2794 MS_U8 reg = 0;
2795 float FreqB = 9.143, FreqS = 45.473; //20.48
2796 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2797 float sfo_value = 0;
2798
2799 // get Reg_TDP_SFO,
2800 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2801 Reg_TDP_SFO = reg;
2802 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2803 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2804 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2805 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2806
2807 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2808
2809 // get Reg_FDP_SFO,
2810 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2811 Reg_FDP_SFO = reg;
2812 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2813 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2815 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2816
2817 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2818
2819 // get Reg_FSA_SFO,
2820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2821 Reg_FSA_SFO = reg;
2822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2823 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2824 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2825 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2826
2827 // get Reg_FSA_IN,
2828 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2829 Reg_FSA_IN = reg;
2830 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2831 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2832 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2833
2834 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2835 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2836
2837 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2838 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2839 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2840
2841
2842 return status;
2843 }
2844
INTERN_DVBT_Get_SYA_status(void)2845 void INTERN_DVBT_Get_SYA_status(void)
2846 {
2847 MS_U8 status = true;
2848 MS_U8 sya_k = 0,reg = 0;
2849 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2850
2851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2852 sya_k = reg;
2853
2854 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2855 sya_th = reg;
2856 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2857 sya_th = (sya_th<<8)|reg;
2858
2859 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2860 sya_offset = reg;
2861 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2862 sya_offset = (sya_offset<<8)|reg;
2863
2864 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2865 len_m = reg;
2866 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2867 len_m = (len_m<<8)|reg;
2868
2869 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2870 len_b = reg;
2871 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2872 len_b = (len_b<<8)|reg;
2873
2874
2875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2876 len_a = reg;
2877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2878 len_a = (len_a<<8)|reg;
2879
2880
2881 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2882 tracking_reg = reg;
2883
2884
2885 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2886 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2887
2888 return;
2889 }
2890
INTERN_DVBT_Get_cci_status(void)2891 void INTERN_DVBT_Get_cci_status(void)
2892 {
2893 MS_U8 status = true;
2894 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2895
2896 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2897 cci_fsweep = reg;
2898
2899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2900 cci_kp = reg;
2901
2902 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2903
2904 return;
2905 }
2906
INTERN_DVBT_Show_PRESFO_Info(void)2907 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2908 {
2909 MS_U8 tmp = 0;
2910 MS_BOOL status = TRUE;
2911 printf("\n[SFO]");
2912 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2913 printf("[%x]",tmp);
2914 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2915 printf("[%x]",tmp);
2916 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2917 printf("[%x]",tmp);
2918 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2919 printf("[%x]",tmp);
2920 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2921 printf("[%x]",tmp);
2922 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2923 printf("[%x]",tmp);
2924 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2925 printf("[%x]",tmp);
2926 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2927 printf("[%x][End]",tmp);
2928
2929 return status;
2930 }
2931
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2932 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2933 {
2934 MS_BOOL status = true;
2935
2936 *locktime = 0xffff;
2937 printf("[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2938
2939 status = false;
2940 return status;
2941 }
2942
2943
INTERN_DVBT_Show_Lock_Time_Info(void)2944 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2945 {
2946 MS_U16 locktime = 0;
2947 MS_BOOL status = TRUE;
2948 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2949 printf("[DVBT]lock_time = %d ms\n",locktime);
2950 return status;
2951 }
2952
INTERN_DVBT_Show_BER_Info(void)2953 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2954 {
2955 MS_U8 tmp = 0;
2956 MS_BOOL status = TRUE;
2957 printf("\n[BER]");
2958 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2959 printf("[%x,",tmp);
2960 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2961 printf("%x]",tmp);
2962 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2963 printf("[%x,",tmp);
2964 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2965 printf("%x]",tmp);
2966 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2967 printf("[%x,",tmp);
2968 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2969 printf("%x][End]",tmp);
2970
2971 return status;
2972
2973 }
2974
2975
INTERN_DVBT_Show_AGC_Info(void)2976 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2977 {
2978 MS_U8 tmp = 0;
2979 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2980 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2981 MS_U16 if_agc_err = 0;
2982 MS_BOOL status = TRUE;
2983 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2984
2985 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2987 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2988 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2989 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2991
2992
2993 // select IF gain to read
2994 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2995 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2996
2997 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2998 if_agc_gain = tmp;
2999 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3000 if_agc_gain = (if_agc_gain<<8)|tmp;
3001
3002
3003 // select d1 gain to read.
3004 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3005 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3006
3007 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3008 d1_gain = tmp;
3009 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3010 d1_gain = (d1_gain<<8)|tmp;
3011
3012 // select d2 gain to read.
3013 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3014 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3015
3016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3017 d2_gain = tmp;
3018 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3019 d2_gain = (d2_gain<<8)|tmp;
3020
3021 // select IF gain err to read
3022 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3023 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3024
3025 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3026 if_agc_err = tmp;
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3028 if_agc_err = (if_agc_err<<8)|tmp;
3029
3030 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3031 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3032 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3033
3034
3035
3036 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3037 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3038
3039 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3040 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3041
3042 return status;
3043
3044 }
3045
INTERN_DVBT_Show_WIN_Info(void)3046 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
3047 {
3048 MS_U8 tmp = 0;
3049 MS_U8 trigger = 0;
3050 MS_U16 win_len = 0;
3051
3052 MS_BOOL status = TRUE;
3053
3054 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3055 win_len = tmp;
3056 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3057 win_len = (win_len<<8)|tmp;
3058
3059 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3060
3061 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3062
3063 return status;
3064 }
3065
INTERN_DVBT_Show_td_coeff(void)3066 void INTERN_DVBT_Show_td_coeff(void)
3067 {
3068 MS_U8 status = true;
3069 MS_U8 w1 = 0,w2 = 0,reg = 0;
3070
3071 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3072 w1 = reg;
3073
3074 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3075 w2 = reg;
3076
3077 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
3078
3079 return;
3080 }
3081
3082 /********************************************************
3083 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
3084 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
3085 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3086 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3087 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
3088 * FFT ( b14) : 0~1 => 2K, 8K
3089 ********************************/
INTERN_DVBT_Show_Modulation_info(void)3090 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
3091 {
3092 MS_U16 tps_info;
3093
3094 // printf("[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
3095
3096 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
3097 {
3098 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
3099 MS_U8 constel = tps_info&0x0007;
3100 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
3101 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
3102 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
3103 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
3104
3105 printf("tps=0x%x ",tps_info);
3106
3107 switch(fft)
3108 {
3109 case 0:
3110 printf("mode = 2K,");
3111 break;
3112 case 1:
3113 printf("mode = 8K,");
3114 break;
3115 default:
3116 printf("mode = unknow,");
3117 break;
3118 }
3119 switch(constel)
3120 {
3121 case 0:
3122 printf(" QPSK, ");
3123 break;
3124 case 1:
3125 printf("16QAM, ");
3126 break;
3127 case 2:
3128 printf("64QAM, ");
3129 break;
3130 default:
3131 printf("unknow QAM, ");
3132 break;
3133 }
3134 switch(gi)
3135 {
3136 case 0:
3137 printf("GI=1/32, ");
3138 break;
3139 case 1:
3140 printf("GI=1/16, ");
3141 break;
3142 case 2:
3143 printf("GI= 1/8, ");
3144 break;
3145 case 3:
3146 printf("GI= 1/4, ");
3147 break;
3148 default:
3149 printf("unknow GI, ");
3150 break;
3151 }
3152
3153 switch(hp_cr)
3154 {
3155 case 0:
3156 printf("HP_CR=1/2, ");
3157 break;
3158 case 1:
3159 printf("HP_CR=2/3, ");
3160 break;
3161 case 2:
3162 printf("HP_CR=3/4, ");
3163 break;
3164 case 3:
3165 printf("HP_CR=5/6, ");
3166 break;
3167 case 4:
3168 printf("HP_CR=7/8, ");
3169 break;
3170 default:
3171 printf("unknow hp_cr, ");
3172 break;
3173 }
3174
3175 switch(lp_cr)
3176 {
3177 case 0:
3178 printf("LP_CR=1/2, ");
3179 break;
3180 case 1:
3181 printf("LP_CR=2/3, ");
3182 break;
3183 case 2:
3184 printf("LP_CR=3/4, ");
3185 break;
3186 case 3:
3187 printf("LP_CR=5/6, ");
3188 break;
3189 case 4:
3190 printf("LP_CR=7/8, ");
3191 break;
3192 default:
3193 printf("unknow lp_cr, ");
3194 break;
3195 }
3196
3197 printf(" Hiearchy=0x%x\n",hiearchy);
3198
3199 // printf("\n");
3200 return TRUE;
3201 }
3202 else
3203 {
3204 printf("INVALID\n");
3205 return FALSE;
3206 }
3207 }
3208
3209
3210
3211
INTERN_DVBT_Show_BER_PacketErr(void)3212 void INTERN_DVBT_Show_BER_PacketErr(void)
3213 {
3214 float f_ber = 0;
3215 MS_U16 packetErr = 0;
3216 INTERN_DVBT_GetPostViterbiBer(&f_ber);
3217 INTERN_DVBT_GetPacketErr(&packetErr);
3218
3219 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3220 return;
3221 }
3222
INTERN_DVBT_Show_Lock_Info(void)3223 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
3224 {
3225
3226 printf("[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
3227 return false;
3228 }
3229
3230
INTERN_DVBT_Show_Demod_Info(void)3231 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
3232 {
3233 MS_U8 demod_state = 0;
3234 MS_BOOL status = true;
3235 static MS_U8 counter = 0;
3236
3237 INTERN_DVBT_get_demod_state(&demod_state);
3238
3239 printf("==========[dvbt]state=%d\n",demod_state);
3240 if (demod_state < 5)
3241 {
3242 INTERN_DVBT_Show_Demod_Version();
3243 INTERN_DVBT_Show_AGC_Info();
3244 INTERN_DVBT_Show_ACI_CI();
3245 }
3246 else if(demod_state < 8)
3247 {
3248 INTERN_DVBT_Show_Demod_Version();
3249 INTERN_DVBT_Show_AGC_Info();
3250 INTERN_DVBT_Show_ACI_CI();
3251 INTERN_DVBT_Show_ChannelLength();
3252 INTERN_DVBT_Get_CFO();
3253 INTERN_DVBT_Get_SFO();
3254 INTERN_DVBT_Show_td_coeff();
3255 }
3256 else if(demod_state < 11)
3257 {
3258 INTERN_DVBT_Show_Demod_Version();
3259 INTERN_DVBT_Show_AGC_Info();
3260 INTERN_DVBT_Show_ACI_CI();
3261 INTERN_DVBT_Show_ChannelLength();
3262 INTERN_DVBT_Get_CFO();
3263 INTERN_DVBT_Get_SFO();
3264 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3265 INTERN_DVBT_Get_SYA_status();
3266 INTERN_DVBT_Show_td_coeff();
3267 }
3268 else if((demod_state == 11) && ((counter%4) == 0))
3269 {
3270 INTERN_DVBT_Show_Demod_Version();
3271 INTERN_DVBT_Show_AGC_Info();
3272 INTERN_DVBT_Show_ACI_CI();
3273 INTERN_DVBT_Show_ChannelLength();
3274 INTERN_DVBT_Get_CFO();
3275 INTERN_DVBT_Get_SFO();
3276 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3277 INTERN_DVBT_Get_SYA_status();
3278 INTERN_DVBT_Show_td_coeff();
3279 INTERN_DVBT_Show_Modulation_info();
3280 INTERN_DVBT_Show_BER_PacketErr();
3281 }
3282 else
3283 status = false;
3284
3285 printf("===========================\n");
3286 counter++;
3287
3288 return status;
3289 }
3290 #endif
3291
3292