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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "ULog.h"
108 #include "MsCommon.h"
109 #include "MsIRQ.h"
110 #include "MsOS.h"
111 //#include "apiPWS.h"
112
113 #include "MsTypes.h"
114 #include "drvBDMA.h"
115 //#include "drvIIC.h"
116 //#include "msAPI_Tuner.h"
117 //#include "msAPI_MIU.h"
118 //#include "BinInfo.h"
119 //#include "halVif.h"
120 #include "drvDMD_INTERN_DVBC.h"
121 #include "halDMD_INTERN_DVBC.h"
122 #include "halDMD_INTERN_common.h"
123 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
124 #include "InfoBlock.h"
125 #endif
126 #include "drvMMIO.h"
127 //#include "TDAG4D01A_SSI_DVBT.c"
128 #include "drvDMD_VD_MBX.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
133
134 #define TDE_REG_BASE 0x2400UL
135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00
136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00
137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00
138
139 #ifdef MS_DEBUG
140 #define DBG_INTERN_DVBC(x) x
141 #define DBG_GET_SIGNAL_DVBC(x) x
142 #define DBG_INTERN_DVBC_TIME(x) x
143 #define DBG_INTERN_DVBC_LOCK(x) x
144 #define INTERN_DVBC_INTERNAL_DEBUG 0
145 #else
146 #define DBG_INTERN_DVBC(x) //x
147 #define DBG_GET_SIGNAL_DVBC(x) //x
148 #define DBG_INTERN_DVBC_TIME(x) //x
149 #define DBG_INTERN_DVBC_LOCK(x) //x
150 #define INTERN_DVBC_INTERNAL_DEBUG 0
151 #endif
152 #define DBG_DUMP_LOAD_DSP_TIME 0
153
154
155 //#define SIGNAL_LEVEL_OFFSET 0.00f
156 //#define TAKEOVERPOINT -60.0f
157 //#define TAKEOVERRANGE 0.5f
158 //#define LOG10_OFFSET -0.21f
159 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
160 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
161
162 #define TUNER_IF 36167
163
164 #define TS_SER_C 0x00 //0: parallel 1:serial
165
166 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
167 #define TS_INV_C 0x01
168 #else
169 #define TS_INV_C 0x00
170 #endif
171
172 #define DVBC_FS 45474 //24000
173 #define CFG_ZIF 0x00 //For ZIF ,FC=0
174 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
175 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
176 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
177 #define FS_L_C (DVBC_FS&0xFF)
178 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
179 #define IQ_SWAP_C 0x00
180 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
181 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
182 // Symbol Rate: 6875 = 0x1ADB
183 // Symbol Rate: 6900 = 0x1AF4
184 // Symbol Rate: 7000 = 0x1B58
185 // Symbol Rate: 4000 = 0x0FA0
186 // Symbol Rate: 6125 = 0x17ED
187 #define SR0_H 0x1A
188 #define SR0_L 0xF4 //6900
189 #define SR1_H 0x1B
190 #define SR1_L 0x58 //7000
191 #define SR2_H 0x17
192 #define SR2_L 0xED //6125
193 #define SR3_H 0x0F
194 #define SR3_L 0xA0 //4000
195 #define SR4_H 0x1B
196 #define SR4_L 0x26 //6950
197 #define SR5_H 0x1A //0xDB
198 #define SR5_L 0xDB //0x1A //6875
199 #define SR6_H 0x1C
200 #define SR6_L 0x20 //7200
201 #define SR7_H 0x1C
202 #define SR7_L 0x52 //7250
203 #define SR8_H 0x0B
204 #define SR8_L 0xB8 //3000
205 #define SR9_H 0x03
206 #define SR9_L 0xE8 //1000
207 #define SR10_H 0x07
208 #define SR10_L 0xD0 //2000
209 #define SR11_H 0x00
210 #define SR11_L 0x00 //0000
211
212
213 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
214
215 // SAR dependent
216 #define NO_SIGNAL_TH_A 0xA3
217 // Tuner dependent
218 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
219 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
220 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
221 #define NO_SIGNAL_TH_C_H 0xff //0x00
222 #define DAGC1_REF 0x70
223 #define DAGC2_REF 0x30
224 #define AGC_REF_L 0x00
225 #define AGC_REF_H 0x06
226
227 #define INTERN_AUTO_SR_C 1
228 #define INTERN_AUTO_QAM_C 1
229
230 #define ATV_DET_EN 1
231
232 #if 0
233 MS_U8 INTERN_DVBC_DSPREG[] =
234 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
235 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
236 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
237 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
238 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
239 };
240 #else
241 MS_U8 INTERN_DVBC_DSPREG[] =
242 {
243 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
244 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
245 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
246 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
247 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
248 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
249 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
250 };
251 #endif
252 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
253
254 //-----------------------------------------------------------------------
255 /****************************************************************
256 *Local Variables *
257 ****************************************************************/
258
259 //static MS_BOOL TPSLock = 0;
260 static MS_U32 u32ChkScanTimeStartDVBC = 0;
261 static MS_U8 g_dvbc_lock = 0;
262
263 //Global Variables
264 S_CMDPKTREG gsCmdPacketDVBC;
265 //MS_U8 gCalIdacCh0, gCalIdacCh1;
266 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
267 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
268 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
269 MS_U8 INTERN_DVBC_table[] = {
270 #include "fwDMD_INTERN_DVBC.dat"
271 };
272
273 #endif
274
275 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
276 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
277 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
278 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
279 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW);
280 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
281 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
282 //MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
283
284 #if (INTERN_DVBC_INTERNAL_DEBUG)
285 void INTERN_DVBC_info(void);
286 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
287 #endif
288
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)289 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
290 {
291 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
292 MS_U8 status = TRUE;
293 MS_U16 u16DspAddr = 0;
294
295 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init\n"));
296
297 #if 0//def MS_DEBUG
298 {
299 MS_U8 u8buffer[256];
300 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Reset\n");
301 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
302 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
303
304 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
305 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
306 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
307 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
308 ULOGD("DEMOD","%x ", u8buffer[idx]);
309 ULOGD("DEMOD","\n");
310
311 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Value\n");
312 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
313 ULOGD("DEMOD","%x ", INTERN_DVBC_DSPREG[idx]);
314 ULOGD("DEMOD","\n");
315 }
316 #endif
317
318 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
319 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
320
321 // readback to confirm.
322 #ifdef MS_DEBUG
323 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
324 {
325 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
326 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
327 {
328 ULOGD("DEMOD","[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
329 }
330 }
331 #endif
332
333 if (u8DVBC_DSPReg != NULL)
334 {
335 if (1 == u8DVBC_DSPReg[0])
336 {
337 u8DVBC_DSPReg+=2;
338 for (idx = 0; idx<u8Size; idx++)
339 {
340 u16DspAddr = *u8DVBC_DSPReg;
341 u8DVBC_DSPReg++;
342 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
343 u8DVBC_DSPReg++;
344 u8Mask = *u8DVBC_DSPReg;
345 u8DVBC_DSPReg++;
346 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
347 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
348 u8DVBC_DSPReg++;
349 DBG_INTERN_DVBC(ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
350 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
351 }
352 }
353 else
354 {
355 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
356 }
357 }
358
359 #if 0//def MS_DEBUG
360 {
361 MS_U8 u8buffer[256];
362 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
363 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
364 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack\n");
365 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
366 ULOGD("DEMOD","%x ", u8buffer[idx]);
367 ULOGD("DEMOD","\n");
368 }
369 #endif
370
371 #if 0//def MS_DEBUG
372 {
373 MS_U8 u8buffer[256];
374 for (idx = 0; idx<128; idx++)
375 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
376 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
377 for (idx = 0; idx<128; idx++)
378 {
379 ULOGD("DEMOD","%x ", u8buffer[idx]);
380 if ((idx & 0xF) == 0xF) ULOGD("DEMOD","\n");
381 }
382 ULOGD("DEMOD","\n");
383 }
384 #endif
385 return status;
386 }
387
388 /***********************************************************************************
389 Subject: Command Packet Interface
390 Function: INTERN_DVBC_Cmd_Packet_Send
391 Parmeter:
392 Return: MS_BOOL
393 Remark:
394 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)395 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
396 {
397 MS_U8 status = true, indx;
398 MS_U8 reg_val, timeout = 0;
399 return TRUE;
400 // ==== Command Phase ===================
401 DBG_INTERN_DVBC(ULOGD("DEMOD","--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
402 pCmdPacket->param[0],pCmdPacket->param[1],
403 pCmdPacket->param[2],pCmdPacket->param[3],
404 pCmdPacket->param[4],pCmdPacket->param[5] ));
405
406 // wait _BIT_END clear
407 do
408 {
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
410 if((reg_val & _BIT_END) != _BIT_END)
411 {
412 break;
413 }
414 MsOS_DelayTask(5);
415 if (timeout > 200)
416 {
417 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
418 return false;
419 }
420 timeout++;
421 } while (1);
422
423 // set cmd_3:0 and _BIT_START
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
427
428
429 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
430 // wait _BIT_START clear
431 do
432 {
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
434 if((reg_val & _BIT_START) != _BIT_START)
435 {
436 break;
437 }
438 MsOS_DelayTask(10);
439 if (timeout > 200)
440 {
441 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
442 return false;
443 }
444 timeout++;
445 } while (1);
446
447 // ==== Data Phase ======================
448
449 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
450
451 for (indx = 0; indx < param_cnt; indx++)
452 {
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
454 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
455
456 // set param[indx] and _BIT_DRQ
457 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
459 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
460
461 // wait _BIT_DRQ clear
462 do
463 {
464 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
465 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
466 {
467 break;
468 }
469 MsOS_DelayTask(5);
470 if (timeout > 200)
471 {
472 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
473 return false;
474 }
475 timeout++;
476 } while (1);
477 }
478
479 // ==== End Phase =======================
480
481 // set _BIT_END to finish command
482 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
483 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
484 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
485 return status;
486 }
487
488
489 /***********************************************************************************
490 Subject: Command Packet Interface
491 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
492 Parmeter:
493 Return: MS_BOOL
494 Remark:
495 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)496 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
497 {
498 return TRUE;
499 }
500
501 /***********************************************************************************
502 Subject: SoftStop
503 Function: INTERN_DVBC_SoftStop
504 Parmeter:
505 Return: MS_BOOL
506 Remark:
507 ************************************************************************************/
508
INTERN_DVBC_SoftStop(void)509 MS_BOOL INTERN_DVBC_SoftStop ( void )
510 {
511 #if 1
512 MS_U16 u8WaitCnt=0;
513
514 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
515 {
516 ULOGD("DEMOD",">> MB Busy!\n");
517 return FALSE;
518 }
519
520 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
521
522 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
523 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
524
525 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
526 {
527 #if TEST_EMBEDED_DEMOD
528 MsOS_DelayTask(1); // << Ken 20090629
529 #endif
530 if (u8WaitCnt++ >= 0x7FFF)
531 {
532 ULOGD("DEMOD",">> DVBC SoftStop Fail!\n");
533 return FALSE;
534 }
535 }
536
537 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
538 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
539 #endif
540 return TRUE;
541 }
542
543
544 /***********************************************************************************
545 Subject: Reset
546 Function: INTERN_DVBC_Reset
547 Parmeter:
548 Return: MS_BOOL
549 Remark:
550 ************************************************************************************/
551 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)552 MS_BOOL INTERN_DVBC_Reset ( void )
553 {
554 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_reset\n"));
555
556 //DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime()));
557
558 // INTERN_DVBC_SoftStop();
559
560
561 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
562 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
563 MsOS_DelayTask(5);
564 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
565 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
566 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
567 MsOS_DelayTask(5);
568
569 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
571
572 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
573 g_dvbc_lock = 0;
574
575 return TRUE;
576 }
577
578 /***********************************************************************************
579 Subject: Exit
580 Function: INTERN_DVBC_Exit
581 Parmeter:
582 Return: MS_BOOL
583 Remark:
584 ************************************************************************************/
INTERN_DVBC_Exit(void)585 MS_BOOL INTERN_DVBC_Exit ( void )
586 {
587
588 return INTERN_DVBC_SoftStop();
589 }
590
591 /***********************************************************************************
592 Subject: Load DSP code to chip
593 Function: INTERN_DVBC_LoadDSPCode
594 Parmeter:
595 Return: MS_BOOL
596 Remark:
597 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)598 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
599 {
600 MS_U8 udata = 0x00;
601 MS_U16 i;
602 MS_U16 fail_cnt=0;
603
604 #if (DBG_DUMP_LOAD_DSP_TIME==1)
605 MS_U32 u32Time;
606 #endif
607
608
609 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
610 BININFO BinInfo;
611 MS_BOOL bResult;
612 MS_U32 u32GEAddr;
613 MS_U8 Data;
614 MS_S8 op;
615 MS_U32 srcaddr;
616 MS_U32 len;
617 MS_U32 SizeBy4K;
618 MS_U16 u16Counter=0;
619 MS_U8 *pU8Data;
620 #endif
621
622 #if 0
623 if(HAL_DMD_RIU_ReadByte(0x101E3E))
624 {
625 ULOGD("DEMOD","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
626 return FALSE;
627 }
628 #endif
629
630 // MDrv_Sys_DisableWatchDog();
631
632
633 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
634 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
635 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
636 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
637 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
638 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
639
640 //// Load code thru VDMCU_IF ////
641 DBG_INTERN_DVBC(ULOGD("DEMOD",">Load Code.....\n"));
642 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
643 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
644 {
645 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
646 }
647 #else
648 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
649 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
650 if ( bResult != PASS )
651 {
652 return FALSE;
653 }
654 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
655
656 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
657 InfoBlock_Flash_2_Checking_Start(&BinInfo);
658 #endif
659
660 #if OBA2
661 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
662 #else
663 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
664 #endif
665
666 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
667 InfoBlock_Flash_2_Checking_End(&BinInfo);
668 #endif
669
670 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
671 SizeBy4K=BinInfo.B_Len/0x1000;
672 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
673
674 #if (DBG_DUMP_LOAD_DSP_TIME==1)
675 u32Time = msAPI_Timer_GetTime0();
676 #endif
677
678 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
679
680 for (i=0;i<=SizeBy4K;i++)
681 {
682 if(i==SizeBy4K)
683 len=BinInfo.B_Len%0x1000;
684 else
685 len=0x1000;
686
687 srcaddr = u32GEAddr+(0x1000*i);
688 //ULOGD("DEMOD","\t i = %08X\n", i);
689 //ULOGD("DEMOD","\t len = %08X\n", len);
690 op = 1;
691 u16Counter = 0 ;
692 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
693 while(len--)
694 {
695 u16Counter ++ ;
696 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
697 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
698 #if OBA2
699 pU8Data = (MS_U8 *)(srcaddr);
700 #else
701 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
702 #endif
703 Data = *pU8Data;
704
705 #if 0
706 if(u16Counter < 0x100)
707 ULOGD("DEMOD","0x%bx,", Data);
708 #endif
709 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
710
711 srcaddr += op;
712 }
713 // ULOGD("DEMOD","\n\n\n");
714 }
715
716 #if (DBG_DUMP_LOAD_DSP_TIME==1)
717 ULOGD("DEMOD","------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
718 #endif
719
720 #endif
721
722 //// Content verification ////
723 DBG_INTERN_DVBC(ULOGD("DEMOD",">Verify Code...\n"));
724
725 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
726 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
727
728 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
729 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
730 {
731 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
732 if (udata != INTERN_DVBC_table[i])
733 {
734 ULOGD("DEMOD",">fail add = 0x%x\n", i);
735 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBC_table[i]);
736 ULOGD("DEMOD",">data = 0x%x\n", udata);
737
738 if (fail_cnt > 10)
739 {
740 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
741 return false;
742 }
743 fail_cnt++;
744 }
745 }
746 #else
747 for (i=0;i<=SizeBy4K;i++)
748 {
749 if(i==SizeBy4K)
750 len=BinInfo.B_Len%0x1000;
751 else
752 len=0x1000;
753
754 srcaddr = u32GEAddr+(0x1000*i);
755 //ULOGD("DEMOD","\t i = %08LX\n", i);
756 //ULOGD("DEMOD","\t len = %08LX\n", len);
757 op = 1;
758 u16Counter = 0 ;
759 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
760 while(len--)
761 {
762 u16Counter ++ ;
763 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
764 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
765 #if OBA2
766 pU8Data = (MS_U8 *)(srcaddr);
767 #else
768 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
769 #endif
770 Data = *pU8Data;
771
772 #if 0
773 if(u16Counter < 0x100)
774 ULOGD("DEMOD","0x%bx,", Data);
775 #endif
776 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
777 if (udata != Data)
778 {
779 ULOGD("DEMOD",">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
780 ULOGD("DEMOD",">code = 0x%x\n", Data);
781 ULOGD("DEMOD",">data = 0x%x\n", udata);
782
783 if (fail_cnt++ > 10)
784 {
785 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
786 return false;
787 }
788 }
789
790 srcaddr += op;
791 }
792 // ULOGD("DEMOD","\n\n\n");
793 }
794 #endif
795
796 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
797 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
798 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
799 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
800
801 DBG_INTERN_DVBC(ULOGD("DEMOD",">DSP Loadcode done."));
802 //while(load_data_variable);
803 #if 0
804 INTERN_DVBC_Config(6875, 128, 36125, 0,1);
805 INTERN_DVBC_Active(ENABLE);
806 while(1);
807 #endif
808 HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
809
810 return TRUE;
811 }
812
813 /***********************************************************************************
814 Subject: DVB-T CLKGEN initialized function
815 Function: INTERN_DVBC_Power_On_Initialization
816 Parmeter:
817 Return: MS_BOOL
818 Remark:
819 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)820 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
821 {
822 // MS_U8 temp_val;
823 HAL_DMD_RIU_WriteByte(0x103c0e, 0x00); //mux from DMD MCU to HK.
824 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
825 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
826
827 // ============================================================== ADC SYNC FLOW START
828 // DMD_ANA_ADC_SYNC CLK_W
829 // [4:0] : reg_ckg_adcd
830 // [0] : disable clock = 1'b1
831 // [1] : invert clock
832 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b01, 16'h0001);
833 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b01, 16'h0001);
834 HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
835 // ============================================================== ADC SYNC FLOW END
836
837 // CLK_DMDMCU clock setting
838 // [0] disable clock
839 // [1] invert clock
840 // [4:2]
841 // 000:170 MHz(MPLL_DIV_BUf)
842 // 001:160MHz
843 // 010:144MHz
844 // 011:123MHz
845 // 100:108MHz
846 // 101:mem_clcok
847 // 110:mem_clock div 2
848 // 111:select XTAL
849 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
850 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
851
852 // set parallet ts clock
853 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
854 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
855 // wriu 0x103301 0x06
856 // wriu 0x103300 0x19
857
858
859 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
860 HAL_DMD_RIU_WriteByte(0x103301,0x07);
861 HAL_DMD_RIU_WriteByte(0x103300,0x13);
862
863 // enable atsc, DVBTC ts clock
864 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
865 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
866 // wriu 0x103309 0x00
867 // wriu 0x103308 0x00
868
869 HAL_DMD_RIU_WriteByte(0x103309,0x00);
870 HAL_DMD_RIU_WriteByte(0x103308,0x00);
871
872 // enable dvbc adc clock
873 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
874 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
875 // wriu 0x103315 0x00
876 // wriu 0x103314 0x00
877
878 HAL_DMD_RIU_WriteByte(0x103315,0x00);
879 HAL_DMD_RIU_WriteByte(0x103314,0x00);
880
881 // Reset TS divider
882 HAL_DMD_RIU_WriteByte(0x103302,0x01);
883 HAL_DMD_RIU_WriteByte(0x103302,0x00);
884
885 // ==============================================================
886 // Start demod_0 CLKGEN setting ......
887 // ==============================================================
888 // ============================================================== ADC SYNC FLOW START
889 // ADC_SYNC CLK_R
890 // enable atsc_adcd_sync clock
891 // [3:0] : reg_ckg_atsc_adcd_sync
892 // [0] : disable clock
893 // [1] : invert clock
894 // [3:2]: Select clock source
895 // 00: clk_dmdadc_sync
896 // 01: 1'b0
897 // 10: 1'b0
898 // 11: DFT_CLK
899 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
900 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
901 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
902 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
903
904 // ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
905 // enable dvbc adc clock
906 // [3:0]: reg_ckg_dvbtc_adc
907 // [0] : disable clock
908 // [1] : invert clock = 1'b0
909 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
910 // 00: clk_dmdadc
911 // 01: clk_dmdadc_div2
912 // 10: clk_dmdadc_div4
913 // 11: DFT_CLK
914 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
915 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
916 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
917 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
918
919 // DMD_ANA_ADC_SYNC CLK_W
920 // [4:0] : reg_ckg_adcd
921 // [0] : disable clock = 1'b0
922 // [1] : invert clock
923 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b01, 16'h0000);
924 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b01, 16'h0000);
925 HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
926 // ============================================================== ADC SYNC FLOW END
927
928 HAL_DMD_RIU_WriteByte(0x152929,0x00);
929 HAL_DMD_RIU_WriteByte(0x152928,0x04);
930
931 HAL_DMD_RIU_WriteByte(0x152903,0x04);
932 HAL_DMD_RIU_WriteByte(0x152902,0x04);
933
934 HAL_DMD_RIU_WriteByte(0x152905,0x00);
935 HAL_DMD_RIU_WriteByte(0x152904,0x00);
936
937 HAL_DMD_RIU_WriteByte(0x152907,0x04);
938 HAL_DMD_RIU_WriteByte(0x152906,0x00);
939
940 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
941 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
942
943
944 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
945 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
946
947 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
948 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
949
950 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
951 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
952
953 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
954 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
955
956 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
957 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
958
959 HAL_DMD_RIU_WriteByte(0x111f69,0x88);
960 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
961
962 HAL_DMD_RIU_WriteByte(0x111f6b,0x01);
963 HAL_DMD_RIU_WriteByte(0x111f6a,0x11);
964
965 HAL_DMD_RIU_WriteByte(0x152923,0x00);
966 HAL_DMD_RIU_WriteByte(0x152922,0x44);
967
968 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
969 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
970
971 HAL_DMD_RIU_WriteByte(0x15296d,0x00);
972 HAL_DMD_RIU_WriteByte(0x15296c,0x81);
973
974 HAL_DMD_RIU_WriteByte(0x152971,0x1c);
975 HAL_DMD_RIU_WriteByte(0x152970,0xc1);
976
977 HAL_DMD_RIU_WriteByte(0x152977,0x08);
978 HAL_DMD_RIU_WriteByte(0x152976,0x08);
979
980 HAL_DMD_RIU_WriteByte(0x152981,0x00);
981 HAL_DMD_RIU_WriteByte(0x152980,0x00);
982
983 HAL_DMD_RIU_WriteByte(0x152983,0x00);
984 HAL_DMD_RIU_WriteByte(0x152982,0x00);
985
986 HAL_DMD_RIU_WriteByte(0x152985,0x00);
987 HAL_DMD_RIU_WriteByte(0x152984,0x00);
988
989 HAL_DMD_RIU_WriteByte(0x152987,0x00);
990 HAL_DMD_RIU_WriteByte(0x152986,0x00);
991
992 HAL_DMD_RIU_WriteByte(0x111feb,0x18);
993 HAL_DMD_RIU_WriteByte(0x111fea,0x14);
994
995 HAL_DMD_RIU_WriteByte(0x111f74,0x10);
996
997 HAL_DMD_RIU_WriteByte(0x111f77,0x01);
998
999 HAL_DMD_RIU_WriteByte(0x111f79,0x41);
1000 HAL_DMD_RIU_WriteByte(0x111f78,0x10);
1001
1002 HAL_DMD_RIU_WriteByte(0x111fe0,0x08);
1003
1004 HAL_DMD_RIU_WriteByte(0x111fe3,0x08);
1005 HAL_DMD_RIU_WriteByte(0x111fe2,0x10);
1006
1007 HAL_DMD_RIU_WriteByte(0x111ff0,0x08);
1008
1009 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
1010
1011 HAL_DMD_RIU_WriteByte(0x101E39, 0x03); //mux from DMD MCU to HK.
1012
1013 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1014 }
1015
1016
1017 /***********************************************************************************
1018 Subject: Power on initialized function
1019 Function: INTERN_DVBC_Power_On_Initialization
1020 Parmeter:
1021 Return: MS_BOOL
1022 Remark:
1023 ************************************************************************************/
1024
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)1025 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
1026 {
1027 MS_U8 status = true;
1028 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_Power_On_Initialization\n"));
1029
1030 #if defined(PWS_ENABLE)
1031 Mapi_PWS_Stop_VDMCU();
1032 #endif
1033
1034 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
1035 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1036 //// Firmware download //////////
1037 ULOGD("DEMOD","INTERN_DVBC Load DSP...\n");
1038 //MsOS_DelayTask(100);
1039
1040 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x04) // DVBT = BIT1 -> 0x02
1041 {
1042 if (INTERN_DVBC_LoadDSPCode() == FALSE)
1043 {
1044 ULOGD("DEMOD","DVB-C Load DSP Code Fail\n");
1045 return FALSE;
1046 }
1047 else
1048 {
1049 ULOGD("DEMOD","DVB-C Load DSP Code OK\n");
1050 }
1051 }
1052
1053 status &= INTERN_DVBC_Reset();
1054
1055 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
1056
1057 return status;
1058 }
1059 /************************************************************************************************
1060 Subject: Driving control
1061 Function: INTERN_DVBC_Driving_Control
1062 Parmeter: bInversionEnable : TRUE For High
1063 Return: void
1064 Remark:
1065 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)1066 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
1067 {
1068 MS_U8 u8Temp;
1069
1070 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1071
1072 if (bEnable)
1073 {
1074 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1075 }
1076 else
1077 {
1078 u8Temp = u8Temp & (~0x01);
1079 }
1080
1081 DBG_INTERN_DVBC(ULOGD("DEMOD","---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1082 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1083 }
1084 /************************************************************************************************
1085 Subject: Clk Inversion control
1086 Function: INTERN_DVBC_Clk_Inversion_Control
1087 Parmeter: bInversionEnable : TRUE For Inversion Action
1088 Return: void
1089 Remark:
1090 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)1091 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1092 {
1093 MS_U8 u8Temp;
1094
1095 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1096
1097 if (bInversionEnable)
1098 {
1099 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1100 }
1101 else
1102 {
1103 u8Temp = u8Temp & (~0x02);
1104 }
1105
1106 DBG_INTERN_DVBC(ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp));
1107 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1108 }
1109 /************************************************************************************************
1110 Subject: Transport stream serial/parallel control
1111 Function: INTERN_DVBC_Serial_Control
1112 Parmeter: bEnable : TRUE For serial
1113 Return: MS_BOOL :
1114 Remark:
1115 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1116 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1117 {
1118 MS_U8 status = true;
1119 return status;
1120
1121
1122 }
1123
1124 /************************************************************************************************
1125 Subject: TS1 output control
1126 Function: INTERN_DVBC_PAD_TS1_Enable
1127 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1128 Return: void
1129 Remark:
1130 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)1131 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
1132 {
1133 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_TS1_Enable... \n"));
1134
1135 if(flag) // PAD_TS1 Enable TS CLK PAD
1136 {
1137 //ULOGD("DEMOD","=== TS1_Enable ===\n");
1138 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1139 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1140 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1141 }
1142 else // PAD_TS1 Disable TS CLK PAD
1143 {
1144 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1145 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1146 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1147 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1148 }
1149 }
1150
1151 /************************************************************************************************
1152 Subject: channel change config
1153 Function: INTERN_DVBC_Config
1154 Parmeter: BW: bandwidth
1155 Return: MS_BOOL :
1156 Remark:
1157 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1158 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1159 {
1160
1161 MS_U8 status = true;
1162 MS_U8 reg_symrate_l, reg_symrate_h;
1163 //MS_U16 u16Fc = 0;
1164 // force
1165 // u16SymbolRate = 0;
1166 // eQamMode = DMD_DVBC_QAMAUTO;
1167
1168 pu16_symbol_rate_list = pu16_symbol_rate_list;
1169 u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1170
1171 //DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk));
1172 //DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime()));
1173
1174 if (u8TSClk == 0xFF) u8TSClk=0x13;
1175
1176 /*
1177 switch(u32IFFreq)
1178 {
1179 case 36125:
1180 case 36167:
1181 case 36000:
1182 case 6000:
1183 case 4560:
1184 //u16Fc = DVBC_FS - u32IFFreq;
1185 DBG_INTERN_DVBC(ULOGD("DEMOD","Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1186 break;
1187 case 44000:
1188 default:
1189 ULOGD("DEMOD","IF frequency not supported\n");
1190 status = false;
1191 break;
1192 }
1193 */
1194
1195 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1196 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1197
1198 status &= INTERN_DVBC_Reset();
1199
1200 if (eQamMode == DMD_DVBC_QAMAUTO)
1201 {
1202 DBG_INTERN_DVBC(ULOGD("DEMOD","DMD_DVBC_QAMAUTO\n"));
1203 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1204 // give default value.
1205 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1206 }
1207 else
1208 {
1209 DBG_INTERN_DVBC(ULOGD("DEMOD","DMD_DVBC_QAM %d\n", eQamMode));
1210 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1211 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1212 }
1213 // auto symbol rate enable/disable
1214 if (u16SymbolRate == 0)
1215 {
1216 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1217 }
1218 else
1219 {
1220 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1221 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1222 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1223 }
1224 // TS mode
1225 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1226
1227 // IQ Swap
1228 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1229
1230 // Fc
1231 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1232 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1233 // Lif
1234 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1235 // Fif
1236 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1237 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1238
1239 //// INTERN_DVBC system init: DVB-C //////////
1240 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1241
1242 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1243 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1244
1245 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1246 INTERN_DVBC_Show_Demod_Version();
1247 #endif
1248
1249 return status;
1250 }
1251 /************************************************************************************************
1252 Subject: enable hw to lock channel
1253 Function: INTERN_DVBC_Active
1254 Parmeter: bEnable
1255 Return: MS_BOOL
1256 Remark:
1257 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1258 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1259 {
1260 MS_U8 status = true;
1261
1262 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_active\n"));
1263
1264 //// INTERN_DVBC Finite State Machine on/off //////////
1265 #if 0
1266 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1267
1268 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1269 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1270 #else
1271 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1272 #endif
1273
1274 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1275 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1276 return status;
1277 }
1278
1279
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,MS_U32 u32CurrRFPowerDbm,MS_U32 u32NoChannelRFPowerDbm,MS_U32 u32TimeInterval)1280 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1281 {
1282 MS_U16 u16Address = 0;
1283 MS_U8 cData = 0;
1284 MS_U8 cBitMask = 0;
1285
1286
1287 if (u32CurrRFPowerDbm < 1000)
1288 {
1289 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1290 {
1291 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1292 if (cData > 5)
1293 {
1294 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1295 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1296 }
1297 else
1298 {
1299 if ((u32CurrRFPowerDbm<u32NoChannelRFPowerDbm) && u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000)
1300 {
1301 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1302 }
1303 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1304 {
1305 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1306 #ifdef MS_DEBUG
1307 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1308 #endif
1309 return TRUE;
1310 }
1311 }
1312 #ifdef MS_DEBUG
1313 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%d Threshold:%d Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, u32CurrRFPowerDbm, u32NoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1314 #endif
1315 }
1316 }
1317
1318 {
1319 switch( eType )
1320 {
1321 case DMD_DVBC_GETLOCK_FEC_LOCK:
1322 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1323 #if (INTERN_DVBC_INTERNAL_DEBUG)
1324 INTERN_DVBC_info();
1325 #endif
1326 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_GetLock FSM 0x%x\n",cData));
1327 if (cData == 0x0C)
1328 {
1329 if(g_dvbc_lock == 0)
1330 {
1331 g_dvbc_lock = 1;
1332 DBG_INTERN_DVBC(ULOGD("DEMOD","[T12][DVBC]lock++++\n"));
1333
1334 }
1335 return TRUE;
1336 }
1337 else
1338 {
1339 if(g_dvbc_lock == 1)
1340 {
1341 g_dvbc_lock = 0;
1342 DBG_INTERN_DVBC(ULOGD("DEMOD","[T12][DVBC]unlock----\n"));
1343 }
1344 return FALSE;
1345 }
1346 break;
1347
1348 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1349 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1350 cBitMask = BIT(1);
1351 break;
1352
1353 case DMD_DVBC_GETLOCK_DCR_LOCK:
1354 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1355 cBitMask = BIT(0);
1356 break;
1357
1358 case DMD_DVBC_GETLOCK_AGC_LOCK:
1359 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1360 cBitMask = BIT(0);
1361 break;
1362
1363 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1364 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1365 cBitMask = BIT(2)|BIT(3)|BIT(4);
1366 #ifdef MS_DEBUG
1367 {
1368 MS_U8 reg_frz=0, FSM=0;
1369 MS_U16 u16Timer=0;
1370 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1371 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1372 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1373 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1374 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1375 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1376 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1377 u16Timer=(u16Timer<<8)+reg_frz;
1378 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1379 u16Timer=(u16Timer<<8)+reg_frz;
1380 ULOGD("DEMOD","DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1381 }
1382 #endif
1383 break;
1384
1385 case DMD_DVBC_GETLOCK_ATV_DETECT:
1386 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1387 cBitMask = BIT(1); // check atv
1388 break;
1389
1390 case DMD_DVBC_GETLOCK_TR_LOCK:
1391 #if 0 // 20111108 temporarily solution
1392 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
1393 cBitMask = BIT(4);
1394 break;
1395 #endif
1396 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1397 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1398 cBitMask = BIT(4);
1399 break;
1400
1401 default:
1402 return FALSE;
1403 }
1404
1405 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1406 return FALSE;
1407
1408 if ((cData & cBitMask) != 0)
1409 {
1410 return TRUE;
1411 }
1412
1413 return FALSE;
1414 }
1415
1416 return FALSE;
1417 }
1418
1419 /****************************************************************************
1420 Subject: To get the Post viterbi BER
1421 Function: INTERN_DVBC_GetPostViterbiBer
1422 Parmeter: Quility
1423 Return: E_RESULT_SUCCESS
1424 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1425 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1426 We will not read the Period, and have the "/256/8"
1427 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg)1428 MS_BOOL INTERN_DVBC_GetPostViterbiBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg)
1429 {
1430 MS_BOOL status = true;
1431 MS_U8 reg = 0, reg_frz = 0;
1432 //MS_U16 BitErrPeriod;
1433 //MS_U32 BitErr;
1434 //MS_U16 PktErr;
1435
1436 /////////// Post-Viterbi BER /////////////
1437
1438 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1441
1442 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1443 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1445 *BitErrPeriod_reg = reg;
1446
1447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1448 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8)|reg;
1449
1450 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1451 // 0x6b [15:8] reg_bit_err_num_15_8
1452 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1453 // 0x6d [15:8] reg_bit_err_num_31_24
1454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1455 *BitErr_reg = reg;
1456
1457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1458 *BitErr_reg = (*BitErr_reg << 8)|reg;
1459
1460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1461 *BitErr_reg = (*BitErr_reg << 8)|reg;
1462
1463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1464 *BitErr_reg = (*BitErr_reg << 8)|reg;
1465
1466
1467 //INTERN_DVBC_GetPacketErr(&PktErr);
1468
1469 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1470 reg_frz=reg_frz&(~0x03);
1471 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1472 /*
1473 if (BitErrPeriod == 0 ) //protect 0
1474 BitErrPeriod = 1;
1475
1476 if (BitErr <=0 )
1477 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1478 else
1479 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1480
1481 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1482 */
1483 return status;
1484 }
1485
1486 /****************************************************************************
1487 Subject: To get the Packet error
1488 Function: INTERN_DVBC_GetPacketErr
1489 Parmeter: pktErr
1490 Return: E_RESULT_SUCCESS
1491 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1492 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1493 We will not read the Period, and have the "/256/8"
1494 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1495 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1496 {
1497 MS_BOOL status = true;
1498 MS_U8 reg = 0, reg_frz = 0;
1499 MS_U16 PktErr;
1500
1501 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1503 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1504
1505 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1506 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1507 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1508 PktErr = reg;
1509
1510 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1511 PktErr = (PktErr << 8)|reg;
1512
1513 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1514 reg_frz=reg_frz&(~0x03);
1515 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1516
1517 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","INTERN_DVBC PktErr = %d \n ", (int)PktErr));
1518
1519 *pktErr = PktErr;
1520
1521 return status;
1522 }
1523
1524
1525 /****************************************************************************
1526 Subject: Read the signal to noise ratio (SNR)
1527 Function: INTERN_DVBC_GetSNR
1528 Parmeter: None
1529 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1530 Remark:
1531 *****************************************************************************/
INTERN_DVBC_GetSNR(MS_U16 * snr_reg)1532 MS_BOOL INTERN_DVBC_GetSNR(MS_U16 *snr_reg)
1533 {
1534 MS_BOOL status = true;
1535 MS_U8 u8Data = 0, reg_frz = 0;
1536 // MS_U8 freeze = 0;
1537 //MS_U16 noisepower = 0;
1538
1539 //if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1540 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200*10, -200*10, 0) )
1541 {
1542 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1545
1546 // read vk
1547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data);
1548 //noisepower = u8Data;
1549 *snr_reg = u8Data;
1550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data);
1551 //noisepower = (noisepower<<8)|u8Data;
1552 *snr_reg = ((*snr_reg)<<8)|u8Data;
1553
1554 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1555 reg_frz=reg_frz&(~0x01);
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1557
1558 //if(noisepower == 0x0000)
1559 // noisepower = 0x0001;
1560 if(*snr_reg == 0x0000)
1561 *snr_reg = 0x0001;
1562 /*
1563 #ifdef MSOS_TYPE_LINUX
1564 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1565 #else
1566 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1567 #endif
1568 */
1569 }
1570 else
1571 {
1572 *snr_reg = 0;
1573 }
1574 return status;
1575
1576
1577 }
1578
INTERN_DVBC_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)1579 MS_BOOL INTERN_DVBC_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
1580 {
1581 MS_BOOL status = true;
1582
1583 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
1584
1585 return status;
1586 }
1587
1588 //waiting mark
1589 #if(0)
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue)1590 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
1591 {
1592 MS_BOOL status = true;
1593 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1594 DMD_DVBC_MODULATION_TYPE Qam_mode;
1595
1596 DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi)));
1597
1598 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1599 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1600 /* Actually, it's more reasonable, that signal level depended on cable input power level
1601 * thougth the signal isn't dvb-t signal.
1602 */
1603 // use pointer of IFAGC table to identify
1604 // case 1: RFAGC from SAR, IFAGC controlled by demod
1605 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1606 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1607 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
1608 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1609 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1610 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
1611 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
1612
1613 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1614
1615 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
1616 {
1617 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
1618 }
1619 else
1620 {
1621 ch_power_db_rel = -100.0f;
1622 }
1623
1624 if(ch_power_db_rel <= -85.0f)
1625 {*strength = 0;}
1626 else if (ch_power_db_rel <= -80.0f)
1627 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
1628 else if (ch_power_db_rel <= -75.0f)
1629 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
1630 else if (ch_power_db_rel <= -70.0f)
1631 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
1632 else if (ch_power_db_rel <= -65.0f)
1633 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
1634 else if (ch_power_db_rel <= -55.0f)
1635 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
1636 else if (ch_power_db_rel <= -45.0f)
1637 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
1638 else
1639 {*strength = 100;}
1640
1641 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
1642 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength));
1643
1644 return status;
1645 }
1646 #endif
1647
1648 /****************************************************************************
1649 Subject: To get the DVT Signal quility
1650 Function: INTERN_DVBC_GetSignalQuality
1651 Parmeter: Quility
1652 Return: E_RESULT_SUCCESS
1653 E_RESULT_FAILURE
1654 Remark: Here we have 4 level range
1655 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1656 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1657 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1658 <4>.4th Range => Quality <10
1659 *****************************************************************************/
1660 //waiting mark
1661 /*
1662 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
1663 {
1664
1665 float fber;
1666 float log_ber;
1667 MS_BOOL status = true;
1668 DMD_DVBC_MODULATION_TYPE Qam_mode;
1669 float f_snr;
1670
1671 fRFPowerDbm = fRFPowerDbm;
1672 status &= INTERN_DVBC_GetSNR(&f_snr);
1673 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
1674 {
1675 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
1676 {
1677 DBG_INTERN_DVBC(ULOGD("DEMOD","\nGetPostViterbiBer Fail!"));
1678 return FALSE;
1679 }
1680
1681 // log_ber = log10(fber)
1682 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
1683
1684 DBG_INTERN_DVBC(ULOGD("DEMOD","\nLog(BER) = %f",log_ber));
1685 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1686 if (Qam_mode == DMD_DVBC_QAM16)
1687 {
1688 if(log_ber <= (-5.5f))
1689 *quality = 100;
1690 else if(log_ber <= (-5.1f))
1691 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
1692 else if(log_ber <= (-4.9f))
1693 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1694 else if(log_ber <= (-4.5f))
1695 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
1696 else if(log_ber <= (-3.7f))
1697 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
1698 else if(log_ber <= (-3.2f))
1699 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1700 else if(log_ber <= (-2.9f))
1701 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1702 else if(log_ber <= (-2.5f))
1703 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
1704 else if(log_ber <= (-2.2f))
1705 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
1706 else if(log_ber <= (-2.0f))
1707 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1708 else
1709 *quality = 0;
1710 }
1711 else if (Qam_mode == DMD_DVBC_QAM32)
1712 {
1713 if(log_ber <= (-5.0f))
1714 *quality = 100;
1715 else if(log_ber <= (-4.7f))
1716 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
1717 else if(log_ber <= (-4.5f))
1718 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
1719 else if(log_ber <= (-3.8f))
1720 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
1721 else if(log_ber <= (-3.5f))
1722 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
1723 else if(log_ber <= (-3.0f))
1724 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
1725 else if(log_ber <= (-2.7f))
1726 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
1727 else if(log_ber <= (-2.4f))
1728 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1729 else if(log_ber <= (-2.2f))
1730 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1731 else if(log_ber <= (-2.0f))
1732 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1733 else
1734 *quality = 0;
1735 }
1736 else if (Qam_mode == DMD_DVBC_QAM64)
1737 {
1738 if(log_ber <= (-5.4f))
1739 *quality = 100;
1740 else if(log_ber <= (-5.1f))
1741 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
1742 else if(log_ber <= (-4.9f))
1743 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1744 else if(log_ber <= (-4.3f))
1745 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
1746 else if(log_ber <= (-3.7f))
1747 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
1748 else if(log_ber <= (-3.2f))
1749 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1750 else if(log_ber <= (-2.9f))
1751 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1752 else if(log_ber <= (-2.4f))
1753 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
1754 else if(log_ber <= (-2.2f))
1755 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1756 else if(log_ber <= (-2.05f))
1757 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
1758 else
1759 *quality = 0;
1760 }
1761 else if (Qam_mode == DMD_DVBC_QAM128)
1762 {
1763 if(log_ber <= (-5.1f))
1764 *quality = 100;
1765 else if(log_ber <= (-4.9f))
1766 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1767 else if(log_ber <= (-4.7f))
1768 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
1769 else if(log_ber <= (-4.1f))
1770 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
1771 else if(log_ber <= (-3.5f))
1772 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
1773 else if(log_ber <= (-3.1f))
1774 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1775 else if(log_ber <= (-2.7f))
1776 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1777 else if(log_ber <= (-2.5f))
1778 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
1779 else if(log_ber <= (-2.06f))
1780 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
1781 //else if(log_ber <= (-2.05))
1782 else
1783 {
1784 if (f_snr >= 27.2f)
1785 *quality = 20;
1786 else if (f_snr >= 25.1f)
1787 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
1788 else
1789 *quality = 0;
1790 }
1791 }
1792 else //256QAM
1793 {
1794 if(log_ber <= (-4.8f))
1795 *quality = 100;
1796 else if(log_ber <= (-4.6f))
1797 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
1798 else if(log_ber <= (-4.4f))
1799 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
1800 else if(log_ber <= (-4.0f))
1801 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
1802 else if(log_ber <= (-3.5f))
1803 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
1804 else if(log_ber <= (-3.1f))
1805 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1806 else if(log_ber <= (-2.7f))
1807 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1808 else if(log_ber <= (-2.4f))
1809 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1810 else if(log_ber <= (-2.06f))
1811 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
1812 //else if(log_ber <= (-2.05))
1813 else
1814 {
1815 if (f_snr >= 29.6f)
1816 *quality = 20;
1817 else if (f_snr >= 27.3f)
1818 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
1819 else
1820 *quality = 0;
1821 }
1822 }
1823 }
1824 else
1825 {
1826 *quality = 0;
1827 }
1828
1829 //DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
1830 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","BER = %8.3e\n", fber));
1831 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","Signal Quility = %d\n", *quality));
1832 return TRUE;
1833 }
1834 #endif
1835 */
1836
1837 /****************************************************************************
1838 Subject: To get the Cell ID
1839 Function: INTERN_DVBC_Get_CELL_ID
1840 Parmeter: point to return parameter cell_id
1841
1842 Return: TRUE
1843 FALSE
1844 Remark:
1845 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)1846 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
1847 {
1848 MS_BOOL status = true;
1849 MS_U8 value1 = 0;
1850 MS_U8 value2 = 0;
1851
1852 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
1853 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
1854
1855 *cell_id = ((MS_U16)value1<<8)|value2;
1856 return status;
1857 }
1858
1859 /****************************************************************************
1860 Subject: To get the DVBC Carrier Freq Offset
1861 Function: INTERN_DVBC_Get_FreqOffset
1862 Parmeter: Frequency offset (in KHz), bandwidth
1863 Return: E_RESULT_SUCCESS
1864 E_RESULT_FAILURE
1865 Remark:
1866 *****************************************************************************/
1867 #if(1)
INTERN_DVBC_Get_FreqOffset(MS_U32 * config_Fc_reg,MS_U32 * Fc_over_Fs_reg,MS_U16 * Cfo_offset_reg,MS_U8 u8BW)1868 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW)
1869 {
1870 MS_U8 reg_frz = 0, reg = 0;
1871 MS_BOOL status = TRUE;
1872
1873 // no use.
1874 u8BW = u8BW;
1875
1876 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_Get_FreqOffset\n"));
1877
1878 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1880 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1881
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, ®);
1883 *config_Fc_reg = reg;
1884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, ®);
1885 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, ®);
1887 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, ®);
1889 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
1890
1891 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1892 reg_frz=reg_frz&(~0x01);
1893 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1894
1895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
1896 *Fc_over_Fs_reg = reg;
1897 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
1898 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
1899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
1900 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
1901 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
1902 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
1903
1904 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
1905 *Cfo_offset_reg = reg;
1906 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
1907 *Cfo_offset_reg = (*Cfo_offset_reg<<8)|reg;
1908
1909 //waiting mark
1910 /*
1911 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
1912
1913 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
1914
1915 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
1916
1917 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
1918
1919 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
1920 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
1921 FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc));
1922
1923 *pFreqOff = FreqCfo_offset;
1924 */
1925 return status;
1926 }
1927 #endif
1928
1929
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)1930 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
1931 {
1932
1933 bPowerOn = bPowerOn;
1934 }
1935
INTERN_DVBC_Power_Save(void)1936 MS_BOOL INTERN_DVBC_Power_Save(void)
1937 {
1938
1939 return TRUE;
1940 }
1941
1942 /****************************************************************************
1943 Subject: To get the current modulation type at the DVB-C Demod
1944 Function: INTERN_DVBC_GetCurrentModulationType
1945 Parmeter: pointer for return QAM type
1946
1947 Return: TRUE
1948 FALSE
1949 Remark:
1950 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)1951 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
1952 {
1953 MS_U8 u8Data=0;
1954
1955 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_GetCurrentModulationType\n"));
1956
1957
1958 MDrv_SYS_DMD_VD_MBX_ReadReg(0x9cc4, &u8Data);
1959
1960
1961
1962 //ULOGD("DEMOD","@@@@@@ 0x9cc4 pQAMMode = %d \n",u8Data&0x07);
1963
1964 switch(u8Data&0x07)
1965 {
1966 case 0:
1967 *pQAMMode = DMD_DVBC_QAM16;
1968 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=16\n"));
1969 return TRUE;
1970 break;
1971 case 1:
1972 *pQAMMode = DMD_DVBC_QAM32;
1973 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=32\n"));
1974 return TRUE;
1975 break;
1976 case 2:
1977 *pQAMMode = DMD_DVBC_QAM64;
1978 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=64\n"));
1979 return TRUE;
1980 break;
1981 case 3:
1982 *pQAMMode = DMD_DVBC_QAM128;
1983 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=128\n"));
1984 return TRUE;
1985 break;
1986 case 4:
1987 *pQAMMode = DMD_DVBC_QAM256;
1988 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=256\n"));
1989 return TRUE;
1990 break;
1991 default:
1992 *pQAMMode = DMD_DVBC_QAMAUTO;
1993 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=invalid\n"));
1994 return FALSE;
1995 }
1996 }
1997
1998 /****************************************************************************
1999 Subject: To get the current symbol rate at the DVB-C Demod
2000 Function: INTERN_DVBC_GetCurrentSymbolRate
2001 Parmeter: pointer pData for return Symbolrate
2002
2003 Return: TRUE
2004 FALSE
2005 Remark:
2006 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)2007 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
2008 {
2009 MS_U8 tmp = 0;
2010 MS_U16 u16SymbolRateTmp = 0;
2011
2012 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_GetCurrentSymbolRate\n"));
2013
2014
2015 // intp
2016 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d2, &tmp);
2017 u16SymbolRateTmp = tmp;
2018 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d1, &tmp);
2019 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
2020
2021 if (abs(u16SymbolRateTmp-6900)<2)
2022 {
2023 u16SymbolRateTmp=6900;
2024 }
2025
2026 if (abs(u16SymbolRateTmp-6875)<2)
2027 {
2028 u16SymbolRateTmp=6875;
2029 }
2030
2031 *u16SymbolRate = u16SymbolRateTmp;
2032
2033 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]SR=%d\n",*u16SymbolRate));
2034
2035
2036 return TRUE;
2037 }
2038
2039
2040 /****************************************************************************
2041 Subject: To get the current symbol rate offset at the DVB-C Demod
2042 Function: INTERN_DVBC_GetCurrentSymbolRate
2043 Parmeter: pointer pData for return Symbolrate offset
2044
2045 Return: TRUE
2046 FALSE
2047 Remark:
2048 *****************************************************************************/
2049 //waiting mark
2050 /*
2051 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
2052 {
2053 MS_U8 u8Data = 0, reg_frz = 0;
2054 MS_U32 u32Data = 0;
2055 // MS_S32 s32Data = 0;
2056 MS_BOOL status = TRUE;
2057 MS_U16 u16SymbolRate = 0;
2058 float f_symb_offset = 0.0f;
2059
2060
2061
2062 // bank 26 0x03 [7] reg_bit_err_num_freeze
2063 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
2064 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
2065
2066 // sel, SFO debug output.
2067 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
2068 u32Data = u8Data;
2069 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
2070 u32Data = (u32Data<<8)|u8Data;
2071 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
2072 u32Data = (u32Data<<8)|u8Data;
2073 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
2074 u32Data = (u32Data<<8)|u8Data;
2075
2076 // bank 26 0x03 [7] reg_bit_err_num_freeze
2077 reg_frz=reg_frz&(~0x80);
2078 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
2079 // s32Data = (MS_S32)(u32Data<<8);
2080
2081 ULOGD("DEMOD","[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2082
2083 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2084
2085 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
2086 // f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
2087 f_symb_offset = (float)((MS_S32)u32Data) * (0.000007276f) * (float)u16SymbolRate/(float)DVBC_FS;
2088
2089 *pData = (MS_U16)(f_symb_offset + 0.5f);
2090
2091 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset));
2092
2093 return status;
2094 }
2095 #endif
2096 */
2097
INTERN_DVBC_Version(MS_U16 * ver)2098 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2099 {
2100
2101 MS_U8 status = true;
2102 MS_U8 tmp = 0;
2103 MS_U16 u16_INTERN_DVBC_Version;
2104
2105 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2106 u16_INTERN_DVBC_Version = tmp;
2107 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2108 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2109 *ver = u16_INTERN_DVBC_Version;
2110
2111 return status;
2112 }
2113
2114
INTERN_DVBC_Show_Demod_Version(void)2115 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2116 {
2117
2118 MS_BOOL status = true;
2119 MS_U16 u16_INTERN_DVBC_Version;
2120
2121 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2122
2123 ULOGD("DEMOD","[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2124
2125 return status;
2126 }
2127
2128
2129
2130 #if (INTERN_DVBC_INTERNAL_DEBUG)
2131
INTERN_DVBC_Show_AGC_Info(void)2132 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2133 {
2134 MS_U8 tmp = 0;
2135 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2136 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2137 MS_U16 if_agc_err = 0;
2138 MS_BOOL status = TRUE;
2139
2140 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2141 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2142 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2143 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2144 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2145 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2146
2147
2148 // select IF gain to read
2149 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2150 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2151
2152 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2153 if_agc_gain = tmp;
2154 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2155 if_agc_gain = (if_agc_gain<<8)|tmp;
2156
2157
2158 // select d1 gain to read.
2159 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2160 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2161
2162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2163 d1_gain = tmp;
2164 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2165 d1_gain = (d1_gain<<8)|tmp;
2166
2167 // select d2 gain to read.
2168 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2169 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2170
2171 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2172 d2_gain = tmp;
2173 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2174 d2_gain = (d2_gain<<8)|tmp;
2175
2176 // select IF gain err to read
2177 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2178 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2179
2180 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2181 if_agc_err = tmp;
2182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2183 if_agc_err = (if_agc_err<<8)|tmp;
2184
2185 ULOGD("DEMOD","[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2186 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2187
2188 ULOGD("DEMOD","[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2189
2190 return status;
2191 }
2192
INTERN_DVBC_info(void)2193 void INTERN_DVBC_info(void)
2194 {
2195 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2196 MS_U8 qam,tmp = 0;
2197 MS_U8 fft_u8 = 0;
2198 MS_U16 fft_u16bw = 0;
2199 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2200 //float f_snr = 0,f_freq = 0;
2201 //DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2202 MS_U16 f_start = 0,f_end = 0;
2203 MS_U8 s0_count = 0;
2204 MS_U8 sc4 = 0,sc3 = 0;
2205 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2206 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2207 MS_U16 count = 0;
2208 MS_U16 fb_i_1,fb_q_1;
2209 MS_U8 e0,e1,e2,e3;
2210 MS_S16 reg_freq;
2211 //float freq,mag;
2212
2213
2214
2215 INTERN_DVBC_Version(&version);
2216
2217 // fb_fs
2218 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2219 fb_fs = tmp;
2220 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2221 fb_fs = (fb_fs<<8)|tmp;
2222 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2223 fb_fs = (fb_fs<<8)|tmp;
2224 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2225 fb_fs = (fb_fs<<8)|tmp;
2226 // fc_fs
2227 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2228 fc_fs = tmp;
2229 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2230 fc_fs = (fc_fs<<8)|tmp;
2231 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2232 fc_fs = (fc_fs<<8)|tmp;
2233 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2234 fc_fs = (fc_fs<<8)|tmp;
2235 // crv
2236 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2237 crv = tmp;
2238 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2239 crv = (crv<<8)|tmp;
2240 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2241 crv = (crv<<8)|tmp;
2242 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2243 crv = (crv<<8)|tmp;
2244 // tr_error
2245 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2246 tr_error = tmp;
2247 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2248 tr_error = (tr_error<<8)|tmp;
2249 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2250 tr_error = (tr_error<<8)|tmp;
2251
2252 // intp
2253 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2254 intp = tmp;
2255 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2256 intp = (intp<<8)|tmp;
2257 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2258 intp = (intp<<8)|tmp;
2259 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2260 intp = (intp<<8)|tmp;
2261
2262 //waiting mark
2263 // fft info
2264 // intp
2265 /*
2266 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2267 fft_u16bw = tmp;
2268 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2269 fft_u16bw = (fft_u16bw<<8)|tmp;
2270 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2271 fft_u8 = tmp;
2272 */
2273
2274 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2275 qam = tmp;
2276
2277 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2278 f_start = tmp;
2279 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2280 f_start = (f_start<<8)|tmp;
2281 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2282 f_end = tmp;
2283 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2284 f_end = (f_end<<8)|tmp;
2285 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2286 s0_count = tmp;
2287
2288 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2289 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2290
2291 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2292 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2293 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2294 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2295 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2296 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2297 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2298
2299
2300 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2301
2302 count = 0x400;
2303 while(count--);
2304
2305 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2306 aci_e0 = tmp&0x0f;
2307 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2308 aci_e0 = aci_e0<<8|tmp;
2309
2310 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2311
2312 count = 0x400;
2313 while(count--);
2314
2315
2316 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2317 aci_e1 = tmp&0x0f;
2318 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2319 aci_e1 = aci_e1<<8|tmp;
2320
2321 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2322
2323 count = 0x400;
2324 while(count--);
2325
2326 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2327 aci_e2 = tmp&0x0f;
2328 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2329 aci_e2 = aci_e2<<8|tmp;
2330
2331 // read aci coef
2332 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2333
2334 count = 0x400;
2335 while(count--);
2336
2337 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2338 aci_e3 = tmp&0x0f;
2339 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2340 aci_e3 = aci_e3<<8|tmp;
2341
2342 //waiting mark
2343 /*
2344 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2345 fb_i_1 = tmp;
2346 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2347 fb_i_1 = fb_i_1<<8|tmp;
2348
2349 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2350 fb_q_1 = tmp;
2351 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2352 fb_q_1 = fb_q_1<<8|tmp;
2353 */
2354
2355 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2356 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2357 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2358 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2359
2360 //reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2361 //freq = (float)reg_freq*45473.0/65536.0;
2362 //mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2363
2364
2365 INTERN_DVBC_GetPacketErr(&packetErr);
2366 //INTERN_DVBC_GetSNR(&f_snr);
2367 INTERN_DVBC_Show_AGC_Info();
2368 //INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2369 //INTERN_DVBC_Get_FreqOffset(&f_freq,8); //GetStatus
2370 //INTERN_DVBC_GetCurrentSymbolRate(&symb_rate); //GetStatus
2371 //INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2372 //INTERN_DVBC_GetCurrentModulationType(&QAMMode); //GetStatus
2373 /*
2374 ULOGD("DEMOD","[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2375 //ULOGD("DEMOD","[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2376 ULOGD("DEMOD","[MStar_2][2]0x%lx\n",intp);
2377 ULOGD("DEMOD","[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2378 ULOGD("DEMOD","[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2379 ULOGD("DEMOD","[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2380 //ULOGD("DEMOD","[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2381 ULOGD("DEMOD","[Mstar_6][3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2382 */
2383 return;
2384
2385 }
2386
2387
2388 #endif
2389
2390 /***********************************************************************************
2391 Subject: read register
2392 Function: MDrv_1210_IIC_Bypass_Mode
2393 Parmeter:
2394 Return:
2395 Remark:
2396 ************************************************************************************/
2397 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2398 //{
2399 // UNUSED(enable);
2400 // if (enable)
2401 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2402 // else
2403 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2404 //}
2405