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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #include <math.h>
105 #include "MsCommon.h"
106 #include "MsIRQ.h"
107 #include "MsOS.h"
108 //#include "apiPWS.h"
109
110 #include "MsTypes.h"
111 #include "drvBDMA.h"
112 //#include "drvIIC.h"
113 //#include "msAPI_Tuner.h"
114 //#include "msAPI_MIU.h"
115 //#include "BinInfo.h"
116 //#include "halVif.h"
117 #include "drvDMD_INTERN_DVBC.h"
118 #include "halDMD_INTERN_DVBC.h"
119 #include "halDMD_INTERN_common.h"
120 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
121 #include "InfoBlock.h"
122 #endif
123 #include "drvMMIO.h"
124 //#include "TDAG4D01A_SSI_DVBT.c"
125 #include "drvDMD_VD_MBX.h"
126 #include "ULog.h"
127 #define TEST_EMBEDED_DEMOD 0
128 //U8 load_data_variable=1;
129 //-----------------------------------------------------------------------
130 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
131
132 #define TDE_REG_BASE 0x2800UL
133 #define INNC_REG_BASE 0x3800UL
134 #define EQE_REG_BASE 0x3900UL
135 //#define EQE2_REG_BASE 0x2d00UL
136
137 #ifdef MS_DEBUG
138 #define DBG_INTERN_DVBC(x) x
139 #define DBG_GET_SIGNAL_DVBC(x) x
140 #define DBG_INTERN_DVBC_TIME(x) x
141 #define DBG_INTERN_DVBC_LOCK(x) x
142 #define INTERN_DVBC_INTERNAL_DEBUG 0
143 #else
144 #define DBG_INTERN_DVBC(x) //x
145 #define DBG_GET_SIGNAL_DVBC(x) //x
146 #define DBG_INTERN_DVBC_TIME(x) //x
147 #define DBG_INTERN_DVBC_LOCK(x) //x
148 #define INTERN_DVBC_INTERNAL_DEBUG 0
149 #endif
150 #define DBG_DUMP_LOAD_DSP_TIME 0
151
152
153 #define SIGNAL_LEVEL_OFFSET 0.00f
154 #define TAKEOVERPOINT -60.0f
155 #define TAKEOVERRANGE 0.5f
156 #define LOG10_OFFSET -0.21f
157 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
158 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
159
160 #define TUNER_IF 5000
161
162 #define TS_SER_C 0x00 //0: parallel 1:serial
163
164 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
165 #define TS_INV_C 0x01
166 #else
167 #define TS_INV_C 0x00
168 #endif
169
170 #define DVBC_FS 48000 //24000
171 #define CFG_ZIF 0x00 //For ZIF ,FC=0
172 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
173 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
174 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
175 #define FS_L_C (DVBC_FS&0xFF)
176 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
177 #define IQ_SWAP_C 0x00
178 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
179 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
180 // Symbol Rate: 6875 = 0x1ADB
181 // Symbol Rate: 6900 = 0x1AF4
182 // Symbol Rate: 7000 = 0x1B58
183 // Symbol Rate: 4000 = 0x0FA0
184 // Symbol Rate: 6125 = 0x17ED
185 #define SR0_H 0x1A
186 #define SR0_L 0xF4 //6900
187 #define SR1_H 0x1B
188 #define SR1_L 0x58 //7000
189 #define SR2_H 0x17
190 #define SR2_L 0xED //6125
191 #define SR3_H 0x0F
192 #define SR3_L 0xA0 //4000
193 #define SR4_H 0x1B
194 #define SR4_L 0x26 //6950
195 #define SR5_H 0x1A //0xDB
196 #define SR5_L 0xDB //0x1A //6875
197 #define SR6_H 0x1C
198 #define SR6_L 0x20 //7200
199 #define SR7_H 0x1C
200 #define SR7_L 0x52 //7250
201 #define SR8_H 0x0B
202 #define SR8_L 0xB8 //3000
203 #define SR9_H 0x03
204 #define SR9_L 0xE8 //1000
205 #define SR10_H 0x07
206 #define SR10_L 0xD0 //2000
207 #define SR11_H 0x00
208 #define SR11_L 0x00 //0000
209
210
211 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
212
213 // SAR dependent
214 #define NO_SIGNAL_TH_A 0xA3
215 // Tuner dependent
216 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
217 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
218 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
219 #define NO_SIGNAL_TH_C_H 0xff //0x00
220 #define DAGC1_REF 0x70
221 #define DAGC2_REF 0x30
222 #define AGC_REF_L 0x00
223 #define AGC_REF_H 0x06
224
225 #define INTERN_AUTO_SR_C 1
226 #define INTERN_AUTO_QAM_C 1
227
228 #define ATV_DET_EN 1
229
230 // Need to update when:
231 // Case#1: New add DSP parameters
232 // Case#2: Use exist DSP parameters to another applications/functions
233 #define UTOPIA_DRIVER_VERSION 0x01 // Update by user.
234
235 #if 0
236 MS_U8 INTERN_DVBC_DSPREG[] =
237 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
238 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
239 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
240 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
241 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
242 };
243 #else
244 MS_U8 INTERN_DVBC_DSPREG[] =
245 {
246 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
247 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
248 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
249 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
250 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
251 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
252 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
253 };
254 #endif
255 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
256
257 //-----------------------------------------------------------------------
258 /****************************************************************
259 *Local Variables *
260 ****************************************************************/
261
262 //static MS_BOOL TPSLock = 0;
263 static MS_U32 u32ChkScanTimeStartDVBC = 0;
264 static MS_U8 g_dvbc_lock = 0;
265 static float intern_dvb_c_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
266
267 //Global Variables
268 S_CMDPKTREG gsCmdPacketDVBC;
269 //MS_U8 gCalIdacCh0, gCalIdacCh1;
270 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
271 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
272 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
273 MS_U8 INTERN_DVBC_table[] = {
274 #include "fwDMD_INTERN_DVBC.dat"
275 };
276
277 #endif
278
279 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
280 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
281 // MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
282 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
283 // MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff);
284 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
285 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
286 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
287
288 #if (INTERN_DVBC_INTERNAL_DEBUG)
289 void INTERN_DVBC_info(void);
290 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
291 #endif
292
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)293 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
294 {
295 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
296 MS_U8 status = TRUE;
297 MS_U16 u16DspAddr = 0;
298
299 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init\n");
300
301 #if 0//def MS_DEBUG
302 {
303 MS_U8 u8buffer[256];
304 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Reset\n");
305 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
306 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
307
308 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
309 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
310 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
311 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
312 ULOGD("DEMOD","%x ", u8buffer[idx]);
313 ULOGD("DEMOD","\n");
314
315 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Value\n");
316 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
317 ULOGD("DEMOD","%x ", INTERN_DVBC_DSPREG[idx]);
318 ULOGD("DEMOD","\n");
319 }
320 #endif
321
322 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
323 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
324
325 // readback to confirm.
326 #ifdef MS_DEBUG
327 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
328 {
329 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
330 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
331 {
332 ULOGD("DEMOD","[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
333 }
334 }
335 #endif
336
337 if (u8DVBC_DSPReg != NULL)
338 {
339 if (1 == u8DVBC_DSPReg[0])
340 {
341 u8DVBC_DSPReg+=2;
342 for (idx = 0; idx<u8Size; idx++)
343 {
344 u16DspAddr = *u8DVBC_DSPReg;
345 u8DVBC_DSPReg++;
346 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
347 u8DVBC_DSPReg++;
348 u8Mask = *u8DVBC_DSPReg;
349 u8DVBC_DSPReg++;
350 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
351 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
352 u8DVBC_DSPReg++;
353 ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite);
354 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
355 }
356 }
357 else
358 {
359 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
360 }
361 }
362
363 #if 0//def MS_DEBUG
364 {
365 MS_U8 u8buffer[256];
366 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
367 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
368 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack\n");
369 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
370 ULOGD("DEMOD","%x ", u8buffer[idx]);
371 ULOGD("DEMOD","\n");
372 }
373 #endif
374
375 #if 0//def MS_DEBUG
376 {
377 MS_U8 u8buffer[256];
378 for (idx = 0; idx<128; idx++)
379 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
380
381 for (idx = 0; idx<128; idx++)
382 {
383 ULOGD("DEMOD","%x ", u8buffer[idx]);
384 if ((idx & 0xF) == 0xF) ULOGD("DEMOD","\n");
385 }
386 ULOGD("DEMOD","\n");
387 }
388 #endif
389
390 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_PARAM_VERSION, UTOPIA_DRIVER_VERSION) != TRUE)
391 {
392 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init NG\n"); return FALSE;
393 }
394
395 return status;
396 }
397
398 /***********************************************************************************
399 Subject: Command Packet Interface
400 Function: INTERN_DVBC_Cmd_Packet_Send
401 Parmeter:
402 Return: MS_BOOL
403 Remark:
404 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)405 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
406 {
407 MS_U8 status = true, indx;
408 MS_U8 reg_val, timeout = 0;
409 return TRUE;
410 // ==== Command Phase ===================
411 ULOGD("DEMOD","--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
412 pCmdPacket->param[0],pCmdPacket->param[1],
413 pCmdPacket->param[2],pCmdPacket->param[3],
414 pCmdPacket->param[4],pCmdPacket->param[5] );
415
416 // wait _BIT_END clear
417 do
418 {
419 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
420 if((reg_val & _BIT_END) != _BIT_END)
421 {
422 break;
423 }
424 MsOS_DelayTask(5);
425 if (timeout > 200)
426 {
427 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
428 return false;
429 }
430 timeout++;
431 } while (1);
432
433 // set cmd_3:0 and _BIT_START
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
435 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
436 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
437
438
439 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
440 // wait _BIT_START clear
441 do
442 {
443 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
444 if((reg_val & _BIT_START) != _BIT_START)
445 {
446 break;
447 }
448 MsOS_DelayTask(10);
449 if (timeout > 200)
450 {
451 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
452 return false;
453 }
454 timeout++;
455 } while (1);
456
457 // ==== Data Phase ======================
458
459 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
460
461 for (indx = 0; indx < param_cnt; indx++)
462 {
463 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
464 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
465
466 // set param[indx] and _BIT_DRQ
467 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
468 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
469 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
470
471 // wait _BIT_DRQ clear
472 do
473 {
474 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
475 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
476 {
477 break;
478 }
479 MsOS_DelayTask(5);
480 if (timeout > 200)
481 {
482 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
483 return false;
484 }
485 timeout++;
486 } while (1);
487 }
488
489 // ==== End Phase =======================
490
491 // set _BIT_END to finish command
492 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
493 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
494 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
495 return status;
496 }
497
498
499 /***********************************************************************************
500 Subject: Command Packet Interface
501 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
502 Parmeter:
503 Return: MS_BOOL
504 Remark:
505 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)506 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
507 {
508 return TRUE;
509 }
510
511 /***********************************************************************************
512 Subject: SoftStop
513 Function: INTERN_DVBC_SoftStop
514 Parmeter:
515 Return: MS_BOOL
516 Remark:
517 ************************************************************************************/
518
INTERN_DVBC_SoftStop(void)519 MS_BOOL INTERN_DVBC_SoftStop ( void )
520 {
521 #if 1
522 MS_U16 u8WaitCnt=0;
523
524 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
525 {
526 ULOGD("DEMOD",">> MB Busy!\n");
527 return FALSE;
528 }
529
530 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
531
532 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
533 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
534
535 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
536 {
537 #if TEST_EMBEDED_DEMOD
538 MsOS_DelayTask(1); // << Ken 20090629
539 #endif
540 if (u8WaitCnt++ >= 0xFF)
541 {
542 ULOGD("DEMOD",">> DVBT SoftStop Fail!\n");
543 return FALSE;
544 }
545 }
546
547 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
548 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
549 #endif
550 return TRUE;
551 }
552
553
554 /***********************************************************************************
555 Subject: Reset
556 Function: INTERN_DVBC_Reset
557 Parmeter:
558 Return: MS_BOOL
559 Remark:
560 ************************************************************************************/
561 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)562 MS_BOOL INTERN_DVBC_Reset ( void )
563 {
564 ULOGD("DEMOD"," @INTERN_DVBC_reset\n");
565
566 //ULOGD("DEMOD","INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime());
567
568 //INTERN_DVBC_SoftStop();
569
570
571 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
572 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
573 MsOS_DelayTask(5);
574 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
575 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
576 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
577 MsOS_DelayTask(5);
578
579 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
580 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
581
582 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
583 g_dvbc_lock = 0;
584
585 return TRUE;
586 }
587
588 /***********************************************************************************
589 Subject: Exit
590 Function: INTERN_DVBC_Exit
591 Parmeter:
592 Return: MS_BOOL
593 Remark:
594 ************************************************************************************/
INTERN_DVBC_Exit(void)595 MS_BOOL INTERN_DVBC_Exit ( void )
596 {
597
598 INTERN_DVBC_SoftStop();
599
600
601 //diable clk gen
602 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
603 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
604
605 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
606 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
607
608 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
609 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
610
611 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
612 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
613
614 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
615 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
616
617 HAL_DMD_RIU_WriteByte(0x103312, 0x05); // dvbt_t:0x0000, dvb_c: 0x0004
618 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
619
620 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
621 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
622
623 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
624 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
625
626 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
627 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
628
629 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
630 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
631
632 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
633
634 return TRUE;
635 }
636
637 /***********************************************************************************
638 Subject: Load DSP code to chip
639 Function: INTERN_DVBC_LoadDSPCode
640 Parmeter:
641 Return: MS_BOOL
642 Remark:
643 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)644 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
645 {
646 MS_U8 udata = 0x00;
647 MS_U16 i;
648 MS_U16 fail_cnt=0;
649
650 #if (DBG_DUMP_LOAD_DSP_TIME==1)
651 MS_U32 u32Time;
652 #endif
653
654
655 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
656 BININFO BinInfo;
657 MS_BOOL bResult;
658 MS_U32 u32GEAddr;
659 MS_U8 Data;
660 MS_S8 op;
661 MS_U32 srcaddr;
662 MS_U32 len;
663 MS_U32 SizeBy4K;
664 MS_U16 u16Counter=0;
665 MS_U8 *pU8Data;
666 #endif
667
668 #if 0
669 if(HAL_DMD_RIU_ReadByte(0x101E3E))
670 {
671 ULOGD("DEMOD","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
672 return FALSE;
673 }
674 #endif
675
676 // MDrv_Sys_DisableWatchDog();
677
678
679 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
680 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // reset VD_MCU
681 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
682 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
683 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
684 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
685 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
686
687 //// Load code thru VDMCU_IF ////
688 ULOGD("DEMOD",">Load Code.....\n");
689 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
690 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
691 {
692 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
693 }
694 #else
695 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
696 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
697 if ( bResult != PASS )
698 {
699 return FALSE;
700 }
701 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
702
703 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
704 InfoBlock_Flash_2_Checking_Start(&BinInfo);
705 #endif
706
707 #if OBA2
708 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
709 #else
710 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
711 #endif
712
713 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
714 InfoBlock_Flash_2_Checking_End(&BinInfo);
715 #endif
716
717 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
718 SizeBy4K=BinInfo.B_Len/0x1000;
719 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
720
721 #if (DBG_DUMP_LOAD_DSP_TIME==1)
722 u32Time = msAPI_Timer_GetTime0();
723 #endif
724
725 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
726
727 for (i=0;i<=SizeBy4K;i++)
728 {
729 if(i==SizeBy4K)
730 len=BinInfo.B_Len%0x1000;
731 else
732 len=0x1000;
733
734 srcaddr = u32GEAddr+(0x1000*i);
735 //ULOGD("DEMOD","\t i = %08X\n", i);
736 //ULOGD("DEMOD","\t len = %08X\n", len);
737 op = 1;
738 u16Counter = 0 ;
739 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
740 while(len--)
741 {
742 u16Counter ++ ;
743 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
744 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
745 #if OBA2
746 pU8Data = (MS_U8 *)(srcaddr);
747 #else
748 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
749 #endif
750 Data = *pU8Data;
751
752 #if 0
753 if(u16Counter < 0x100)
754 ULOGD("DEMOD","0x%bx,", Data);
755 #endif
756 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
757
758 srcaddr += op;
759 }
760 // ULOGD("DEMOD","\n\n\n");
761 }
762
763 #if (DBG_DUMP_LOAD_DSP_TIME==1)
764 ULOGD("DEMOD","------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
765 #endif
766
767 #endif
768
769 //// Content verification ////
770 ULOGD("DEMOD",">Verify Code...\n");
771
772 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
773 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
774
775 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
776 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
777 {
778 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
779 if (udata != INTERN_DVBC_table[i])
780 {
781 ULOGD("DEMOD",">fail add = 0x%x\n", i);
782 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBC_table[i]);
783 ULOGD("DEMOD",">data = 0x%x\n", udata);
784
785 if (fail_cnt > 10)
786 {
787 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
788 return false;
789 }
790 fail_cnt++;
791 }
792 }
793 #else
794 for (i=0;i<=SizeBy4K;i++)
795 {
796 if(i==SizeBy4K)
797 len=BinInfo.B_Len%0x1000;
798 else
799 len=0x1000;
800
801 srcaddr = u32GEAddr+(0x1000*i);
802 //ULOGD("DEMOD","\t i = %08LX\n", i);
803 //ULOGD("DEMOD","\t len = %08LX\n", len);
804 op = 1;
805 u16Counter = 0 ;
806 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
807 while(len--)
808 {
809 u16Counter ++ ;
810 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
811 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
812 #if OBA2
813 pU8Data = (MS_U8 *)(srcaddr);
814 #else
815 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
816 #endif
817 Data = *pU8Data;
818
819 #if 0
820 if(u16Counter < 0x100)
821 ULOGD("DEMOD","0x%bx,", Data);
822 #endif
823 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
824 if (udata != Data)
825 {
826 ULOGD("DEMOD",">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
827 ULOGD("DEMOD",">code = 0x%x\n", Data);
828 ULOGD("DEMOD",">data = 0x%x\n", udata);
829
830 if (fail_cnt++ > 10)
831 {
832 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
833 return false;
834 }
835 }
836
837 srcaddr += op;
838 }
839 // ULOGD("DEMOD","\n\n\n");
840 }
841 #endif
842
843 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
844 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
845 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
846 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
847
848 ULOGD("DEMOD",">DSP Loadcode done.");
849 //while(load_data_variable);
850 #if 0
851 INTERN_DVBC_Config(6875, 128, 36125, 0,1);
852 INTERN_DVBC_Active(ENABLE);
853 while(1);
854 #endif
855 HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
856
857 return TRUE;
858 }
859
860 /***********************************************************************************
861 Subject: DVB-T CLKGEN initialized function
862 Function: INTERN_DVBC_Power_On_Initialization
863 Parmeter:
864 Return: MS_BOOL
865 Remark:
866 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)867 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
868 {
869 MS_U8 temp_val;
870 //move to drvSYS MS_U8 tmp;
871 //MS_U8 udatatemp = 0x00;
872 /************************************************************************
873 * T10 U01
874 * This bit0 is mux for DMD muc and HK,
875 * bit0: 0:HK can rw bank 0x1120, 1: DMD mcu can rw bank 0x1120;
876 ************************************************************************/
877 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
878
879 // ================================================================
880 // Start TOP CLKGEN setting
881 // ================================================================
882
883 // Set DMDMCU clock
884 // [4:0] : reg_ckg_dmdmcu
885 // [0] : disable clock
886 // [1] : invert clock
887 // [4:2]: Select clock source
888 // 000: clk_172_buf
889 // 001: clk_160_buf
890 // 010: clk_144_buf
891 // 011: clk_123_buf
892 // 100: clk_108_buf
893 // 101: 1'b0
894 // 110: 1'b0
895 // 111: clk_xtal_12M_buf
896 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b01, 16'h0010);
897 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b01, 16'h0010);
898 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
899
900 // Set parallel TS clock
901 // [11] : reg_ckg_demod_test_in_en = 0
902 // 0: select internal ADC CLK
903 // 1: select external test-in clock
904 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
905 // 0: select gated clock
906 // 1: select free-run clock
907 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 1
908 // 0: normal phase to pad
909 // 1: invert phase to pad
910 // [8] : reg_ckg_atsc_dvb_div_sel = 1
911 // 0: select clk_dmplldiv5
912 // 1: select clk_dmplldiv3
913 // [4:0]: reg_ckg_dvbtm_ts_divnum = 19
914 // => TS clock = (864/3)/(2*(19+1)) = 7.2MHz
915 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0713);
916 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0713);
917 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
918 temp_val|=0x07;
919 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
920 HAL_DMD_RIU_WriteByte(0x103300,0x13);
921
922 // Enable ATSC, DVBTC TS clock
923 // [3:0] : reg_ckg_atsc_ts
924 // [0] : disable clock
925 // [1] : invert clock
926 // [3:2] : Select clock source
927 // 00: clk_atsc_dvb_div
928 // 01: 62 MHz
929 // 10: 54 MHz
930 // 11: reserved
931 // [11:8]: reg_ckg_dvbtc_ts
932 // [0] : disable clock
933 // [1] : invert clock
934 // [3:2] : Select clock source
935 // 00: clk_atsc_dvb_div
936 // 01: 62 MHz
937 // 10: 54 MHz
938 // 11: reserved
939 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
940 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
941
942 HAL_DMD_RIU_WriteByte(0x103309,0x00);
943 HAL_DMD_RIU_WriteByte(0x103308,0x00);
944
945 // Enable ADC clock in clkgen_demod!!!
946 // ^^^^^^^^^^^^^^^
947 // [3:0]: reg_ckg_dvbtc_adc
948 // [0] : disable clock
949 // [1] : invert clock
950 // [2] : Select clock source => for demod clkgen clk_dvbtc_adc
951 // 0:clk_dmdadc
952 // 1:clk_vif_ssc_mux
953 // ^^^^^^^^^^^^^^^
954 // if(reg_vif_ssc_en) => clk_vif_ssc_43p2_p(43.2 MHz)
955 // else => clk_dmplldiv10_div2(43.2 MHz)
956 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
957 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
958 HAL_DMD_RIU_WriteByte(0x103315,0x00);
959 HAL_DMD_RIU_WriteByte(0x103314,0x00);
960
961 // Enable VIF DAC clock in clkgen_demod!!!
962 // ^^^^^^^^^^^^^^^
963 // [3:0] : reg_ckg_vifdbb_dac
964 // [11:8]: reg_ckg_vifdbb_vdac
965 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
966
967
968 // Reset TS divider
969 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0001);
970 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0001);
971 HAL_DMD_RIU_WriteByte(0x103302,0x01);
972 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0000);
973 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0000);
974 HAL_DMD_RIU_WriteByte(0x103302,0x00);
975
976 // ================================================================
977 // Start Demod CLKGEN setting
978 // ================================================================
979
980
981
982 // Enable clk_atsc_adcd_sync
983 // [3:0]: reg_ckg_atsc_adcd_sync
984 // [0] : disable clock
985 // [1] : invert clock
986 // [3:2]: Select clock source
987 // 00: clk_dmdadc_sync
988 // 01: clk_atsc50_p
989 // ^^^^^^^^^^^^
990 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
991 // else => clk_dmplldiv17(50.82 MHz)
992 // 10: clk_atsc25_p
993 // ^^^^^^^^^^^^
994 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
995 // else => clk_dmplldiv17_div2(25.41 MHz)
996 // 11: 1'b0
997 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
998 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
999 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1000 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1001 // @0x3511
1002 // [2:0] : reg_ckg_dvbt_outer1x
1003 // [0] : disable clock
1004 // [1] : invert clock
1005 // [2] : Select clock source
1006 // 00: dvb_clk48_buf
1007 // 01: dvb_clk43_buf
1008 // 10: 1'b0
1009 // 11: DFT_CLK
1010 // [6:4] : reg_ckg_dvbt_outer2x
1011 // [4] : disable clock
1012 // [5] : invert clock
1013 // [6] : Select clock source
1014 // 00: dvb_clk96_buf
1015 // 01: dvb_clk86_buf
1016 // 10: 1'b0
1017 // 11: DFT_CLK
1018 // [11:8]: reg_ckg_dvbtc_outer2x
1019 // [8] : disable clock
1020 // [9] : invert clock
1021 // [11:10]: Select clock source
1022 // 00: mpll_clk57p6_buf
1023 // 01: dvb_clk43_buf
1024 // 10: dvb_clk86_buf
1025 // 11: dvb_clk96_buf
1026 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0844);
1027 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0844);
1028 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
1029 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1030 // @0x3516
1031 // [2:0] : reg_ckg_dvbc_inner
1032 // [0] : disable clock
1033 // [1] : invert clock
1034 // [2]: Select clock source
1035 // 0: dvb_clk48_buf
1036 // 1: 1'b0
1037 // [6:4] : reg_ckg_dvbc_inner
1038 // [4] : disable clock
1039 // [5] : invert clock
1040 // [6]: Select clock source
1041 // 0: mpll_clk18_buf
1042 // 1: 1'b0
1043 // [10:8] : reg_ckg_dvbc_inner
1044 // [8] : disable clock
1045 // [9] : invert clock
1046 // [10]: Select clock source
1047 // 0: mpll_clk144_buf
1048 // 1: 1'b0
1049 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h15, 2'b11, 16'h0000);
1050 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h15, 2'b11, 16'h0000);
1051 HAL_DMD_RIU_WriteByte(0x111f2b,0x00);
1052 HAL_DMD_RIU_WriteByte(0x111f2a,0x00);
1053 // @0x351d
1054 // [4:0] : reg_ckg_dvbtm_adc_eq_1x
1055 // [0] : disable clock
1056 // [1] : invert clock
1057 // [2] : Select clock source
1058 // 00: adc_clk_buf
1059 // 01: 1'b0
1060 // 10: 1'b0
1061 // 11: DFT_CLK
1062 // [12:8]: reg_ckg_dvbtm_adc_eq_0p5x
1063 // [4] : disable clock
1064 // [5] : invert clock
1065 // [6]: Select clock source
1066 // 00: clk_adc_div2_buf
1067 // 01: 1'b0
1068 // 10: 1'b0
1069 // 11: DFT_CLK
1070 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1071 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1072 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
1073 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
1074 // @0x3512
1075 // [11:8]: reg_ckg_acifir
1076 // [8] : disable clock
1077 // [9] : invert clock
1078 // [11:10]: Select clock source
1079 // 000: clk_atsc25_p
1080 // 001: clk_dmdadc
1081 // 010: clk_vif_ssc_mux
1082 // 011: 1'b0
1083 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0400);
1084 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0400);
1085 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
1086 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1087 // @0x3571 //Maserati
1088 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1089 // [13:8] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1090 // [0] : disable clock
1091 // [1] : invert clock
1092 // [4:2] : Select clock source
1093 // 000: dvb_clk96_buf
1094 // 001: dvb_clk86_buf
1095 // 010: adc_clk_buf
1096 // 011: mpll_clk18_buf
1097 // 100: clk_dmplldiv10
1098 // 100: clk_adc1x_eq1x_p
1099 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1100 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1101 HAL_DMD_RIU_WriteByte(0x111fe3,0x08);
1102 HAL_DMD_RIU_WriteByte(0x111fe2,0x10);
1103 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1104 // [0] : disable clock
1105 // [1] : invert clock
1106 // [3:2]: Select clock source
1107 // 00: dtmb_clk288_buf(256 MHz)
1108 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1109 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1110 // 11: 1'b0
1111 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1112 // ^^^^^^^^^^
1113 // [0] : disable clock
1114 // [1] : invert clock
1115 // [3:2]: Select clock source
1116 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1117 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1118 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1119 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1120 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1121 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1122 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1123 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1124 // ^^^^^^^^^^
1125 // [0] : disable clock
1126 // [1] : invert clock
1127 // [3:2]: Select clock source
1128 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1129 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1130 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1131 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1132 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1133 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1134 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1135 // [15:12]: reg_ckg_dtmb_sram_dump
1136 // [0] : disable clock
1137 // [1] : invert clock
1138 // [3:2]: Select clock source
1139 // 00: dtmb_clk18_buf(16 MHz)
1140 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1141 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1142 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1143 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h38, 2'b11, 16'h1001);
1144 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h38, 2'b11, 16'h1001);
1145 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1146 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1147 // @0x353b //Maserati
1148 // [15:12] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner4x
1149 // [12] : disable clock
1150 // [13] : invert clock
1151 // [15:14] : Select clock source
1152 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1153 // 01: clk_isdbt_inner4x_p
1154 // 10: clk_share_dtmb_eq0p5x_isdbt_sram0_mux
1155 // 11: clk_adc1x_eq1x_p
1156 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b10, 16'h0111);
1157 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b10, 16'h0111);
1158 HAL_DMD_RIU_WriteByte(0x111f77,0x01);
1159 // @0x353c //Maserati
1160 // [ 3: 0] reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x[3:0]
1161 // [ 6: 4] reg_ckg_dvbtm_sram_t12x_t22x_isdbt_inner2x[2:0]
1162 // [10: 8] reg_ckg_dvbtm_sram_t11x_t22x_isdbt_inner2x[2:0]
1163 // [14:12] reg_ckg_dvbtm_sram_t12x_t24x_isdbt_outer6x
1164 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h1110);
1165 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h1110);
1166 HAL_DMD_RIU_WriteByte(0x111f79,0x11);
1167 HAL_DMD_RIU_WriteByte(0x111f78,0x10);
1168 // @0x3571 //Maserati
1169 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1170 // [13:8] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1171 // [0] : disable clock
1172 // [1] : invert clock
1173 // [4:2] : Select clock source
1174 // 000: dvb_clk96_buf
1175 // 001: dvb_clk86_buf
1176 // 010: adc_clk_buf
1177 // 011: mpll_clk18_buf
1178 // 100: clk_dmplldiv10
1179 // 100: clk_adc1x_eq1x_p
1180 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0811);
1181 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0811);
1182 HAL_DMD_RIU_WriteByte(0x111fe3,0x08);
1183 HAL_DMD_RIU_WriteByte(0x111fe2,0x11);
1184
1185 // @0x3578 //Maserati
1186 // [4:0] : reg_ckg_dvbt2_inner2x_srd0p5x
1187 // [0] : disable clock
1188 // [1] : invert clock
1189 // [4:2] : Select clock source
1190 // 000: dvb_clk48_buf
1191 // 001: dvb_clk43_buf
1192 // 010: clk_adc_div2_buf
1193 // 011: mpll_clk9_buf
1194 // 100: clk_adc0p5x_eq0p5x_p
1195 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1196 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1197 HAL_DMD_RIU_WriteByte(0x111ff0,0x08);
1198 // @Macan
1199 // [ 4: 0] reg_ckg_dvbtm_sram_t14x_t24x
1200 // [12: 8] reg_ckg_dvbtm_ts_in
1201 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b10, 16'h1c01);
1202 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b10, 16'h1c01);
1203 HAL_DMD_RIU_WriteByte(0x111f31,0x1c);
1204
1205 // ================================================================
1206 // Select reg_DMDTOP and reg_DMDANA are controlled by which MCU
1207 // ================================================================
1208
1209 // reg_dmdtop_dmd_sel=test_chip_top.chip_top.reg_chip_top.reg_CHIPTOP_inst.reg_chiptop_dummy_0[8]: 0x1c
1210 // 1'b0->reg_DMDTOP control by HK_MCU.
1211 // wriu 0x101e39 8'bxxxx_xxx0
1212 // 1'b1->reg_DMDTOP control by DMD_MCU.
1213 // wriu 0x101e39 8'bxxxx_xxx1
1214 // reg_dmd_ana_regsel=test_chip_top.chip_top.reg_chip_top.reg_CHIPTOP_inst.reg_chiptop_dummy_0[9]: 0x1c
1215 // 1'b0->reg_DMDANA control by HK_MCU.
1216 // wriu 0x101e39 8'bxxxx_xx0x
1217 // 1'b1->reg_DMDANA control by DMD_MCU.
1218 // wriu 0x101e39 8'bxxxx_xx1x
1219 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1220 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1221 HAL_DMD_RIU_WriteByte(0x101E39, 0x03); //mux from DMD MCU to HK.
1222 }
1223
1224 /***********************************************************************************
1225 Subject: Power on initialized function
1226 Function: INTERN_DVBC_Power_On_Initialization
1227 Parmeter:
1228 Return: MS_BOOL
1229 Remark:
1230 ************************************************************************************/
1231
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)1232 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
1233 {
1234 MS_U8 status = true;
1235 ULOGD("DEMOD","INTERN_DVBC_Power_On_Initialization\n");
1236
1237 #if defined(PWS_ENABLE)
1238 Mapi_PWS_Stop_VDMCU();
1239 #endif
1240
1241 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
1242 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1243 //// Firmware download //////////
1244 ULOGD("DEMOD","INTERN_DVBC Load DSP...\n");
1245 //MsOS_DelayTask(100);
1246
1247 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x04) // DVBT = BIT1 -> 0x02
1248 {
1249 if (INTERN_DVBC_LoadDSPCode() == FALSE)
1250 {
1251 ULOGD("DEMOD","DVB-C Load DSP Code Fail\n");
1252 return FALSE;
1253 }
1254 else
1255 {
1256 ULOGD("DEMOD","DVB-C Load DSP Code OK\n");
1257 }
1258 }
1259
1260 status &= INTERN_DVBC_Reset();
1261
1262 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
1263
1264 return status;
1265 }
1266
1267 /************************************************************************************************
1268 Subject: Driving control
1269 Function: INTERN_DVBC_Driving_Control
1270 Parmeter: bInversionEnable : TRUE For High
1271 Return: void
1272 Remark:
1273 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)1274 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
1275 {
1276 MS_U8 u8Temp;
1277
1278 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1279
1280 if (bEnable)
1281 {
1282 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1283 }
1284 else
1285 {
1286 u8Temp = u8Temp & (~0x01);
1287 }
1288
1289 ULOGD("DEMOD","---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp);
1290 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1291 }
1292 /************************************************************************************************
1293 Subject: Clk Inversion control
1294 Function: INTERN_DVBC_Clk_Inversion_Control
1295 Parmeter: bInversionEnable : TRUE For Inversion Action
1296 Return: void
1297 Remark:
1298 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)1299 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1300 {
1301 MS_U8 u8Temp;
1302
1303 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1304
1305 if (bInversionEnable)
1306 {
1307 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1308 }
1309 else
1310 {
1311 u8Temp = u8Temp & (~0x02);
1312 }
1313
1314 ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp);
1315 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1316 }
1317 /************************************************************************************************
1318 Subject: Transport stream serial/parallel control
1319 Function: INTERN_DVBC_Serial_Control
1320 Parmeter: bEnable : TRUE For serial
1321 Return: MS_BOOL :
1322 Remark:
1323 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1324 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1325 {
1326 MS_U8 status = true;
1327 MS_U8 temp_val;
1328 ULOGD("DEMOD"," @INTERN_DVBC_ts... u8TSClk=%d\n", u8TSClk);
1329
1330 if (u8TSClk == 0xFF) u8TSClk=0x13;
1331 if (bEnable) //Serial mode for TS pad
1332 {
1333 // serial
1334 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1335 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1336
1337 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1338 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1339 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1340 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1341 temp_val|=0x04;
1342 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1343 #else
1344 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1345 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1346 temp_val|=0x07;
1347 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1348 #endif
1349 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1350 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1351
1352 //// INTERN_DVBC TS Control: Serial //////////
1353
1354 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_SERIAL);
1355
1356 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1357 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1358 #else
1359 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1360 #endif
1361 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1362
1363 gsCmdPacketDVBC.param[0] = TS_SERIAL;
1364 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1365 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1366 #else
1367 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1368 #endif
1369 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1370 }
1371 else
1372 {
1373 //parallel
1374 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1375 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1376
1377 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1378 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1379 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1380 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1381 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1382 temp_val|=0x05;
1383 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1384 #else
1385 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1386 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1387 temp_val|=0x07;
1388 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1389 #endif
1390
1391 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1392 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1393
1394 //// INTERN_DVBC TS Control: Parallel //////////
1395
1396 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_PARALLEL);
1397
1398 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1399 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1400 #else
1401 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1402 #endif
1403 //// INTERN_DVBC TS Control: Parallel //////////
1404 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1405
1406 gsCmdPacketDVBC.param[0] = TS_PARALLEL;
1407 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1408 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1409 #else
1410 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1411 #endif
1412 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1413 }
1414
1415 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1416 ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",0 );
1417 #else
1418 ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",1 );
1419 #endif
1420
1421 INTERN_DVBC_Driving_Control(INTERN_DVBC_DTV_DRIVING_LEVEL);
1422 return status;
1423 }
1424
1425 /************************************************************************************************
1426 Subject: TS1 output control
1427 Function: INTERN_DVBC_PAD_TS1_Enable
1428 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1429 Return: void
1430 Remark:
1431 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)1432 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
1433 {
1434 ULOGD("DEMOD"," @INTERN_DVBC_TS1_Enable... \n");
1435
1436 if(flag) // PAD_TS1 Enable TS CLK PAD
1437 {
1438 //ULOGD("DEMOD","=== TS1_Enable ===\n");
1439 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1440 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1441 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1442 }
1443 else // PAD_TS1 Disable TS CLK PAD
1444 {
1445 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1446 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1447 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1448 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1449 }
1450 }
1451
1452 /************************************************************************************************
1453 Subject: channel change config
1454 Function: INTERN_DVBC_Config
1455 Parmeter: BW: bandwidth
1456 Return: MS_BOOL :
1457 Remark:
1458 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1459 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1460 {
1461
1462 MS_U8 status = true;
1463 MS_U8 reg_symrate_l, reg_symrate_h;
1464 //MS_U16 u16Fc = 0;
1465 MS_U8 temp_val;
1466 // force
1467 // u16SymbolRate = 0;
1468 // eQamMode = DMD_DVBC_QAMAUTO;
1469
1470 //pu16_symbol_rate_list = pu16_symbol_rate_list;
1471 //u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1472
1473 //ULOGD("DEMOD"," @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk);
1474 //ULOGD("DEMOD","INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime());
1475
1476 if (u8TSClk == 0xFF) u8TSClk=0x13;
1477
1478 /*
1479 switch(u32IFFreq)
1480 {
1481 case 36125:
1482 case 36167:
1483 case 36000:
1484 case 6000:
1485 case 4560:
1486 //u16Fc = DVBC_FS - u32IFFreq;
1487 DBG_INTERN_DVBC(ULOGD("DEMOD","Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1488 break;
1489 case 44000:
1490 default:
1491 ULOGD("DEMOD","IF frequency not supported\n");
1492 status = false;
1493 break;
1494 }
1495 */
1496
1497 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1498 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1499
1500 status &= INTERN_DVBC_Reset();
1501
1502 if (eQamMode == DMD_DVBC_QAMAUTO)
1503 {
1504 ULOGD("DEMOD","DMD_DVBC_QAMAUTO\n");
1505 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1506 // give default value.
1507 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1508 }
1509 else
1510 {
1511 ULOGD("DEMOD","DMD_DVBC_QAM %d\n", eQamMode);
1512 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1513 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1514 }
1515 // auto symbol rate enable/disable
1516 if (u16SymbolRate == 0)
1517 {
1518 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1519 }
1520 else
1521 {
1522 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1523 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1524 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1525 MS_U8 indx = 0;
1526 MS_U8 max_len = (E_DMD_DVBC_CFG_BW11_H - E_DMD_DVBC_CFG_BW0_L + 1)/2;
1527
1528 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1529
1530 if (max_len < u8_symbol_rate_list_num)
1531 {
1532 ULOGD("DEMOD","[a1_dvbc]Error!!! %s, %s, %d, max_len < u8_symbol_rate_list_num\n",__FILE__,__FUNCTION__,__LINE__);
1533
1534 // Force dvbc unlock.
1535 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, 0x01);
1536 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, 0x00);
1537 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW1_L, 0x00);
1538 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW1_H, 0x00);
1539 }
1540 else if (u8_symbol_rate_list_num == 0)
1541 {
1542 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1543 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1544 }
1545 else
1546 {
1547 for (indx = 0; indx < max_len ; indx++)
1548 {
1549 if (indx < u8_symbol_rate_list_num)
1550 {
1551 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2, (MS_U8)pu16_symbol_rate_list[indx]);
1552 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2 + 1, (MS_U8)(pu16_symbol_rate_list[indx]>>8));
1553 }
1554 else
1555 {
1556 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2, 0x00);
1557 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2 + 1, 0x00);
1558 }
1559 }
1560 }
1561 }
1562 // TS mode
1563 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1564
1565 // IQ Swap
1566 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1567
1568 // Fc
1569 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1570 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1571 // Lif
1572 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1573 // Fif
1574 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1575 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1576
1577 //// INTERN_DVBC system init: DVB-C //////////
1578 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1579
1580 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1581 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1582
1583 if (bSerialTS)
1584 {
1585 // serial
1586 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1587 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1588
1589 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1590 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1591 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1592 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1593 temp_val|=0x04;
1594 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1595 #else
1596 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1597 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1598 temp_val|=0x07;
1599 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1600 #endif
1601 }
1602 else
1603 {
1604 //parallel
1605 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1606 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1607
1608 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1609 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1610 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1611 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1612 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1613 temp_val|=0x05;
1614 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1615 #else
1616 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1617 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1618 temp_val|=0x07;
1619 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1620 #endif
1621 }
1622 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1623 INTERN_DVBC_Show_Demod_Version();
1624 #endif
1625
1626 return status;
1627 }
1628 /************************************************************************************************
1629 Subject: enable hw to lock channel
1630 Function: INTERN_DVBC_Active
1631 Parmeter: bEnable
1632 Return: MS_BOOL
1633 Remark:
1634 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1635 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1636 {
1637 MS_U8 status = true;
1638 MS_U8 reg_frz = 0, reg_frza = 0;
1639
1640 ULOGD("DEMOD"," @INTERN_DVBC_active\n");
1641
1642 //// INTERN_DVBC Finite State Machine on/off //////////
1643 #if 0
1644 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1645
1646 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1647 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1648 #else
1649 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1650 #endif
1651
1652 #if (1)//vesion check here
1653 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_PARAM_VERSION, ®_frz);
1654 ULOGD("DEMOD","##########DVBC------>(Driver) = 0x%x #########\n" , reg_frz);
1655 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_OP_RFAGC_EN, ®_frza);
1656 ULOGD("DEMOD","##########DVBC------>(FW) = 0x%x #########\n" , reg_frza);
1657 if (reg_frz < reg_frza)
1658 {
1659 while(1)
1660 ULOGD("DEMOD","##########--------->Abnormal case, please update demod utopia driver version!!! #########\n");
1661 }
1662 else{
1663 ULOGD("DEMOD","##########--------->Normal case! #########\n");
1664 }
1665 #endif
1666
1667 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1668 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1669 return status;
1670 }
1671
1672
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)1673 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1674 {
1675 MS_U16 u16Address = 0;
1676 MS_U8 cData = 0;
1677 MS_U8 cBitMask = 0;
1678
1679 if (fCurrRFPowerDbm < 100.0f)
1680 {
1681 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1682 {
1683 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE6, &cData);
1684 if (cData > 5)
1685 {
1686 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1687 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1688 }
1689 else
1690 {
1691 if ((fCurrRFPowerDbm<fNoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000))
1692 {
1693 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1694 }
1695 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1696 {
1697 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1698 #ifdef MS_DEBUG
1699 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1700 #endif
1701 return TRUE;
1702 }
1703 }
1704 #ifdef MS_DEBUG
1705 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%f Threshold:%f Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1706 #endif
1707 }
1708 }
1709
1710 {
1711 switch( eType )
1712 {
1713 case DMD_DVBC_GETLOCK_FEC_LOCK:
1714 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE6, &cData);
1715 #if (INTERN_DVBC_INTERNAL_DEBUG)
1716 INTERN_DVBC_info();
1717 #endif
1718 ULOGD("DEMOD"," @INTERN_DVBC_GetLock FSM 0x%x\n",cData);
1719 if (cData == 0x0C)
1720 {
1721 if(g_dvbc_lock == 0)
1722 {
1723 g_dvbc_lock = 1;
1724 ULOGD("DEMOD","[T12][DVBC]lock++++\n");
1725
1726 }
1727 return TRUE;
1728 }
1729 else
1730 {
1731 if(g_dvbc_lock == 1)
1732 {
1733 g_dvbc_lock = 0;
1734 ULOGD("DEMOD","[T12][DVBC]unlock----\n");
1735 }
1736 return FALSE;
1737 }
1738 break;
1739
1740 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1741 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1742 cBitMask = BIT(1);
1743 break;
1744
1745 case DMD_DVBC_GETLOCK_DCR_LOCK:
1746 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1747 cBitMask = BIT(0);
1748 break;
1749
1750 case DMD_DVBC_GETLOCK_AGC_LOCK:
1751 u16Address = TDP_REG_BASE + 0x29; //AGC Lock,
1752 cBitMask = BIT(0);
1753 break;
1754
1755 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1756 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1757 cBitMask = BIT(2)|BIT(3)|BIT(4);
1758 #ifdef MS_DEBUG
1759 {
1760 MS_U8 reg_frz=0, FSM=0;
1761 MS_U16 u16Timer=0;
1762 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE6, &FSM);
1763 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1764 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1765 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1766 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1767 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1768 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1769 u16Timer=(u16Timer<<8)+reg_frz;
1770 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1771 u16Timer=(u16Timer<<8)+reg_frz;
1772 ULOGD("DEMOD","DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1773 }
1774 #endif
1775 break;
1776
1777 case DMD_DVBC_GETLOCK_ATV_DETECT:
1778 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1779 cBitMask = BIT(1); // check atv
1780 break;
1781
1782 case DMD_DVBC_GETLOCK_TR_LOCK:
1783 #if 0 // 20111108 temporarily solution
1784 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
1785 cBitMask = BIT(4);
1786 break;
1787 #endif
1788 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1789 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1790 cBitMask = BIT(4);
1791 break;
1792
1793 default:
1794 return FALSE;
1795 }
1796
1797 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1798 return FALSE;
1799
1800 if ((cData & cBitMask) != 0)
1801 {
1802 return TRUE;
1803 }
1804
1805 return FALSE;
1806 }
1807
1808 return FALSE;
1809 }
1810
1811
1812 /****************************************************************************
1813 Subject: To get the Post viterbi BER
1814 Function: INTERN_DVBC_GetPostViterbiBer
1815 Parmeter: Quility
1816 Return: E_RESULT_SUCCESS
1817 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1818 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1819 We will not read the Period, and have the "/256/8"
1820 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(float * ber)1821 MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber)
1822 {
1823 MS_BOOL status = true;
1824 MS_U8 reg = 0, reg_frz = 0;
1825 MS_U16 BitErrPeriod;
1826 MS_U32 BitErr;
1827 MS_U16 PktErr;
1828
1829 /////////// Post-Viterbi BER /////////////
1830
1831 // bank 3f 0x03 [1:0] reg_bit_err_num_freeze
1832 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x32, ®_frz);
1833 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32, reg_frz|0x80);
1834
1835 // bank 3f 0x46 [7:0] reg_bit_err_sblprd_7_0
1836 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x31, ®);
1838 BitErrPeriod = reg;
1839
1840 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x30, ®);
1841 BitErrPeriod = (BitErrPeriod << 8)|reg;
1842
1843 // bank 3f 0x6a [7:0] reg_bit_err_num_7_0
1844 // 0x6b [15:8] reg_bit_err_num_15_8
1845 // bank 3f 0x6c [7:0] reg_bit_err_num_23_16
1846 // 0x6d [15:8] reg_bit_err_num_31_24
1847 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3D, ®);
1848 BitErr = reg;
1849
1850 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3C, ®);
1851 BitErr = (BitErr << 8)|reg;
1852
1853 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3B, ®);
1854 BitErr = (BitErr << 8)|reg;
1855
1856 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3A, ®);
1857 BitErr = (BitErr << 8)|reg;
1858
1859 INTERN_DVBC_GetPacketErr(&PktErr);
1860
1861 // bank 3f 0x03 [1:0] reg_bit_err_num_freeze
1862 reg_frz=reg_frz&(~0x80);
1863 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32, reg_frz);
1864
1865 if (BitErrPeriod == 0 ) //protect 0
1866 BitErrPeriod = 1;
1867
1868 if (BitErr <=0 )
1869 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1870 else
1871 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1872
1873 ULOGD("DEMOD","INTERN_DVBC PostVitBER = %8.3e \n ", *ber);
1874
1875 return status;
1876 }
1877
1878
1879 /****************************************************************************
1880 Subject: To get the Packet error
1881 Function: INTERN_DVBC_GetPacketErr
1882 Parmeter: pktErr
1883 Return: E_RESULT_SUCCESS
1884 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1885 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1886 We will not read the Period, and have the "/256/8"
1887 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1888 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1889 {
1890 MS_BOOL status = true;
1891 MS_U8 reg = 0, reg_frz = 0;
1892 MS_U16 PktErr;
1893
1894 // bank 3f 0x03 [1:0] reg_bit_err_num_freeze
1895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x32, ®_frz);
1896 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32, reg_frz|0x80);
1897
1898 // bank 3f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1899 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1900 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3f, ®);
1901 PktErr = reg;
1902
1903 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3e, ®);
1904 PktErr = (PktErr << 8)|reg;
1905
1906 // bank 3f 0x03 [1:0] reg_bit_err_num_freeze
1907 reg_frz=reg_frz&(~0x80);
1908 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32, reg_frz);
1909
1910 ULOGD("DEMOD","INTERN_DVBC PktErr = %d \n ", (int)PktErr);
1911 *pktErr = PktErr;
1912
1913 return status;
1914 }
1915
1916 /****************************************************************************
1917 Subject: Read the signal to noise ratio (SNR)
1918 Function: INTERN_DVBC_GetSNR
1919 Parmeter: None
1920 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1921 Remark:
1922 *****************************************************************************/
INTERN_DVBC_GetSNR(float * f_snr)1923 MS_BOOL INTERN_DVBC_GetSNR(float *f_snr)
1924 {
1925 MS_BOOL status = true;
1926 MS_U8 u8Data = 0;
1927 // MS_U8 freeze = 0;
1928 MS_U16 noisepower = 0;
1929
1930 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1931 {
1932 #if 1
1933 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1934 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x20);
1935 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80);
1936 // read vk
1937 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45, &u8Data);
1938 noisepower = u8Data;
1939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44, &u8Data);
1940 noisepower = (noisepower<<8)|u8Data;
1941
1942 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1943 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x00);
1944 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00);
1945 #else
1946 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1947 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1948 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1949
1950 // read vk
1951 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data);
1952 noisepower = u8Data;
1953 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data);
1954 noisepower = (noisepower<<8)|u8Data;
1955
1956 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1957 reg_frz=reg_frz&(~0x01);
1958 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1959 #endif
1960 if(noisepower == 0x0000)
1961 noisepower = 0x0001;
1962
1963 #ifdef MSOS_TYPE_LINUX
1964 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1965 #else
1966 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1967 #endif
1968
1969 }
1970 else
1971 {
1972 *f_snr = 0.0f;
1973 }
1974 return status;
1975
1976
1977 }
1978
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1979 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1980 {
1981 MS_BOOL status = true;
1982 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1983 DMD_DVBC_MODULATION_TYPE Qam_mode;
1984
1985 //ULOGD("DEMOD","INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi));
1986
1987 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1988 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1989 /* Actually, it's more reasonable, that signal level depended on cable input power level
1990 * thougth the signal isn't dvb-t signal.
1991 */
1992 // use pointer of IFAGC table to identify
1993 // case 1: RFAGC from SAR, IFAGC controlled by demod
1994 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1995 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1996 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
1997 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1998 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1999 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
2000 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
2001
2002 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
2003
2004 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
2005 {
2006 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
2007 }
2008 else
2009 {
2010 ch_power_db_rel = -100.0f;
2011 }
2012
2013 if(ch_power_db_rel <= -85.0f)
2014 {*strength = 0;}
2015 else if (ch_power_db_rel <= -80.0f)
2016 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
2017 else if (ch_power_db_rel <= -75.0f)
2018 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
2019 else if (ch_power_db_rel <= -70.0f)
2020 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
2021 else if (ch_power_db_rel <= -65.0f)
2022 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
2023 else if (ch_power_db_rel <= -55.0f)
2024 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
2025 else if (ch_power_db_rel <= -45.0f)
2026 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
2027 else
2028 {*strength = 100;}
2029
2030 ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength);
2031 ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength);
2032
2033 return status;
2034 }
2035
2036 /****************************************************************************
2037 Subject: To get the DVT Signal quility
2038 Function: INTERN_DVBC_GetSignalQuality
2039 Parmeter: Quility
2040 Return: E_RESULT_SUCCESS
2041 E_RESULT_FAILURE
2042 Remark: Here we have 4 level range
2043 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2044 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2045 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2046 <4>.4th Range => Quality <10
2047 *****************************************************************************/
INTERN_DVBC_GetSignalQuality(MS_U16 * quality,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2048 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2049 {
2050
2051 float fber;
2052 float log_ber;
2053 MS_BOOL status = true;
2054 DMD_DVBC_MODULATION_TYPE Qam_mode;
2055 float f_snr;
2056
2057 fRFPowerDbm = fRFPowerDbm;
2058 status &= INTERN_DVBC_GetSNR(&f_snr);
2059 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
2060 {
2061 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
2062 {
2063 ULOGD("DEMOD","\nGetPostViterbiBer Fail!");
2064 return FALSE;
2065 }
2066
2067 // log_ber = log10(fber)
2068 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
2069
2070 ULOGD("DEMOD","\nLog(BER) = %f",log_ber);
2071 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
2072 if (Qam_mode == DMD_DVBC_QAM16)
2073 {
2074 if(log_ber <= (-5.5f))
2075 *quality = 100;
2076 else if(log_ber <= (-5.1f))
2077 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
2078 else if(log_ber <= (-4.9f))
2079 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2080 else if(log_ber <= (-4.5f))
2081 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
2082 else if(log_ber <= (-3.7f))
2083 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
2084 else if(log_ber <= (-3.2f))
2085 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2086 else if(log_ber <= (-2.9f))
2087 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2088 else if(log_ber <= (-2.5f))
2089 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
2090 else if(log_ber <= (-2.2f))
2091 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
2092 else if(log_ber <= (-2.0f))
2093 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2094 else
2095 *quality = 0;
2096 }
2097 else if (Qam_mode == DMD_DVBC_QAM32)
2098 {
2099 if(log_ber <= (-5.0f))
2100 *quality = 100;
2101 else if(log_ber <= (-4.7f))
2102 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
2103 else if(log_ber <= (-4.5f))
2104 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
2105 else if(log_ber <= (-3.8f))
2106 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
2107 else if(log_ber <= (-3.5f))
2108 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
2109 else if(log_ber <= (-3.0f))
2110 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
2111 else if(log_ber <= (-2.7f))
2112 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
2113 else if(log_ber <= (-2.4f))
2114 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2115 else if(log_ber <= (-2.2f))
2116 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2117 else if(log_ber <= (-2.0f))
2118 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2119 else
2120 *quality = 0;
2121 }
2122 else if (Qam_mode == DMD_DVBC_QAM64)
2123 {
2124 if(log_ber <= (-5.4f))
2125 *quality = 100;
2126 else if(log_ber <= (-5.1f))
2127 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
2128 else if(log_ber <= (-4.9f))
2129 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2130 else if(log_ber <= (-4.3f))
2131 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
2132 else if(log_ber <= (-3.7f))
2133 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
2134 else if(log_ber <= (-3.2f))
2135 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2136 else if(log_ber <= (-2.9f))
2137 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2138 else if(log_ber <= (-2.4f))
2139 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
2140 else if(log_ber <= (-2.2f))
2141 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2142 else if(log_ber <= (-2.05f))
2143 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
2144 else
2145 *quality = 0;
2146 }
2147 else if (Qam_mode == DMD_DVBC_QAM128)
2148 {
2149 if(log_ber <= (-5.1f))
2150 *quality = 100;
2151 else if(log_ber <= (-4.9f))
2152 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2153 else if(log_ber <= (-4.7f))
2154 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
2155 else if(log_ber <= (-4.1f))
2156 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
2157 else if(log_ber <= (-3.5f))
2158 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
2159 else if(log_ber <= (-3.1f))
2160 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2161 else if(log_ber <= (-2.7f))
2162 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2163 else if(log_ber <= (-2.5f))
2164 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
2165 else if(log_ber <= (-2.06f))
2166 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
2167 //else if(log_ber <= (-2.05))
2168 else
2169 {
2170 if (f_snr >= 27.2f)
2171 *quality = 20;
2172 else if (f_snr >= 25.1f)
2173 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
2174 else
2175 *quality = 0;
2176 }
2177 }
2178 else //256QAM
2179 {
2180 if(log_ber <= (-4.8f))
2181 *quality = 100;
2182 else if(log_ber <= (-4.6f))
2183 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
2184 else if(log_ber <= (-4.4f))
2185 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
2186 else if(log_ber <= (-4.0f))
2187 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
2188 else if(log_ber <= (-3.5f))
2189 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
2190 else if(log_ber <= (-3.1f))
2191 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2192 else if(log_ber <= (-2.7f))
2193 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2194 else if(log_ber <= (-2.4f))
2195 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2196 else if(log_ber <= (-2.06f))
2197 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
2198 //else if(log_ber <= (-2.05))
2199 else
2200 {
2201 if (f_snr >= 29.6f)
2202 *quality = 20;
2203 else if (f_snr >= 27.3f)
2204 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
2205 else
2206 *quality = 0;
2207 }
2208 }
2209 }
2210 else
2211 {
2212 *quality = 0;
2213 }
2214
2215 //DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2216 ULOGD("DEMOD","BER = %8.3e\n", fber);
2217 ULOGD("DEMOD","Signal Quility = %d\n", *quality);
2218 return TRUE;
2219 }
2220
2221 /****************************************************************************
2222 Subject: To get the Cell ID
2223 Function: INTERN_DVBC_Get_CELL_ID
2224 Parmeter: point to return parameter cell_id
2225
2226 Return: TRUE
2227 FALSE
2228 Remark:
2229 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)2230 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
2231 {
2232 MS_BOOL status = true;
2233 MS_U8 value1 = 0;
2234 MS_U8 value2 = 0;
2235
2236 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
2237 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
2238
2239 *cell_id = ((MS_U16)value1<<8)|value2;
2240 return status;
2241 }
2242
2243 /****************************************************************************
2244 Subject: To get the DVBC Carrier Freq Offset
2245 Function: INTERN_DVBC_Get_FreqOffset
2246 Parmeter: Frequency offset (in KHz), bandwidth
2247 Return: E_RESULT_SUCCESS
2248 E_RESULT_FAILURE
2249 Remark:
2250 *****************************************************************************/
INTERN_DVBC_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2251 MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2252 {
2253 MS_U16 FreqB, config_Fc=0;
2254 float FreqCfo_offset,f_Fc;
2255 MS_U32 RegCfo_offset, Reg_Fc_over_Fs;
2256 MS_U8 reg = 0;
2257 MS_BOOL status = TRUE;
2258
2259 // no use.
2260 u8BW = u8BW;
2261
2262 ULOGD("DEMOD","INTERN_DVBC_Get_FreqOffset\n");
2263 #if 1
2264 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2265 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x20);
2266 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80);
2267
2268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, ®);
2269 RegCfo_offset = reg;
2270 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, ®);
2271 RegCfo_offset = (RegCfo_offset<<8)|reg;
2272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, ®);
2273 RegCfo_offset = (RegCfo_offset<<8)|reg;
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, ®);
2275 RegCfo_offset = (RegCfo_offset<<8)|reg;
2276
2277 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2278 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x00);
2279 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00);
2280 #else
2281 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2282 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
2283 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
2284
2285 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, ®);
2286 RegCfo_offset = reg;
2287 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, ®);
2288 RegCfo_offset = (RegCfo_offset<<8)|reg;
2289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, ®);
2290 RegCfo_offset = (RegCfo_offset<<8)|reg;
2291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, ®);
2292 RegCfo_offset = (RegCfo_offset<<8)|reg;
2293
2294 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2295 reg_frz=reg_frz&(~0x01);
2296 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
2297 #endif
2298 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
2299 Reg_Fc_over_Fs = reg;
2300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
2301 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2302 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
2303 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2304 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
2305 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2306
2307 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
2308 config_Fc = reg;
2309 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
2310 config_Fc = (config_Fc<<8)|reg;
2311
2312 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
2313
2314 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
2315
2316 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
2317
2318 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
2319
2320 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
2321 //ULOGD("DEMOD","[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
2322 // FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc);
2323
2324 *pFreqOff = FreqCfo_offset;
2325
2326 return status;
2327 }
2328
2329
2330
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)2331 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
2332 {
2333
2334 bPowerOn = bPowerOn;
2335 }
2336
INTERN_DVBC_Power_Save(void)2337 MS_BOOL INTERN_DVBC_Power_Save(void)
2338 {
2339
2340 return TRUE;
2341 }
2342
2343 /****************************************************************************
2344 Subject: To get the current modulation type at the DVB-C Demod
2345 Function: INTERN_DVBC_GetCurrentModulationType
2346 Parmeter: pointer for return QAM type
2347
2348 Return: TRUE
2349 FALSE
2350 Remark:
2351 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)2352 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
2353 {
2354 MS_U8 u8Data=0;
2355
2356 ULOGD("DEMOD","INTERN_DVBC_GetCurrentModulationType\n");
2357 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &u8Data);
2358 // MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0xC4, &u8Data);
2359
2360 switch(u8Data&0x07)
2361 {
2362 case 0:
2363 *pQAMMode = DMD_DVBC_QAM16;
2364 ULOGD("DEMOD","[dvbc]QAM=16\n");
2365 return TRUE;
2366 break;
2367 case 1:
2368 *pQAMMode = DMD_DVBC_QAM32;
2369 ULOGD("DEMOD","[dvbc]QAM=32\n");
2370 return TRUE;
2371 break;
2372 case 2:
2373 *pQAMMode = DMD_DVBC_QAM64;
2374 ULOGD("DEMOD","[dvbc]QAM=64\n");
2375 return TRUE;
2376 break;
2377 case 3:
2378 *pQAMMode = DMD_DVBC_QAM128;
2379 ULOGD("DEMOD","[dvbc]QAM=128\n");
2380 return TRUE;
2381 break;
2382 case 4:
2383 *pQAMMode = DMD_DVBC_QAM256;
2384 ULOGD("DEMOD","[dvbc]QAM=256\n");
2385 return TRUE;
2386 break;
2387 default:
2388 *pQAMMode = DMD_DVBC_QAMAUTO;
2389 ULOGD("DEMOD","[dvbc]QAM=invalid\n");
2390 return FALSE;
2391 }
2392 }
2393
2394 /****************************************************************************
2395 Subject: To get the current symbol rate at the DVB-C Demod
2396 Function: INTERN_DVBC_GetCurrentSymbolRate
2397 Parmeter: pointer pData for return Symbolrate
2398
2399 Return: TRUE
2400 FALSE
2401 Remark:
2402 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)2403 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
2404 {
2405 MS_U8 tmp = 0;
2406 MS_U16 u16SymbolRateTmp = 0;
2407
2408 // intp
2409 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd2, &tmp);
2410 u16SymbolRateTmp = tmp;
2411 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd1, &tmp);
2412 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
2413
2414 if (abs(u16SymbolRateTmp-6900)<2)
2415 {
2416 u16SymbolRateTmp=6900;
2417 }
2418
2419 if (abs(u16SymbolRateTmp-6875)<2)
2420 {
2421 u16SymbolRateTmp=6875;
2422 }
2423
2424 *u16SymbolRate = u16SymbolRateTmp;
2425
2426 ULOGD("DEMOD","[dvbc]SR=%d\n",*u16SymbolRate);
2427
2428 return TRUE;
2429 }
2430
2431
2432 /****************************************************************************
2433 Subject: To get the current symbol rate offset at the DVB-C Demod
2434 Function: INTERN_DVBC_GetCurrentSymbolRate
2435 Parmeter: pointer pData for return Symbolrate offset
2436
2437 Return: TRUE
2438 FALSE
2439 Remark:
2440 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 * pData)2441 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
2442 {
2443 MS_U8 u8Data = 0, reg_frz = 0;
2444 MS_U32 u32Data = 0;
2445 // MS_S32 s32Data = 0;
2446 MS_BOOL status = TRUE;
2447 MS_U16 u16SymbolRate = 0;
2448 float f_symb_offset = 0.0f;
2449
2450
2451
2452 // bank 26 0x03 [7] reg_bit_err_num_freeze
2453 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
2454 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
2455
2456 // sel, SFO debug output.
2457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
2458 u32Data = u8Data;
2459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
2460 u32Data = (u32Data<<8)|u8Data;
2461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
2462 u32Data = (u32Data<<8)|u8Data;
2463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
2464 u32Data = (u32Data<<8)|u8Data;
2465
2466 // bank 26 0x03 [7] reg_bit_err_num_freeze
2467 reg_frz=reg_frz&(~0x80);
2468 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
2469 // s32Data = (MS_S32)(u32Data<<8);
2470
2471 ULOGD("DEMOD","[dvbc]u32_symb_offset = 0x%x\n",u32Data);
2472
2473 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2474
2475 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
2476 f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
2477
2478 *pData = (MS_U16)(f_symb_offset + 0.5f);
2479
2480 ULOGD("DEMOD","[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset);
2481
2482 return status;
2483 }
2484
INTERN_DVBC_Version(MS_U16 * ver)2485 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2486 {
2487
2488 MS_U8 status = true;
2489 MS_U8 tmp = 0;
2490 MS_U16 u16_INTERN_DVBC_Version;
2491
2492 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2493 u16_INTERN_DVBC_Version = tmp;
2494 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2495 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2496 *ver = u16_INTERN_DVBC_Version;
2497
2498 return status;
2499 }
2500
2501
INTERN_DVBC_Show_Demod_Version(void)2502 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2503 {
2504
2505 MS_BOOL status = true;
2506 MS_U16 u16_INTERN_DVBC_Version;
2507
2508 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2509
2510 ULOGD("DEMOD","[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2511
2512 return status;
2513 }
2514
2515
2516
2517 #if (INTERN_DVBC_INTERNAL_DEBUG)
2518
INTERN_DVBC_Show_AGC_Info(void)2519 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2520 {
2521 MS_U8 tmp = 0;
2522 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2523 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2524 MS_U16 if_agc_err = 0;
2525 MS_BOOL status = TRUE;
2526
2527 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2528 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2529 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2530 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2531 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2532 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2533
2534
2535 // select IF gain to read
2536 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2537 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2538
2539 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2540 if_agc_gain = tmp;
2541 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2542 if_agc_gain = (if_agc_gain<<8)|tmp;
2543
2544
2545 // select d1 gain to read.
2546 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2547 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2548
2549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2550 d1_gain = tmp;
2551 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2552 d1_gain = (d1_gain<<8)|tmp;
2553
2554 // select d2 gain to read.
2555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2557
2558 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2559 d2_gain = tmp;
2560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2561 d2_gain = (d2_gain<<8)|tmp;
2562
2563 // select IF gain err to read
2564 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2565 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2566
2567 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2568 if_agc_err = tmp;
2569 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2570 if_agc_err = (if_agc_err<<8)|tmp;
2571
2572 ULOGD("DEMOD","[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2573 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2574
2575 ULOGD("DEMOD","[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2576
2577 return status;
2578 }
2579
INTERN_DVBC_info(void)2580 void INTERN_DVBC_info(void)
2581 {
2582 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2583 MS_U8 qam,tmp = 0;
2584 MS_U8 fft_u8 = 0;
2585 MS_U16 fft_u16bw = 0;
2586 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2587 float f_snr = 0,f_freq = 0;
2588 DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2589 MS_U16 f_start = 0,f_end = 0;
2590 MS_U8 s0_count = 0;
2591 MS_U8 sc4 = 0,sc3 = 0;
2592 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2593 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2594 MS_U16 count = 0;
2595 MS_U16 fb_i_1,fb_q_1;
2596 MS_U8 e0,e1,e2,e3;
2597 MS_S16 reg_freq;
2598 float freq,mag;
2599
2600
2601
2602 INTERN_DVBC_Version(&version);
2603
2604 // fb_fs
2605 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2606 fb_fs = tmp;
2607 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2608 fb_fs = (fb_fs<<8)|tmp;
2609 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2610 fb_fs = (fb_fs<<8)|tmp;
2611 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2612 fb_fs = (fb_fs<<8)|tmp;
2613 // fc_fs
2614 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2615 fc_fs = tmp;
2616 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2617 fc_fs = (fc_fs<<8)|tmp;
2618 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2619 fc_fs = (fc_fs<<8)|tmp;
2620 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2621 fc_fs = (fc_fs<<8)|tmp;
2622 // crv
2623 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2624 crv = tmp;
2625 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2626 crv = (crv<<8)|tmp;
2627 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2628 crv = (crv<<8)|tmp;
2629 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2630 crv = (crv<<8)|tmp;
2631 // tr_error
2632 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2633 tr_error = tmp;
2634 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2635 tr_error = (tr_error<<8)|tmp;
2636 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2637 tr_error = (tr_error<<8)|tmp;
2638
2639 // intp
2640 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2641 intp = tmp;
2642 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2643 intp = (intp<<8)|tmp;
2644 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2645 intp = (intp<<8)|tmp;
2646 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2647 intp = (intp<<8)|tmp;
2648
2649 // fft info
2650 // intp
2651 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2652 fft_u16bw = tmp;
2653 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2654 fft_u16bw = (fft_u16bw<<8)|tmp;
2655 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2656 fft_u8 = tmp;
2657
2658
2659 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2660 qam = tmp;
2661
2662 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2663 f_start = tmp;
2664 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2665 f_start = (f_start<<8)|tmp;
2666 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2667 f_end = tmp;
2668 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2669 f_end = (f_end<<8)|tmp;
2670 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2671 s0_count = tmp;
2672
2673 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2674 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2675
2676 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2677 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2678 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2679 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2680 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2681 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2682 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2683
2684
2685 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2686
2687 count = 0x400;
2688 while(count--);
2689
2690 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2691 aci_e0 = tmp&0x0f;
2692 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2693 aci_e0 = aci_e0<<8|tmp;
2694
2695 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2696
2697 count = 0x400;
2698 while(count--);
2699
2700
2701 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2702 aci_e1 = tmp&0x0f;
2703 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2704 aci_e1 = aci_e1<<8|tmp;
2705
2706 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2707
2708 count = 0x400;
2709 while(count--);
2710
2711 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2712 aci_e2 = tmp&0x0f;
2713 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2714 aci_e2 = aci_e2<<8|tmp;
2715
2716 // read aci coef
2717 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2718
2719 count = 0x400;
2720 while(count--);
2721
2722 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2723 aci_e3 = tmp&0x0f;
2724 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2725 aci_e3 = aci_e3<<8|tmp;
2726
2727 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2728 fb_i_1 = tmp;
2729 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2730 fb_i_1 = fb_i_1<<8|tmp;
2731
2732 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2733 fb_q_1 = tmp;
2734 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2735 fb_q_1 = fb_q_1<<8|tmp;
2736
2737
2738 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2739 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2740 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2741 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2742
2743 reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2744 freq = (float)reg_freq*45473.0/65536.0;
2745 mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2746
2747
2748 INTERN_DVBC_GetPacketErr(&packetErr);
2749 INTERN_DVBC_GetSNR(&f_snr);
2750 INTERN_DVBC_Show_AGC_Info();
2751 INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2752 INTERN_DVBC_Get_FreqOffset(&f_freq,8);
2753 INTERN_DVBC_GetCurrentSymbolRate(&symb_rate);
2754 INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2755 INTERN_DVBC_GetCurrentModulationType(&QAMMode);
2756
2757 ULOGD("DEMOD","[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2758 ULOGD("DEMOD","[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2759 ULOGD("DEMOD","[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2760 ULOGD("DEMOD","[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2761 ULOGD("DEMOD","[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2762 ULOGD("DEMOD","[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2763 return;
2764 }
2765
2766
2767 #endif
2768
2769 /***********************************************************************************
2770 Subject: read register
2771 Function: MDrv_1210_IIC_Bypass_Mode
2772 Parmeter:
2773 Return:
2774 Remark:
2775 ************************************************************************************/
2776 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2777 //{
2778 // UNUSED(enable);
2779 // if (enable)
2780 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2781 // else
2782 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2783 //}
2784