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93 ////////////////////////////////////////////////////////////////////////////////
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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #define TEST_EMBEDED_DEMOD 0
129 //U8 load_data_variable=1;
130 //-----------------------------------------------------------------------
131 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
132
133 #define TDE_REG_BASE 0x2400UL
134 #define DIV_REG_BASE 0x2500UL
135 #define TR_REG_BASE 0x2600UL
136 #define FTN_REG_BASE 0x2700UL
137 #define FTNEXT_REG_BASE 0x2800UL
138
139
140
141 #if 0//ENABLE_SCAN_ONELINE_MSG
142 #define DBG_INTERN_DVBT_ONELINE(x) x
143 #else
144 #define DBG_INTERN_DVBT_ONELINE(x) // x
145 #endif
146
147 #ifdef MS_DEBUG
148 #define DBG_INTERN_DVBT(x) x
149 #define DBG_GET_SIGNAL(x) x
150 #define DBG_INTERN_DVBT_TIME(x) x
151 #define DBG_INTERN_DVBT_LOCK(x) x
152 #else
153 #define DBG_INTERN_DVBT(x) //x
154 #define DBG_GET_SIGNAL(x) //x
155 #define DBG_INTERN_DVBT_TIME(x) // x
156 #define DBG_INTERN_DVBT_LOCK(x) //x
157 #endif
158 #define DBG_DUMP_LOAD_DSP_TIME 0
159
160 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
161 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
162 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
163
164 /*bryan temp close*/
165 #define INTERN_DVBT_INTERNAL_DEBUG 0
166
167 #define SIGNAL_LEVEL_OFFSET 0.00
168 #define TAKEOVERPOINT -59.0
169 #define TAKEOVERRANGE 0.5
170 #define LOG10_OFFSET -0.21
171 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
172 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
173
174
175 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
176 #define TUNER_VPP 2
177 #define IF_AGC_VPP 2
178 #else
179 #define TUNER_VPP 1
180 #define IF_AGC_VPP 2
181 #endif
182
183 #if (TUNER_VPP == 1)
184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
185 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
186 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
187 #endif
188
189 /*BEG INTERN_DVBT_DSPREG_TABLE*/
190 #define D_DMD_DVBT_PARAM_VERSION 0x01
191 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
192 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
193 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
194 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
195 #define D_DMD_DVBT_OP_DCR_EN 0x01
196 #define D_DMD_DVBT_OP_IIS_EN 0x01
197 #define D_DMD_DVBT_OP_IQB_EN 0x00
198 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
199 #define D_DMD_DVBT_OP_ACI_EN 0x01
200 #define D_DMD_DVBT_OP_CCI_EN 0x01
201 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
202 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
203 #define D_DMD_DVBT_CFG_BW 0x00 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
204 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
205 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
206 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
207 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
208 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
209 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
210 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
211 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
212 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
213 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
214 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
215 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
216 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
217 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
218 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
219 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
220 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
221 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
222 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
223
224 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
225 #define D_DMD_DVBT_CFG_FC_H 0x4E
226 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
227 #define D_DMD_DVBT_CFG_FS_H 0x5D
228 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
229
230 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
231 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
232 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
233 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
234 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
235 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
236 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
237 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
238 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
239 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
240 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
241 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
242
243 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
244 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
245 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
246 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
247 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
248 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
249 #else
250 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
251 #endif
252 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
253 //#define DMD_DVBT_CHECKSUM 0x00
254 /*END INTERN_DVBT_DSPREG_TABLE*/
255 #define DVBT_FS 45474 // 24000
256 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
257 #define FC_L 0x20 // 0323 jason
258 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
259 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
260 #define SET_ZIF 0x00
261 #define IQB_EN 0x00
262
263 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
264 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
265 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
266 #define CSTL 0x02 //0:QPSK 1:16 2: 64
267 #define HIER 0x00
268 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
269 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
270 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
271 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
272 #define LP_SEL 0x00 // LP select
273 #define IQ_SWAP 0x00 //0x01
274 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
275 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
276 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
277 #define TS_SER 0
278 #define TS_INV 0
279 #define FIF_H (MS_U8)(( (((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))>>8)
280 #define FIF_L (MS_U8)(( ((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))
281 #define IF_INV_PWM 0x00
282 #define T_LOWIF 1
283
284 MS_U8 INTERN_DVBT_DSPREG[] =
285 {
286 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
287 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
288 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
289 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
290 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
291 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
292 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
293 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
294 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
295 /*
296 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
297 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
298 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
299 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
300 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
301 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
302 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
303 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
304 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
305 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
306 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
307 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
308 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
309 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
310 */
311 };
312 /*END INTERN_DVBT_DSPREG_TABLE*/
313 //-----------------------------------------------------------------------
314 /****************************************************************
315 *Local Variables *
316 ****************************************************************/
317 static MS_BOOL bFECLock=0;
318 static MS_BOOL bTPSLock = 0;
319 static MS_U32 u32ChkScanTimeStart = 0;
320 static MS_U32 u32FecFirstLockTime=0;
321 static MS_U32 u32FecLastLockTime=0;
322 //bryan temp mark
323 #if(0)
324 static float fViterbiBerFiltered=-1;
325 #endif
326 //Global Variables
327 S_CMDPKTREG gsCmdPacket;
328 //U8 gCalIdacCh0, gCalIdacCh1;
329
330 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
331 MS_U8 INTERN_DVBT_table[] = {
332 #include "fwDMD_INTERN_DVBT.dat"
333 };
334
335 #endif
336
337 /*bryan temp mark*/
338 #if(0)
339 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
340 {
341 { _QPSK , _CR1Y2, -93},
342 { _QPSK , _CR2Y3, -91},
343 { _QPSK , _CR3Y4, -90},
344 { _QPSK , _CR5Y6, -89},
345 { _QPSK , _CR7Y8, -88},
346
347 { _16QAM , _CR1Y2, -87},
348 { _16QAM , _CR2Y3, -85},
349 { _16QAM , _CR3Y4, -84},
350 { _16QAM , _CR5Y6, -83},
351 { _16QAM , _CR7Y8, -82},
352
353 { _64QAM , _CR1Y2, -82},
354 { _64QAM , _CR2Y3, -80},
355 { _64QAM , _CR3Y4, -78},
356 { _64QAM , _CR5Y6, -77},
357 { _64QAM , _CR7Y8, -76},
358 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
359 };
360 #endif
361
362 /*bryan temp mark*/
363 #if(0)
364 static void INTERN_DVBT_SignalQualityReset(void);
365 #endif
366 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
367
368 #if(0)
INTERN_DVBT_SignalQualityReset(void)369 static void INTERN_DVBT_SignalQualityReset(void)
370 {
371 u32FecFirstLockTime=0;
372 fViterbiBerFiltered=-1;
373 }
374 #endif
375
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)376 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
377 {
378 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
379 MS_BOOL status = TRUE;
380 MS_U16 u16DspAddr = 0;
381
382 DBG_INTERN_DVBT(printf("INTERN_DVBT_DSPReg_Init\n"));
383
384 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
385 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
386
387 if (u8DVBT_DSPReg != NULL)
388 {
389 /*temp solution until new dsp table applied.*/
390 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
391 if (u8DVBT_DSPReg[0] >= 1)
392 {
393 u8DVBT_DSPReg+=2;
394 for (idx = 0; idx<u8Size; idx++)
395 {
396 u16DspAddr = *u8DVBT_DSPReg;
397 u8DVBT_DSPReg++;
398 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
399 u8DVBT_DSPReg++;
400 u8Mask = *u8DVBT_DSPReg;
401 u8DVBT_DSPReg++;
402 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
403 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
404 u8DVBT_DSPReg++;
405 DBG_INTERN_DVBT(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
406 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
407 }
408 }
409 else
410 {
411 printf("FATAL: parameter version incorrect\n");
412 }
413 }
414
415 return status;
416 }
417
418 /***********************************************************************************
419 Subject: Command Packet Interface
420 Function: INTERN_DVBT_Cmd_Packet_Send
421 Parmeter:
422 Return: MS_BOOL
423 Remark:
424 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)425 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
426 {
427 MS_U8 status = true, indx;
428 MS_U8 reg_val=0, timeout = 0;
429 return TRUE;
430 //MsOS_ObtainMutex(_s32_Demod_DVBT_Mutex, MSOS_WAIT_FOREVER);
431 // ==== Command Phase ===================
432 DBG_INTERN_DVBT(printf("--->INTERN_DVBT (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
433 pCmdPacket->param[0],pCmdPacket->param[1],
434 pCmdPacket->param[2],pCmdPacket->param[3],
435 pCmdPacket->param[4],pCmdPacket->param[5] ));
436
437 // wait _BIT_END clear
438 do
439 {
440 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
441 if((reg_val & _BIT_END) != _BIT_END)
442 {
443 break;
444 }
445 MsOS_DelayTask(5);
446 if (timeout++ > 200)
447 {
448 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
449 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
450 return false;
451 }
452 } while (1);
453
454 // set cmd_3:0 and _BIT_START
455 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
456 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
457 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
458
459
460 //DBG_INTERN_DVBT(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
461 // wait _BIT_START clear
462 do
463 {
464 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
465 if((reg_val & _BIT_START) != _BIT_START)
466 {
467 break;
468 }
469 MsOS_DelayTask(5);
470 if (timeout++ > 200)
471 {
472 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
473 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
474 return false;
475 }
476 } while (1);
477
478 // ==== Data Phase ======================
479
480 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
481
482 for (indx = 0; indx < param_cnt; indx++)
483 {
484 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
485 //DBG_INTERN_DVBT(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
486
487 // set param[indx] and _BIT_DRQ
488 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
489 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
490 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
491
492 // wait _BIT_DRQ clear
493 do
494 {
495 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
496 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
497 {
498 break;
499 }
500 MsOS_DelayTask(5);
501 if (timeout++ > 200)
502 {
503 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
504 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
505 return false;
506 }
507 } while (1);
508 }
509
510 // ==== End Phase =======================
511
512 // set _BIT_END to finish command
513 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
514 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
515 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
516 return status;
517 }
518
519
520 /***********************************************************************************
521 Subject: Command Packet Interface
522 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
523 Parmeter:
524 Return: MS_BOOL
525 Remark:
526 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)527 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
528 {
529 return TRUE;
530 }
531
532 /***********************************************************************************
533 Subject: SoftStop
534 Function: INTERN_DVBT_SoftStop
535 Parmeter:
536 Return: MS_BOOL
537 Remark:
538 ************************************************************************************/
539
INTERN_DVBT_SoftStop(void)540 MS_BOOL INTERN_DVBT_SoftStop ( void )
541 {
542 #if 1
543 MS_U16 u8WaitCnt=0;
544
545 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
546 {
547 printf(">> MB Busy!\n");
548 return FALSE;
549 }
550
551 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
552
553 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
554 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
555
556 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
557 {
558 #if TEST_EMBEDED_DEMOD
559 MsOS_DelayTask(1); // << Ken 20090629
560 #endif
561 if (u8WaitCnt++ >= 0xFF)
562 {
563 printf(">> DVBT SoftStop Fail!\n");
564 return FALSE;
565 }
566 }
567
568 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
569 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
570 #endif
571 return TRUE;
572 }
573
574
575 /***********************************************************************************
576 Subject: Reset
577 Function: INTERN_DVBT_Reset
578 Parmeter:
579 Return: MS_BOOL
580 Remark:
581 ************************************************************************************/
582 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)583 MS_BOOL INTERN_DVBT_Reset ( void )
584 {
585 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_reset\n"));
586
587 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime()));
588
589 INTERN_DVBT_SoftStop();
590
591
592 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
593 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
594 MsOS_DelayTask(5);
595 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
596 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
597 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
598 MsOS_DelayTask(5);
599
600 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
601 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
602
603 bFECLock = FALSE;
604 bTPSLock = FALSE;
605 u32ChkScanTimeStart = MsOS_GetSystemTime();
606 return TRUE;
607 }
608
609 /***********************************************************************************
610 Subject: Exit
611 Function: INTERN_DVBT_Exit
612 Parmeter:
613 Return: MS_BOOL
614 Remark:
615 ************************************************************************************/
INTERN_DVBT_Exit(void)616 MS_BOOL INTERN_DVBT_Exit ( void )
617 {
618
619 INTERN_DVBT_SoftStop();
620
621
622
623 return TRUE;
624 }
625
626 /***********************************************************************************
627 Subject: Load DSP code to chip
628 Function: INTERN_DVBT_LoadDSPCode
629 Parmeter:
630 Return: MS_BOOL
631 Remark:
632 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)633 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
634 {
635 MS_U8 udata = 0x00;
636 MS_U16 i;
637 MS_U16 fail_cnt=0;
638
639 #if (DBG_DUMP_LOAD_DSP_TIME==1)
640 MS_U32 u32Time;
641 #endif
642
643
644 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
645 BININFO BinInfo;
646 MS_BOOL bResult;
647 MS_U32 u32GEAddr;
648 MS_U8 Data;
649 MS_S8 op;
650 MS_U32 srcaddr;
651 MS_U32 len;
652 MS_U32 SizeBy4K;
653 MS_U16 u16Counter=0;
654 MS_U8 *pU8Data;
655 #endif
656
657 #if 0
658 if(HAL_DMD_RIU_ReadByte(0x101E3E))
659 {
660 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
661 return FALSE;
662 }
663 #endif
664
665 // MDrv_Sys_DisableWatchDog();
666
667
668 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
669 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
670 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
671 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
672 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
673 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
674
675 //// Load code thru VDMCU_IF ////
676 DBG_INTERN_DVBT(printf(">Load Code...\n"));
677 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
678 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
679 {
680 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
681 }
682 #else
683 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
684 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
685 if ( bResult != PASS )
686 {
687 return FALSE;
688 }
689 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
690
691 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
692 InfoBlock_Flash_2_Checking_Start(&BinInfo);
693 #endif
694
695 #if OBA2
696 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
697 #else
698 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
699 #endif
700
701 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
702 InfoBlock_Flash_2_Checking_End(&BinInfo);
703 #endif
704
705 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
706
707 //bryan temp mark
708 //SizeBy4K=BinInfo.B_Len/0x1000;
709 SizeBy4K=BinInfo.B_Len>>12; //deivde to 4096
710
711 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
712
713 #if (DBG_DUMP_LOAD_DSP_TIME==1)
714 u32Time = msAPI_Timer_GetTime0();
715 #endif
716
717 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
718
719 for (i=0;i<=SizeBy4K;i++)
720 {
721 if(i==SizeBy4K)
722 len=BinInfo.B_Len%0x1000;
723 else
724 len=0x1000;
725
726 srcaddr = u32GEAddr+(0x1000*i);
727 //printf("\t i = %08X\n", i);
728 //printf("\t len = %08X\n", len);
729 op = 1;
730 u16Counter = 0 ;
731 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
732 while(len--)
733 {
734 u16Counter ++ ;
735 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
736 //pU8Data = (U8 *)(srcaddr|0x80000000);
737 #if OBA2
738 pU8Data = (U8 *)(srcaddr);
739 #else
740 pU8Data = (U8 *)(srcaddr|0x80000000);
741 #endif
742 Data = *pU8Data;
743
744 #if 0
745 if(u16Counter < 0x100)
746 printf("0x%bx,", Data);
747 #endif
748 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
749
750 srcaddr += op;
751 }
752 // printf("\n\n\n");
753 }
754
755 #if (DBG_DUMP_LOAD_DSP_TIME==1)
756 printf("------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
757 #endif
758
759 #endif
760
761 //// Content verification ////
762 DBG_INTERN_DVBT(printf(">Verify Code...\n"));
763
764 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
765 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
766
767 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
768 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
769 {
770 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
771 if (udata != INTERN_DVBT_table[i])
772 {
773 printf(">fail add = 0x%x\n", i);
774 printf(">code = 0x%x\n", INTERN_DVBT_table[i]);
775 printf(">data = 0x%x\n", udata);
776
777 if (fail_cnt++ > 10)
778 {
779 printf(">DVB-T DSP Loadcode fail!");
780 return false;
781 }
782 }
783 }
784 #else
785 for (i=0;i<=SizeBy4K;i++)
786 {
787 if(i==SizeBy4K)
788 len=BinInfo.B_Len%0x1000;
789 else
790 len=0x1000;
791
792 srcaddr = u32GEAddr+(0x1000*i);
793 //printf("\t i = %08LX\n", i);
794 //printf("\t len = %08LX\n", len);
795 op = 1;
796 u16Counter = 0 ;
797 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
798 while(len--)
799 {
800 u16Counter ++ ;
801 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
802 //pU8Data = (U8 *)(srcaddr|0x80000000);
803 #if OBA2
804 pU8Data = (U8 *)(srcaddr);
805 #else
806 pU8Data = (U8 *)(srcaddr|0x80000000);
807 #endif
808 Data = *pU8Data;
809
810 #if 0
811 if(u16Counter < 0x100)
812 printf("0x%bx,", Data);
813 #endif
814 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
815 if (udata != Data)
816 {
817 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
818 printf(">code = 0x%x\n", Data);
819 printf(">data = 0x%x\n", udata);
820
821 if (fail_cnt++ > 10)
822 {
823 printf(">DVB-T DSP Loadcode fail!");
824 return false;
825 }
826 }
827
828 srcaddr += op;
829 }
830 // printf("\n\n\n");
831 }
832 #endif
833
834 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
835 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
836 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
837 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
838
839 DBG_INTERN_DVBT(printf(">DSP Loadcode done."));
840 //while(load_data_variable);
841
842
843 return TRUE;
844 }
845
846 /***********************************************************************************
847 Subject: DVB-T CLKGEN initialized function
848 Function: INTERN_DVBT_Power_On_Initialization
849 Parmeter:
850 Return: MS_BOOL
851 Remark:
852 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)853 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
854 {
855 MS_U8 temp_val;
856 MS_U8 udatatemp = 0x00;
857 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
858 // HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
859
860 // Release vivaldi2mi_bridge reset
861 // [0] reg_vivaldi2mi_bridge_rst
862 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
863 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
864 // HAL_DMD_RIU_WriteByte(0x11208E, (HAL_DMD_RIU_ReadByte(0x11208E)&(~(BIT(0)))));
865
866 // ----------------------------------------------
867 // start demod CLKGEN setting
868 // ----------------------------------------------
869 // *** Set register at CLKGEN1
870 // enable DMD MCU clock "bit[0] set 0"
871 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
872 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
873 // CLK_DMDMCU clock setting
874 // [0] disable clock
875 // [1] invert clock
876 // [4:2]
877 // 000:170 MHz(MPLL_DIV_BUf)
878 // 001:160MHz
879 // 010:144MHz
880 // 011:123MHz
881 // 100:108MHz
882 // 101:mem_clcok
883 // 110:mem_clock div 2
884 // 111:select XTAL
885 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
886 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
887
888 // set parallet ts clock
889 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
890 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
891
892 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b
893 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
894 temp_val|=0x07;
895 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
896
897 HAL_DMD_RIU_WriteByte(0x103300,0x17);
898
899 // enable atsc, DVBTC ts clock
900 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
901 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
902 HAL_DMD_RIU_WriteByte(0x103309,0x00);
903 HAL_DMD_RIU_WriteByte(0x103308,0x00);
904
905 // enable dvbc adc clock
906 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
907 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
908 HAL_DMD_RIU_WriteByte(0x103315,0x00);
909 HAL_DMD_RIU_WriteByte(0x103314,0x00);
910
911 udatatemp = HAL_DMD_RIU_ReadByte(0x111f2a);
912 HAL_DMD_RIU_WriteByte(0x111f2a,udatatemp&0xF8);
913
914 // Reset TS divider
915 HAL_DMD_RIU_WriteByte(0x103302,0x01);
916 HAL_DMD_RIU_WriteByte(0x103302,0x00);
917
918 // enable vif DAC clock
919 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
920 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
921 // HAL_DMD_RIU_WriteByte(0x10331b,0x00);
922 // HAL_DMD_RIU_WriteByte(0x10331a,0x00);
923
924 // Select MPLLDIV17
925 // [0] : reg_atsc_adc_sel_mplldiv2
926 // [1] : reg_atsc_eq_sel_mplldiv2
927 // [2] : reg_eq25_sel_mplldiv3
928 // [3] : reg_p4_cfo_sel_eq25
929 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
930 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
931 // HAL_DMD_RIU_WriteByte(0x111f28,0x03);
932
933 // *** Set register at CLKGEN_DMD
934 // enable atsc clock
935 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
936 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
937 // HAL_DMD_RIU_WriteByte(0x111f03,0x04);
938 // HAL_DMD_RIU_WriteByte(0x111f02,0x04);
939 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
940 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
941 // HAL_DMD_RIU_WriteByte(0x111f05,0x00);
942 // HAL_DMD_RIU_WriteByte(0x111f04,0x00);
943 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
944 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
945 // HAL_DMD_RIU_WriteByte(0x111f07,0x04);
946 // HAL_DMD_RIU_WriteByte(0x111f06,0x04);
947
948 // enable clk_atsc_adcd_sync
949 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
950 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
951 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
952 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
953
954 // enable dvbt inner clock
955 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
956 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
957 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
958 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
959
960 // enable dvbt inner clock
961 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
962 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
963 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
964 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
965
966 // enable dvbt inner clock
967 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
968 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
969 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
970 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
971
972 // enable dvbc outer clock
973 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
974 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
975 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
976 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
977
978 // enable dvbc inner-c clock
979 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
980 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
981 // HAL_DMD_RIU_WriteByte(0x111f15,0x00);
982 // HAL_DMD_RIU_WriteByte(0x111f14,0x00);
983
984 // enable dvbc eq clock
985 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
986 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
987 // HAL_DMD_RIU_WriteByte(0x111f17,0x00);
988 // HAL_DMD_RIU_WriteByte(0x111f16,0x00);
989
990 // enable sram clock
991 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
992 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
993 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
994 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
995
996 // select clock
997 // [3:0] : reg_ckg_frontend
998 // [0] : disable clock
999 // [1] : invert clock
1000 // [3:2]: Select clock source
1001 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
1002 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1003 // 10: reserved
1004 // 11: select DFT_CLK
1005 // [7:4] : reg_ckg_tr
1006 // [0] : disable clock
1007 // [1] : invert clock
1008 // [3:2]: Select clock source
1009 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
1010 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1011 // 10: reserved
1012 // 11: select DFT_CLK
1013 // [11:8]: reg_ckg_acifir
1014 // [0] : disable clock
1015 // [1] : invert clock
1016 // [3:2]: Select clock source
1017 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
1018 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1019 // 10: clk_vif_ssc_mux (43.2~50.82 MHz, VIF)
1020 // 11: select DFT_CLK
1021 // [15:12]: reg_ckg_frontend_d2
1022 // [0] : disable clock
1023 // [1] : invert clock
1024 // [3:2]: Select clock source
1025 // 00: clk_dmdadc_div2
1026 // 01: clk_dmplldiv17_div4(12.705 MHz)
1027 // 10: reserved
1028 // 11: select DFT_CLK
1029 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1030 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1031 // HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1032 // HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1033
1034 // enable isdbt clock
1035 // [2:0] : reg_ckg_isdbt_inner1x
1036 // [0] : disable clock
1037 // [1] : invert clock
1038 // [3:2]: Select clock source
1039 // 00: clk_dmplldiv10_div4(21.6MHz, ISDBT only)
1040 // 01: reserved
1041 // 10: reserved
1042 // 11: DFT_CLK
1043 // [6:4]: reg_ckg_isdbt_inner2x
1044 // [0] : disable clock
1045 // [1] : invert clock
1046 // [2]: Select clock source
1047 // 00: clk_dmplldiv10_div2(43.2MHz,ISDBT only)
1048 // 01: reserved
1049 // 10: reserved
1050 // 11: DFT_CLK
1051 // [10:8] : reg_ckg_isdbt_inner4x
1052 // [0] : disable clock
1053 // [1] : invert clock
1054 // [3:2]: Select clock source
1055 // 00: clk_dmplldiv10(86.4 MHz, DVBT only)
1056 // 01: reserved
1057 // 10: reserved
1058 // 11: DFT_CLK
1059 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1060 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1061 // HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1062 // HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1063
1064
1065 // enable isdbt outer clock
1066 // [3:0] : reg_ckg_isdbt_outer1x
1067 // [0] : disable clock
1068 // [1] : invert clock
1069 // [3:2]: Select clock source
1070 // 00: isdbt_clk6_lat (6 MHz)
1071 // 01: isdbt_clk8_lat (8 MHz)
1072 // 10: reserved
1073 // 11: DFT_CLK
1074 // [6:4]: reg_ckg_isdbt_outer4x
1075 // [0] : disable clock
1076 // [1] : invert clock
1077 // [3:2]: Select clock source
1078 // 00: isdbt_clk24_lat(24 MHz)
1079 // 01: isdbt_clk32_lat(32 MHz)
1080 // 10: reserved
1081 // 11: DFT_CLK
1082 // [10:8]: reg_ckg_isdbt_outer6x
1083 // [0] : disable clock
1084 // [1] : invert clock
1085 // [2] : Select clock source
1086 // 00: isdbt_clk36_lat(36 MHz)
1087 // 01: isdbt_clk48_lat(48 MHz)
1088 // 10: reserved
1089 // 11: DFT_CLK
1090 // [14:12]: reg_ckg_isdbt_outer12x
1091 // [0] : disable clock
1092 // [1] : invert clock
1093 // [2] : Select clock source
1094 // 00: isdbt_clk72_lat(72 MHz)
1095 // 01: isdbt_clk96_lat(96 MHz)
1096 // 10: reserved
1097 // 11: DFT_CLK
1098 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1099 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1100 // HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1101 // HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1102
1103 // Enable ISDBT clk_outer_div
1104 // reg_clk_isdbt_outer_div_en[0]
1105 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1106 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1107 // HAL_DMD_RIU_WriteByte(0x111f46,0x01);
1108
1109 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1110 // [1:0] : reg_ckg_dvbtc_sram4_isdbt_inner4x
1111 // [0]: disable clock
1112 // [1]: invert clock
1113 // [5:4] : reg_ckg_dvbtc_sram4_isdbt_outer6x
1114 // [0]: disable clock
1115 // [1]: invert clock
1116 // [9:8] : reg_ckg_adc1x_eq1x
1117 // [0]: disable clock
1118 // [1]: invert clock
1119 // [13:12] : reg_ckg_adc0p5x_eq0p5x
1120 // [0]: disable clock
1121 // [1]: invert clock
1122 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1123 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1124 HAL_DMD_RIU_WriteByte(0x111f49,0x00);
1125 HAL_DMD_RIU_WriteByte(0x111f48,0x00);
1126
1127 // [1:0] : reg_ckg_isdbt_outer6x_dvbt_inner1x
1128 // [0]: disable clock
1129 // [1]: invert clock
1130 // [5:4] : reg_ckg_isdbt_outer6x_dvbt_inner2x
1131 // [0]: disable clock
1132 // [1]: invert clock
1133 // [9:8] : reg_ckg_isdbt_outer6x_dvbt_outer2x
1134 // [0]: disable clock
1135 // [1]: invert clock
1136 // [13:12]: reg_ckg_isdbt_outer6x_dvbt_outer2x_c
1137 // [0]: disable clock
1138 // [1]: invert clock
1139 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1140 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1141 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
1142 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
1143
1144 // enable isdbt outer clock_rs
1145 // [7:4] : reg_ckg_isdbt_outer_rs
1146 // [0] : disable clock
1147 // [1] : invert clock
1148 // [3:2]: Select clock source
1149 // 00: isdbt_clk36_lat (36 MHz)
1150 // 01: isdbt_clk48_lat (48 MHz)
1151 // 10: clk_dmplldiv3_div4(72 MHz)
1152 // 11: isdbt_clk96_buf (96 MHz)
1153 // enable share isdbt &dvbt logic clock
1154 // [1:0] : reg_ckg_isdbt_inner2x_dvbt_inner2x
1155 // [0]: disable clock
1156 // [1]: invert clock
1157 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1158 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1159 // HAL_DMD_RIU_WriteByte(0x111f4c,0x00);
1160 HAL_DMD_RIU_WriteByte(0x111f4d,0x00);
1161 HAL_DMD_RIU_WriteByte(0x111f4c,0x10);
1162
1163 // enable vif clock
1164 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1165 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1166 // HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
1167 // HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
1168
1169 // enable DEMODE-DMA clock
1170 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1171 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1172 // HAL_DMD_RIU_WriteByte(0x111f21,0x00);
1173 // HAL_DMD_RIU_WriteByte(0x111f20,0x00);
1174
1175 // select clock
1176 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1177 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1178 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1179 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1180
1181
1182 // [15:12]: reg_ckg_dtmb_sram_dump
1183 // [0] : disable clock
1184 // [1] : invert clock
1185 // [3:2]: Select clock source
1186 // 00: dtmb_clk18_buf(16 MHz)
1187 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1188 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1189 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1190 HAL_DMD_RIU_WriteByte(0x111f71,0x18);
1191 HAL_DMD_RIU_WriteByte(0x111f70,0x81);
1192
1193 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1194 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1195
1196 HAL_DMD_RIU_WriteByte(0x111f4f,0x0c);
1197 HAL_DMD_RIU_WriteByte(0x111f4e,0x40);
1198
1199 HAL_DMD_RIU_WriteByte(0x111f51,0x48);
1200 HAL_DMD_RIU_WriteByte(0x111f50,0x44);
1201
1202 // Enable SAWLESS clock
1203 // reg_ckg_adcd_d2 @0x12[3:0]
1204 // reg_ckg_adcd_d4 @0x12[7:4]
1205 // reg_ckg_adcd_d6 @0x12[11:8]
1206 // reg_ckg_adcd_d12@0x12[15:12]
1207 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1208 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1209 // wriu 0x111f25 0x00
1210 // wriu 0x111f24 0x00
1211 // HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1212 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1213
1214 // ----------------------------------------------
1215 // start demod CLKGEN setting
1216 // ----------------------------------------------
1217
1218 // reg_allpad_in=0
1219 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1220 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1221 // HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1222 // HAL_DMD_RIU_WriteByte(0x101ea0,0x00);
1223
1224 // reg_ts1config=2
1225 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1226 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1227 //HAL_DMD_RIU_WriteByte(0x101eaf,0x10);
1228 //HAL_DMD_RIU_WriteByte(0x101eae,0x00);
1229
1230 // select DMD MCU
1231 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1232 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1233 // begin BY temp patch
1234 // HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1235 // HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1236 // end
1237 // HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1238
1239 // wriu 0x111f81 0x00
1240 // wriu 0x111f80 0x00
1241 // wriu 0x111f83 0x00
1242 // wriu 0x111f82 0x00
1243 // wriu 0x111f85 0x00
1244 // wriu 0x111f84 0x00
1245 // wriu 0x111f87 0x00
1246 // wriu 0x111f86 0x00
1247 // wriu 0x111f89 0x44
1248 // wriu 0x111f88 0x44
1249 // wriu 0x111f8b 0x00
1250 // wriu 0x111f8a 0x44
1251
1252 HAL_DMD_RIU_WriteByte(0x111f81,0x00);
1253 HAL_DMD_RIU_WriteByte(0x111f80,0x00);
1254
1255 HAL_DMD_RIU_WriteByte(0x111f83,0x00);
1256 HAL_DMD_RIU_WriteByte(0x111f82,0x00);
1257
1258 HAL_DMD_RIU_WriteByte(0x111f85,0x00);
1259 HAL_DMD_RIU_WriteByte(0x111f84,0x00);
1260
1261 HAL_DMD_RIU_WriteByte(0x111f87,0x00);
1262 HAL_DMD_RIU_WriteByte(0x111f86,0x00);
1263
1264 HAL_DMD_RIU_WriteByte(0x111f89,0x44);
1265 HAL_DMD_RIU_WriteByte(0x111f88,0x44);
1266
1267 HAL_DMD_RIU_WriteByte(0x111f8b,0x00);
1268 HAL_DMD_RIU_WriteByte(0x111f8a,0x44);
1269 // ----------------------------------------------
1270 // Turn TSP
1271 // ----------------------------------------------
1272 // turn on ts1_clk, ts0_clk
1273 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1274 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1275 // check TSP work or not
1276 //HAL_DMD_RIU_WriteByte(0x100b51,0x00);
1277 //HAL_DMD_RIU_WriteByte(0x100b50,0x00);
1278
1279 // stream2miu_en, activate rst_wadr
1280 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1281 // HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1282 // stream2miu_en, turn off rst_wadr
1283 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1284 // wriu 0x000e13 0x01
1285 //HAL_DMD_RIU_WriteByte(0x000e13,0x01);
1286 // udatatemp = HAL_DMD_RIU_ReadByte(0x000e13);
1287 // HAL_DMD_RIU_WriteByte(0x000e13, udatatemp&0xFB);//Set 0e12,Bit10=0,
1288 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1289 }
1290
1291 /***********************************************************************************
1292 Subject: Power on initialized function
1293 Function: INTERN_DVBT_Power_On_Initialization
1294 Parmeter:
1295 Return: MS_BOOL
1296 Remark:
1297 ************************************************************************************/
1298
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)1299 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
1300 {
1301 MS_U16 status = true;
1302 MS_U8 cData = 0;
1303 //U8 cal_done;
1304 DBG_INTERN_DVBT(printf("INTERN_DVBT_Power_On_Initialization\n"));
1305
1306 #if defined(PWS_ENABLE)
1307 Mapi_PWS_Stop_VDMCU();
1308 #endif
1309
1310 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
1311 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1312 //// Firmware download //////////
1313 DBG_INTERN_DVBT(printf("INTERN_DVBT Load DSP...\n"));
1314 //MsOS_DelayTask(100);
1315
1316 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1317 {
1318 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1319 {
1320 printf("DVB-T Load DSP Code Fail\n");
1321 return FALSE;
1322 }
1323 else
1324 {
1325 DBG_INTERN_DVBT(printf("DVB-T Load DSP Code OK\n"));
1326 }
1327 }
1328
1329
1330 //// MCU Reset //////////
1331 DBG_INTERN_DVBT(printf("INTERN_DVBT Reset...\n"));
1332 if (INTERN_DVBT_Reset() == FALSE)
1333 {
1334 DBG_INTERN_DVBT(printf("Fail\n"));
1335 return FALSE;
1336 }
1337 else
1338 {
1339 DBG_INTERN_DVBT(printf("OK\n"));
1340 }
1341
1342 // reset FDP
1343 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1344 // SRAM setting, DVB-T use it.
1345 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1346 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1347 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1348
1349 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1350 return status;
1351 }
1352
1353 /************************************************************************************************
1354 Subject: Driving control
1355 Function: INTERN_DVBT_Driving_Control
1356 Parmeter: bInversionEnable : TRUE For High
1357 Return: void
1358 Remark:
1359 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1360 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1361 {
1362 MS_U8 u8Temp;
1363
1364 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1365
1366 if (bEnable)
1367 {
1368 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1369 }
1370 else
1371 {
1372 u8Temp = u8Temp & (~0x01);
1373 }
1374
1375 DBG_INTERN_DVBT(printf("---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1376 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1377 }
1378 /************************************************************************************************
1379 Subject: Clk Inversion control
1380 Function: INTERN_DVBT_Clk_Inversion_Control
1381 Parmeter: bInversionEnable : TRUE For Inversion Action
1382 Return: void
1383 Remark:
1384 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1385 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1386 {
1387 MS_U8 u8Temp;
1388
1389 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1390
1391 if (bInversionEnable)
1392 {
1393 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1394 }
1395 else
1396 {
1397 u8Temp = u8Temp & (~0x02);
1398 }
1399
1400 DBG_INTERN_DVBT(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1401 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1402 }
1403 /************************************************************************************************
1404 Subject: Transport stream serial/parallel control
1405 Function: INTERN_DVBT_Serial_Control
1406 Parmeter: bEnable : TRUE For serial
1407 Return: MS_BOOL :
1408 Remark:
1409 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1410 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1411 {
1412 MS_U8 status = true;
1413 MS_U8 temp_val;
1414 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_ts... u8TSClk=%d\n",u8TSClk));
1415
1416 return status;
1417 if (u8TSClk == 0xFF) u8TSClk=0x13;
1418 if (bEnable) //Serial mode for TS pad
1419 {
1420 // serial
1421 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1422 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1423
1424 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1425 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1426 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1427
1428 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1429 temp_val|=0x04;
1430 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1431 #else
1432 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1433 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1434 temp_val|=0x07;
1435 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1436 #endif
1437 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1438 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1439
1440 //// INTERN_DVBT TS Control: Serial //////////
1441 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1442
1443 gsCmdPacket.param[0] = TS_SERIAL;
1444 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1445 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1446 #else
1447 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1448 #endif
1449 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1450 }
1451 else
1452 {
1453 //parallel
1454 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1455 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1456
1457 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1458 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1459 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1460 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1461 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1462 temp_val|=0x05;
1463 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1464 #else
1465 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1466 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1467 temp_val|=0x07;
1468 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1469 #endif
1470
1471 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1472 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1473
1474 //// INTERN_DVBT TS Control: Parallel //////////
1475 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1476
1477 gsCmdPacket.param[0] = TS_PARALLEL;
1478 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1479 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1480 #else
1481 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1482 #endif
1483 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1484 }
1485
1486 DBG_INTERN_DVBT(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1487
1488 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1489 return status;
1490 }
1491
1492 /************************************************************************************************
1493 Subject: TS1 output control
1494 Function: INTERN_DVBT_PAD_TS1_Enable
1495 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1496 Return: void
1497 Remark:
1498 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1499 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1500 {
1501 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_TS1_Enable... \n"));
1502
1503 if(flag) // PAD_TS1 Enable TS CLK PAD
1504 {
1505 //printf("=== TS1_Enable ===\n");
1506 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1507 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1508 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1509 }
1510 else // PAD_TS1 Disable TS CLK PAD
1511 {
1512 //printf("=== TS1_Disable ===\n");
1513 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1514 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1515 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1516 }
1517 }
1518
1519 /************************************************************************************************
1520 Subject: channel change config
1521 Function: INTERN_DVBT_Config
1522 Parmeter: BW: bandwidth
1523 Return: MS_BOOL :
1524 Remark:
1525 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1526 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1527 {
1528 MS_U8 bandwidth;
1529 MS_U8 status = true;
1530
1531 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_config %d %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap));
1532 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime()));
1533
1534 if (u8TSClk == 0xFF) u8TSClk=0x13;
1535 switch(BW)
1536 {
1537 case E_DMD_RF_CH_BAND_6MHz:
1538 bandwidth = 1;
1539 break;
1540 case E_DMD_RF_CH_BAND_7MHz:
1541 bandwidth = 2;
1542 break;
1543 case E_DMD_RF_CH_BAND_8MHz:
1544 default:
1545 bandwidth = 3;
1546 break;
1547 }
1548
1549 status &= INTERN_DVBT_Reset();
1550
1551 // BW mode
1552 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1553 // TS mode
1554 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1555 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1557 // Hierarchy mode
1558 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1559 // FC
1560 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1561 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1562 // FS
1563 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1564 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1565 // IQSwap
1566 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1567
1568 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1569 // Fif
1570 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1571 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1572
1573 return status;
1574 }
1575 /************************************************************************************************
1576 Subject: enable hw to lock channel
1577 Function: INTERN_DVBT_Active
1578 Parmeter: bEnable
1579 Return: MS_BOOL
1580 Remark:
1581 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1582 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1583 {
1584 MS_U8 status = true;
1585
1586 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_active\n"));
1587
1588 //// INTERN_DVBT Finite State Machine on/off //////////
1589 #if 0
1590 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1591
1592 gsCmdPacket.param[0] = (MS_U8)bEnable;
1593 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1594 #else
1595 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1596 #endif
1597
1598 /*bryan temp mark*/
1599 #if(0)
1600 INTERN_DVBT_SignalQualityReset();
1601 #endif
1602
1603 return status;
1604 }
1605 /************************************************************************************************
1606 Subject: Return lock status
1607 Function: INTERN_DVBT_Lock
1608 Parmeter: eStatus :
1609 Return: MS_BOOL
1610 Remark:
1611 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1612 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1613 {
1614 /*bryan temp mark*/
1615 //float fBER=0.0f;
1616
1617
1618 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1619 {
1620 if (bFECLock == FALSE)
1621 {
1622 u32FecFirstLockTime = MsOS_GetSystemTime();
1623 DBG_INTERN_DVBT(printf("++++++++[utopia]dvbt lock\n"));
1624 }
1625 /*bryan temp mark*/
1626 /*
1627 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1628 {
1629 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1630 {
1631 if(fViterbiBerFiltered <= 0.0)
1632 fViterbiBerFiltered = fBER;
1633 else
1634 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1635 }
1636 DBG_INTERN_DVBT(printf("[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered));
1637 }
1638 */
1639 u32FecLastLockTime = MsOS_GetSystemTime();
1640 bFECLock = TRUE;
1641 return E_DMD_LOCK;
1642 }
1643 else
1644 {
1645 /*bryam temp mark*/
1646 #if(0)
1647 INTERN_DVBT_SignalQualityReset();
1648 #endif
1649
1650 if (bFECLock == TRUE)
1651 {
1652 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1653 {
1654 return E_DMD_LOCK;
1655 }
1656 }
1657 bFECLock = FALSE;
1658 }
1659
1660 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1661 {
1662 printf("==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1663 return E_DMD_UNLOCK;
1664 }
1665
1666 if(!bTPSLock)
1667 {
1668 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1669 {
1670 DBG_INTERN_DVBT(printf("==> INTERN_DVBT_Lock -- TPSLock \n"););
1671 bTPSLock = TRUE;
1672 }
1673 }
1674 if(bTPSLock)
1675 {
1676 DBG_INTERN_DVBT(printf("TPSLock %ld\n",MsOS_GetSystemTime()));
1677 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1678 {
1679 return E_DMD_CHECKING;
1680 }
1681 }
1682 else
1683 {
1684 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1685 {
1686 return E_DMD_CHECKING;
1687 }
1688 }
1689 return E_DMD_UNLOCK;
1690
1691 }
1692
1693
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1694 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1695 {
1696 MS_U16 u16Address = 0;
1697 MS_U8 cData = 0;
1698 MS_U8 cBitMask = 0;
1699
1700 switch( eStatus )
1701 {
1702 case E_DMD_COFDM_FEC_LOCK:
1703 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1704
1705 if (cData == 0x0B)
1706 {
1707 return TRUE;
1708 }
1709 else
1710 {
1711 return FALSE; // continuously un-lock
1712 }
1713 break;
1714
1715 case E_DMD_COFDM_PSYNC_LOCK:
1716 u16Address = 0x232C; //FEC: P-sync Lock,
1717 cBitMask = BIT(1);
1718 break;
1719
1720 case E_DMD_COFDM_TPS_LOCK:
1721 u16Address = 0x2222; //TPS HW Lock,
1722 cBitMask = BIT(1);
1723 break;
1724
1725 case E_DMD_COFDM_DCR_LOCK:
1726 u16Address = 0x2737; //DCR Lock,
1727 cBitMask = BIT(0);
1728 break;
1729
1730 case E_DMD_COFDM_AGC_LOCK:
1731 u16Address = 0x271D; //AGC Lock,
1732 cBitMask = BIT(0);
1733 break;
1734
1735 case E_DMD_COFDM_MODE_DET:
1736 u16Address = 0x24CF; //Mode CP Detect,
1737 cBitMask = BIT(4);
1738 break;
1739
1740 case E_DMD_COFDM_TPS_EVER_LOCK:
1741 u16Address = 0x20C0; //TPS Ever Lock,
1742 cBitMask = BIT(3);
1743 break;
1744
1745 case E_DMD_COFDM_NO_CHANNEL:
1746 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1747 cBitMask = BIT(7);
1748 break;
1749
1750 default:
1751 return FALSE;
1752 }
1753
1754 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1755 return FALSE;
1756
1757 if ((cData & cBitMask) == cBitMask)
1758 {
1759 return TRUE;
1760 }
1761
1762 return FALSE;
1763
1764 }
1765
1766 /****************************************************************************
1767 Subject: To get the Post viterbi BER
1768 Function: INTERN_DVBT_GetPostViterbiBer
1769 Parmeter: Quility
1770 Return: E_RESULT_SUCCESS
1771 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1772 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1773 We will not read the Period, and have the "/256/8"
1774 *****************************************************************************/
1775 /*bryan temp mark*/
1776 #if(0)
INTERN_DVBT_GetPostViterbiBer(float * ber)1777 MS_BOOL INTERN_DVBT_GetPostViterbiBer(float *ber)
1778 {
1779 MS_BOOL status = true;
1780 MS_U8 reg=0, reg_frz=0;
1781 MS_U16 BitErrPeriod;
1782 MS_U32 BitErr;
1783 MS_U16 PktErr;
1784
1785 /////////// Post-Viterbi BER /////////////
1786
1787 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1788 {
1789 *ber = (float)-1.0;
1790 return false;
1791 }
1792 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1793 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1794 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1795
1796 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1797 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1799 BitErrPeriod = reg;
1800
1801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1802 BitErrPeriod = (BitErrPeriod << 8)|reg;
1803
1804 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1805 // 0x6b [15:8] reg_bit_err_num_15_8
1806 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1807 // 0x6d [15:8] reg_bit_err_num_31_24
1808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1809 BitErr = reg;
1810
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1812 BitErr = (BitErr << 8)|reg;
1813
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1815 BitErr = (BitErr << 8)|reg;
1816
1817 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1818 BitErr = (BitErr << 8)|reg;
1819
1820 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1821 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1823 PktErr = reg;
1824
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1826 PktErr = (PktErr << 8)|reg;
1827
1828 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1829 reg_frz=reg_frz&(~0x03);
1830 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1831
1832 if (BitErrPeriod == 0 ) //protect 0
1833 BitErrPeriod = 1;
1834
1835 if (BitErr <=0 )
1836 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1837 else
1838 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1839
1840
1841 DBG_GET_SIGNAL(printf("INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1842 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1843
1844 return status;
1845 }
1846
1847 /****************************************************************************
1848 Subject: To get the Pre viterbi BER
1849 Function: INTERN_DVBT_GetPreViterbiBer
1850 Parmeter: ber
1851 Return: E_RESULT_SUCCESS
1852 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1853 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1854 We will not read the Period, and have the "/256/8"
1855 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1856 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1857 {
1858 MS_U8 status = true;
1859 MS_U8 reg=0, reg_frz=0;
1860 MS_U16 BitErrPeriod;
1861 MS_U32 BitErr;
1862 MS_BOOL BEROver;
1863
1864 // bank 7 0x10 [3] reg_rd_freezeber
1865 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1866 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1867
1868 // bank 7 0x16 [7:0] reg_ber_timerl
1869 // [15:8] reg_ber_timerm
1870 // bank 7 0x18 [5:0] reg_ber_timerh
1871 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1872 BitErrPeriod = reg&0x3f;
1873
1874 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1875 BitErrPeriod = (BitErrPeriod << 8)|reg;
1876
1877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1878 BitErrPeriod = (BitErrPeriod << 8)|reg;
1879
1880 // bank 7 0x1e [7:0] reg_ber_7_0
1881 // [15:8] reg_ber_15_8
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1883 BitErr = reg;
1884
1885 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1886 BitErr = (BitErr << 8)|reg;
1887
1888 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1889 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1890 if (reg & 0x10)
1891 BEROver = true;
1892 else
1893 BEROver = false;
1894
1895 if (BitErrPeriod ==0 )//protect 0
1896 BitErrPeriod=1;
1897
1898 if (BEROver)
1899 {
1900 *ber = 1;
1901 printf("BER is over\n");
1902 }
1903 else
1904 {
1905 if (BitErr <=0 )
1906 *ber=0.5 / (float)(BitErrPeriod * 256);
1907 else
1908 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1909 }
1910
1911 // bank 7 0x10 [3] reg_rd_freezeber
1912 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1913
1914 return status;
1915 }
1916 #endif
1917
1918 /****************************************************************************
1919 Subject: To get the Packet error
1920 Function: INTERN_DVBT_GetPacketErr
1921 Parmeter: pktErr
1922 Return: E_RESULT_SUCCESS
1923 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1924 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1925 We will not read the Period, and have the "/256/8"
1926 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1927 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1928 {
1929 MS_BOOL status = true;
1930 MS_U8 reg = 0, reg_frz = 0;
1931 MS_U16 PktErr;
1932
1933 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1934 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1935 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1936
1937 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1938 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1940 PktErr = reg;
1941
1942 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1943 PktErr = (PktErr << 8)|reg;
1944
1945 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1946 reg_frz=reg_frz&(~0x03);
1947 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1948
1949 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1950
1951 *u16PktErr = PktErr;
1952
1953 return status;
1954 }
1955
1956 /****************************************************************************
1957 Subject: To get the DVBT parameter
1958 Function: INTERN_DVBT_Get_TPS_Info
1959 Parmeter: point to return parameter
1960 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1961 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1962 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1963 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1964 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1965 FFT ( b14) : 0~1 => 2K, 8K
1966 Priority(bit 15) : 0~1=> HP,LP
1967 Return: TRUE
1968 FALSE
1969 Remark: The TPS parameters will be available after TPS lock
1970 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1971 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1972 {
1973 MS_U8 u8Temp;
1974
1975 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1976 return FALSE;
1977
1978 if ((u8Temp& 0x02) != 0x02)
1979 {
1980 return FALSE; //TPS unlock
1981 }
1982 else
1983 {
1984 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1985 return FALSE;
1986
1987 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1988 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1989
1990 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1991 return FALSE;
1992
1993 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1994 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1995
1996 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1997 return FALSE;
1998
1999 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
2000 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
2001
2002 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
2003 return FALSE;
2004
2005 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
2006
2007 }
2008 return TRUE;
2009 }
2010
2011
2012 /****************************************************************************
2013 Subject: Read the signal to noise ratio (SNR)
2014 Function: INTERN_DVBT_GetSNR
2015 Parmeter: None
2016 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2017 Remark:
2018 *****************************************************************************/
2019 #if(0)
INTERN_DVBT_GetSNR(void)2020 float INTERN_DVBT_GetSNR (void)
2021 {
2022 MS_U8 status = true;
2023 MS_U8 reg=0, reg_frz=0;
2024 MS_U32 noise_power;
2025 float snr;
2026
2027 // bank 6 0xfe [0] reg_fdp_freeze
2028 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2029 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2030
2031 // bank 6 0xff [0] reg_fdp_load
2032 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2033
2034 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
2035 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
2036 noise_power = reg & 0x07;
2037
2038 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
2039 noise_power = (noise_power << 8)|reg;
2040
2041 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
2042 noise_power = (noise_power << 8)|reg;
2043
2044 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
2045 noise_power = (noise_power << 8)|reg;
2046
2047 // bank 6 0x26 [5:4] reg_transmission_mode
2048 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2049
2050 // bank 6 0xfe [0] reg_fdp_freeze
2051 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
2052
2053 // bank 6 0xff [0] reg_fdp_load
2054 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2055
2056 #if 1 // copy from utopia2\mxlib\hal\miami\demod\halDMD_INTERN_DVBT.c
2057 noise_power = noise_power/2;
2058 noise_power /=1280;
2059 // noisepower = (rand()%256)*256;
2060 if (noise_power==0)//protect value 0
2061 noise_power=1;
2062
2063 #ifdef MSOS_TYPE_LINUX
2064 snr = 10*log10f((float)noise_power);
2065 #else
2066 snr = 10*Log10Approx((float)noise_power);
2067 #endif
2068
2069
2070 #else
2071 noise_power = noise_power/2;
2072
2073 if ((reg&0x30)==0x00) //2K
2074 {
2075 if (noise_power<1512)
2076 snr = 0;
2077 else
2078 #ifdef MSOS_TYPE_LINUX
2079 snr = 10*log10f((float)noise_power/1512);
2080 #else
2081 snr = 10*Log10Approx((float)noise_power/1512);
2082 #endif
2083 }
2084 //else if ((reg&0x30)==0x10)//8K
2085 else
2086 {
2087 if (noise_power<6048)
2088 snr = 0;
2089 else
2090 #ifdef MSOS_TYPE_LINUX
2091 snr = 10*log10f((float)noise_power/6048);
2092 #else
2093 snr = 10*Log10Approx((float)noise_power/6048);
2094 #endif
2095 }
2096 /* ignore 4K
2097 else //4K
2098 {
2099 if (noise_power<3024)
2100 snr = 0;
2101 else
2102 snr = 10*Log10Approx(noise_power/3024);
2103 }
2104 */
2105 #endif
2106
2107 if (status == true)
2108 return snr;
2109 else
2110 return -1;
2111
2112 }
2113 #endif
2114 /****************************************************************************
2115 Subject: To check if Hierarchy on
2116 Function: INTERN_DVBT_Is_HierarchyOn
2117 Parmeter:
2118 Return: BOOLEAN
2119 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)2120 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
2121 {
2122 MS_U16 u16_tmp;
2123
2124 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
2125 return FALSE;
2126 //printf("u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
2127 if(u16_tmp&0x38)
2128 {
2129 return TRUE;
2130 }
2131 return FALSE;
2132 }
2133
2134 /*bryan temp mark*/
2135 #if(0)
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2136 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2137 {
2138 MS_U8 status = true;
2139 float ch_power_db = 0.0f;
2140 float ch_power_ref = 11.0f;
2141 float ch_power_rel = 0.0f;
2142 MS_U8 u8_index = 0;
2143 MS_U16 tps_info_qam,tps_info_cr;
2144
2145 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2146 {
2147 *strength = 0;
2148 return TRUE;
2149 }
2150 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2151
2152 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
2153 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
2154 /* Actually, it's more reasonable, that signal level depended on cable input power level
2155 * thougth the signal isn't dvb-t signal.
2156 */
2157
2158 // use pointer of IFAGC table to identify
2159 // case 1: RFAGC from SAR, IFAGC controlled by demod
2160 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2161 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2162 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
2163 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2164 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2165 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
2166 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
2167
2168
2169 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
2170 printf("[dvbt]TPS qam parameter retrieve failure\n");
2171
2172 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
2173 printf("[dvbt]TPS cr parameter retrieve failure\n");
2174
2175
2176 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2177 {
2178 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
2179 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
2180 {
2181 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2182 break;
2183 }
2184 else
2185 {
2186 u8_index++;
2187 }
2188 }
2189
2190 if (ch_power_ref > 10.0f)
2191 *strength = 0;
2192 else
2193 {
2194 ch_power_rel = ch_power_db - ch_power_ref;
2195
2196 if ( ch_power_rel < -15.0f )
2197 {
2198 *strength = 0;
2199 }
2200 else if ( ch_power_rel < 0.0f )
2201 {
2202 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2203 }
2204 else if ( ch_power_rel < 20 )
2205 {
2206 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2207 }
2208 else if ( ch_power_rel < 35.0f )
2209 {
2210 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2211 }
2212 else
2213 {
2214 *strength = 100;
2215 }
2216 }
2217
2218 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2219 {
2220 *strength = 0;
2221 return TRUE;
2222 }
2223
2224 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2225 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2226
2227 return status;
2228 }
2229
2230
2231 /****************************************************************************
2232 Subject: To get the DVT Signal quility
2233 Function: INTERN_DVBT_GetSignalQuality
2234 Parmeter: Quility
2235 Return: E_RESULT_SUCCESS
2236 E_RESULT_FAILURE
2237 Remark: Here we have 4 level range
2238 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2239 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2240 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2241 <4>.4th Range => Quality <10
2242 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2243 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2244 {
2245 float ber_sqi;
2246 float fber;
2247 float cn_rec = 0;
2248 float cn_nordig_p1 = 0;
2249 float cn_rel = 0;
2250
2251 MS_U8 status = true;
2252 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
2253 MS_U16 u16_tmp;
2254
2255 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2256
2257 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
2258 {
2259
2260 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2261 {
2262 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2263 }
2264 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
2265 if(fViterbiBerFiltered<= 0.0)
2266 {
2267 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
2268 {
2269 DBG_INTERN_DVBT(printf("GetPostViterbiBer Fail!\n"));
2270 return FALSE;
2271 }
2272 fViterbiBerFiltered = fber;
2273 }
2274 else
2275 {
2276 fber = fViterbiBerFiltered;
2277 }
2278
2279 if (fber > 1.0E-3)
2280 ber_sqi = 0.0;
2281 else if (fber > 8.5E-7)
2282 #ifdef MSOS_TYPE_LINUX
2283 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2284 #else
2285 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2286 #endif
2287 else
2288 ber_sqi = 100.0;
2289
2290 cn_rec = INTERN_DVBT_GetSNR();
2291
2292 if (cn_rec == -1) //get SNR return fail
2293 status = false;
2294
2295 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2296 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2297 tps_cnstl = 0xff;
2298 tps_cr = 0xff;
2299 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
2300 tps_cnstl = (MS_U8)u16_tmp&0x07;
2301 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
2302 tps_cr = (MS_U8)u16_tmp&0x07;
2303
2304 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
2305 {
2306 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
2307 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
2308 {
2309 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
2310 break;
2311 }
2312 }
2313
2314 // 0,5, snr offset
2315 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
2316
2317 // patch....
2318 // Noridg SQI,
2319 // 64QAM, CR34, GI14, SNR 22dB.
2320 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
2321 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
2322 {
2323 cn_rel += 1.5f;
2324 }
2325
2326 if (cn_rel < -7.0f)
2327 {
2328 *quality = 0;
2329 }
2330 else if (cn_rel < 3.0)
2331 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
2332 else
2333 *quality = (MS_U16)ber_sqi;
2334 }
2335 else
2336 {
2337 *quality = 0;
2338 }
2339
2340 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2341 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2342 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2343 return status;
2344 }
2345 #endif
2346
2347 /****************************************************************************
2348 Subject: To get the Cell ID
2349 Function: INTERN_DVBT_Get_CELL_ID
2350 Parmeter: point to return parameter cell_id
2351
2352 Return: TRUE
2353 FALSE
2354 Remark:
2355 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2356 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2357 {
2358 MS_U8 status = true;
2359 MS_U8 value1=0;
2360 MS_U8 value2=0;
2361
2362 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2363 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2364
2365 *cell_id = ((MS_U16)value1<<8)|value2;
2366 return status;
2367 }
2368 /*
2369 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2370 {
2371 #define SQI_LOOP_NUM 50
2372 U8 inn = 0;
2373 WORD sqi = 0;
2374 WORD ave_sqi = 0;
2375 WORD ave_num = 0;
2376 while(inn++<SQI_LOOP_NUM)
2377 {
2378 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2379 {
2380 printf("[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2381 ave_sqi+=sqi;
2382 ave_num++;
2383 }
2384 MsOS_DelayTask(50);
2385 }
2386
2387 if(ave_num != 0 )
2388 *quality = ave_sqi/ave_num;
2389
2390 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2391 }
2392 */
2393 /****************************************************************************
2394 Subject: To get the DVBT Carrier Freq Offset
2395 Function: INTERN_DVBT_Get_FreqOffset
2396 Parmeter: Frequency offset (in KHz), bandwidth
2397 Return: E_RESULT_SUCCESS
2398 E_RESULT_FAILURE
2399 Remark:
2400 *****************************************************************************/
2401 /*bryan temp mark*/
2402 #if(0)
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2403 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2404 {
2405 float N, FreqB;
2406 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2407 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2408 MS_U8 reg_frz=0, reg=0;
2409 MS_U8 status;
2410
2411 FreqB = (float)u8BW * 8 / 7;
2412
2413 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2414
2415 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2416
2417 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2418 RegCfoTd = reg;
2419
2420 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2421 RegCfoTd = (RegCfoTd << 8)|reg;
2422
2423 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2424 RegCfoTd = (RegCfoTd << 8)|reg;
2425
2426 FreqCfoTd = (float)RegCfoTd;
2427
2428 if (RegCfoTd & 0x800000)
2429 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2430
2431 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2432
2433 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2434
2435 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2436 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2437
2438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2439
2440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2441 RegCfoFd = reg;
2442
2443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2444 RegCfoFd = (RegCfoFd << 8)|reg;
2445
2446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2447 RegCfoFd = (RegCfoFd << 8)|reg;
2448
2449 FreqCfoFd = (float)RegCfoFd;
2450
2451 if (RegCfoFd & 0x800000)
2452 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2453
2454 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2455
2456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2457 RegIcfo = reg & 0x07;
2458
2459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2460 RegIcfo = (RegIcfo << 8)|reg;
2461
2462 FreqIcfo = (float)RegIcfo;
2463
2464 if (RegIcfo & 0x400)
2465 FreqIcfo = FreqIcfo - (float)0x800;
2466
2467 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2468 reg = reg & 0x30;
2469
2470 switch (reg)
2471 {
2472 case 0x00: N = 2048; break;
2473 case 0x20: N = 4096; break;
2474 case 0x10:
2475 default: N = 8192; break;
2476 }
2477
2478 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2479 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2480 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2481 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2482 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2483 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2484 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2485 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2486 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2487 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2488
2489 if (status == TRUE)
2490 return TRUE;
2491 else
2492 return FALSE;
2493 }
2494 #endif
2495
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2496 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2497 {
2498
2499 bPowerOn = bPowerOn;
2500 }
2501
INTERN_DVBT_Power_Save(void)2502 MS_BOOL INTERN_DVBT_Power_Save(void)
2503 {
2504
2505 return TRUE;
2506 }
2507
2508 /****************************************************************************
2509 Subject: To get the DVBT constellation parameter
2510 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2511 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2512 Return: TRUE
2513 FALSE
2514 Remark: The TPS parameters will be available after TPS lock
2515 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2516 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2517 {
2518 MS_U8 tps_param;
2519
2520 //@@++ Arki 20100125
2521 if (eSignalType == TS_MODUL_MODE)
2522 {
2523 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2524 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2525 }
2526
2527 if (eSignalType == TS_CODE_RATE)
2528 {
2529 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2530 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2531 }
2532
2533 if (eSignalType == TS_GUARD_INTERVAL)
2534 {
2535 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2536 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2537 }
2538
2539 if (eSignalType == TS_FFX_VALUE)
2540 {
2541 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2542 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2543 }
2544 //@@-- Arki 20100125
2545 return TRUE;
2546 }
2547
INTERN_DVBT_Version(MS_U16 * ver)2548 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2549 {
2550
2551 MS_U8 status = true;
2552 MS_U8 tmp = 0;
2553 MS_U16 u16_INTERN_DVBT_Version;
2554
2555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2556 u16_INTERN_DVBT_Version = tmp;
2557 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2558 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2559 *ver = u16_INTERN_DVBT_Version;
2560
2561 return status;
2562 }
2563
INTERN_DVBT_Version_minor(MS_U8 * ver2)2564 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2565 {
2566
2567 MS_U8 status = true;
2568
2569 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2570
2571 return status;
2572 }
2573
2574
INTERN_DVBT_Show_Demod_Version(void)2575 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2576 {
2577
2578 MS_BOOL status = true;
2579 MS_U16 u16_INTERN_DVBT_Version;
2580 MS_U8 u8_minor_ver = 0;
2581
2582 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2583 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2584 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2585
2586 return status;
2587 }
2588
2589 /*bryan temp mark*/
2590 #if(0)
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2591 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2592 {
2593 MS_U8 u8_index = 0;
2594 MS_BOOL bRet = false;
2595
2596 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2597 {
2598 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2599 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2600 {
2601 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2602 bRet = true;
2603 break;
2604 }
2605 else
2606 {
2607 u8_index++;
2608 }
2609 }
2610 return bRet;
2611 }
2612
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2613 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2614 {
2615 MS_U8 u8_index = 0;
2616 MS_BOOL bRet = false;
2617
2618 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2619 {
2620 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2621 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2622 {
2623 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2624 bRet = true;
2625 break;
2626 }
2627 else
2628 {
2629 u8_index++;
2630 }
2631 }
2632 return bRet;
2633 }
2634 #endif
2635
2636 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2637 void INTERN_DVBT_get_demod_state(MS_U8* state)
2638 {
2639 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2640 return;
2641 }
2642
INTERN_DVBT_Show_ChannelLength(void)2643 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2644 {
2645 MS_U8 status = true;
2646 MS_U8 tmp = 0;
2647 MS_U16 len = 0;
2648 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2649 len = tmp;
2650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2651 len = (len<<8)|tmp;
2652 printf("[dvbt]Hw_channel=%d\n",len);
2653 return status;
2654 }
2655
INTERN_DVBT_Show_SW_ChannelLength(void)2656 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2657 {
2658 MS_U8 status = true;
2659 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2660 MS_U16 sw_len = 0;
2661 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2662 sw_len = tmp;
2663 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2664 sw_len = (sw_len<<8)|tmp;
2665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2666 peak_num = tmp;
2667 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2668 insideGI = tmp&0x01;
2669 stoptracking = (tmp&0x02)>>1;
2670 flag_short_echo = (tmp&0x0C)>>2;
2671 fsa_mode = (tmp&0x30)>>4;
2672
2673 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2674 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2675
2676 return status;
2677 }
2678
INTERN_DVBT_Show_ACI_CI(void)2679 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2680 {
2681
2682 #define BIT4 0x10
2683 MS_U8 status = true;
2684 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2685
2686 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2687 digACI = (tmp&BIT4)>>4;
2688
2689 // get flag_CI
2690 // 0: No interference
2691 // 1: CCI
2692 // 2: in-band ACI
2693 // 3: N+1 ACI
2694 // flag_ci = (tmp&0xc0)>>6;
2695 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2696 flag_CI = (tmp&0xC0)>>6;
2697 td_coef = (tmp&0x0C)>>2;
2698
2699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2700
2701 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2702
2703 return status;
2704 }
2705
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2706 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2707 {
2708 MS_U8 status = true;
2709 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2710 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2711 fd = tmp;
2712 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2713 ch_len = tmp;
2714 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2715 snr_sel = (tmp>>4)&0x03;
2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2717 pertone_num = tmp;
2718
2719 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2720
2721 return status;
2722 }
2723
INTERN_DVBT_Get_CFO(void)2724 MS_BOOL INTERN_DVBT_Get_CFO(void)
2725 {
2726
2727 float N = 0, FreqB = 0;
2728 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2729 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2730 MS_U8 reg_frz = 0, reg = 0;
2731 MS_U8 status = 0;
2732 MS_U8 u8BW = 8;
2733
2734 FreqB = (float)u8BW * 8 / 7;
2735
2736 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2737
2738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2739
2740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2741 RegCfoTd = reg;
2742
2743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2744 RegCfoTd = (RegCfoTd << 8)|reg;
2745
2746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2747 RegCfoTd = (RegCfoTd << 8)|reg;
2748
2749 FreqCfoTd = (float)RegCfoTd;
2750
2751 if (RegCfoTd & 0x800000)
2752 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2753
2754 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2755
2756 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2757
2758 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2759 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2760
2761 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2762
2763 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2764 RegCfoFd = reg;
2765
2766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2767 RegCfoFd = (RegCfoFd << 8)|reg;
2768
2769 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2770 RegCfoFd = (RegCfoFd << 8)|reg;
2771
2772 FreqCfoFd = (float)RegCfoFd;
2773
2774 if (RegCfoFd & 0x800000)
2775 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2776
2777 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2778
2779 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2780 RegIcfo = reg & 0x07;
2781
2782 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2783 RegIcfo = (RegIcfo << 8)|reg;
2784
2785 FreqIcfo = (float)RegIcfo;
2786
2787 if (RegIcfo & 0x400)
2788 FreqIcfo = FreqIcfo - (float)0x800;
2789
2790 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2791 reg = reg & 0x30;
2792
2793 switch (reg)
2794 {
2795 case 0x00: N = 2048; break;
2796 case 0x20: N = 4096; break;
2797 case 0x10:
2798 default: N = 8192; break;
2799 }
2800
2801 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2802 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2803 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2804 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2805 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2806
2807 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2808
2809 return status;
2810
2811 }
INTERN_DVBT_Get_SFO(void)2812 MS_BOOL INTERN_DVBT_Get_SFO(void)
2813 {
2814 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2815 MS_BOOL status = true;
2816 MS_U8 reg = 0;
2817 float FreqB = 9.143, FreqS = 45.473; //20.48
2818 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2819 float sfo_value = 0;
2820
2821 // get Reg_TDP_SFO,
2822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2823 Reg_TDP_SFO = reg;
2824 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2825 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2826 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2827 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2828
2829 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2830
2831 // get Reg_FDP_SFO,
2832 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2833 Reg_FDP_SFO = reg;
2834 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2835 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2836 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2837 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2838
2839 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2840
2841 // get Reg_FSA_SFO,
2842 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2843 Reg_FSA_SFO = reg;
2844 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2845 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2846 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2847 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2848
2849 // get Reg_FSA_IN,
2850 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2851 Reg_FSA_IN = reg;
2852 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2853 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2854 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2855
2856 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2857 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2858
2859 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2860 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2861 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2862
2863
2864 return status;
2865 }
2866
INTERN_DVBT_Get_SYA_status(void)2867 void INTERN_DVBT_Get_SYA_status(void)
2868 {
2869 MS_U8 status = true;
2870 MS_U8 sya_k = 0,reg = 0;
2871 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2872
2873 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2874 sya_k = reg;
2875
2876 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2877 sya_th = reg;
2878 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2879 sya_th = (sya_th<<8)|reg;
2880
2881 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2882 sya_offset = reg;
2883 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2884 sya_offset = (sya_offset<<8)|reg;
2885
2886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2887 len_m = reg;
2888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2889 len_m = (len_m<<8)|reg;
2890
2891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2892 len_b = reg;
2893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2894 len_b = (len_b<<8)|reg;
2895
2896
2897 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2898 len_a = reg;
2899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2900 len_a = (len_a<<8)|reg;
2901
2902
2903 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2904 tracking_reg = reg;
2905
2906
2907 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2908 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2909
2910 return;
2911 }
2912
INTERN_DVBT_Get_cci_status(void)2913 void INTERN_DVBT_Get_cci_status(void)
2914 {
2915 MS_U8 status = true;
2916 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2917
2918 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2919 cci_fsweep = reg;
2920
2921 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2922 cci_kp = reg;
2923
2924 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2925
2926 return;
2927 }
2928
INTERN_DVBT_Show_PRESFO_Info(void)2929 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2930 {
2931 MS_U8 tmp = 0;
2932 MS_BOOL status = TRUE;
2933 printf("\n[SFO]");
2934 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2935 printf("[%x]",tmp);
2936 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2937 printf("[%x]",tmp);
2938 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2939 printf("[%x]",tmp);
2940 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2941 printf("[%x]",tmp);
2942 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2943 printf("[%x]",tmp);
2944 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2945 printf("[%x]",tmp);
2946 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2947 printf("[%x]",tmp);
2948 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2949 printf("[%x][End]",tmp);
2950
2951 return status;
2952 }
2953
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2954 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2955 {
2956 MS_BOOL status = true;
2957
2958 *locktime = 0xffff;
2959 printf("[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2960
2961 status = false;
2962 return status;
2963 }
2964
2965
INTERN_DVBT_Show_Lock_Time_Info(void)2966 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2967 {
2968 MS_U16 locktime = 0;
2969 MS_BOOL status = TRUE;
2970 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2971 printf("[DVBT]lock_time = %d ms\n",locktime);
2972 return status;
2973 }
2974
INTERN_DVBT_Show_BER_Info(void)2975 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2976 {
2977 MS_U8 tmp = 0;
2978 MS_BOOL status = TRUE;
2979 printf("\n[BER]");
2980 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2981 printf("[%x,",tmp);
2982 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2983 printf("%x]",tmp);
2984 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2985 printf("[%x,",tmp);
2986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2987 printf("%x]",tmp);
2988 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2989 printf("[%x,",tmp);
2990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2991 printf("%x][End]",tmp);
2992
2993 return status;
2994
2995 }
2996
2997
INTERN_DVBT_Show_AGC_Info(void)2998 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2999 {
3000 MS_U8 tmp = 0;
3001 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
3002 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
3003 MS_U16 if_agc_err = 0;
3004 MS_BOOL status = TRUE;
3005 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
3006
3007 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
3008 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
3009 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
3010 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
3011 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
3012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
3013
3014
3015 // select IF gain to read
3016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3017 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
3018
3019 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3020 if_agc_gain = tmp;
3021 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3022 if_agc_gain = (if_agc_gain<<8)|tmp;
3023
3024
3025 // select d1 gain to read.
3026 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3027 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3028
3029 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3030 d1_gain = tmp;
3031 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3032 d1_gain = (d1_gain<<8)|tmp;
3033
3034 // select d2 gain to read.
3035 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3036 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3037
3038 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3039 d2_gain = tmp;
3040 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3041 d2_gain = (d2_gain<<8)|tmp;
3042
3043 // select IF gain err to read
3044 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3045 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3046
3047 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3048 if_agc_err = tmp;
3049 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3050 if_agc_err = (if_agc_err<<8)|tmp;
3051
3052 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3053 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3054 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3055
3056
3057
3058 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3059 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3060
3061 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3062 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3063
3064 return status;
3065
3066 }
3067
INTERN_DVBT_Show_WIN_Info(void)3068 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
3069 {
3070 MS_U8 tmp = 0;
3071 MS_U8 trigger = 0;
3072 MS_U16 win_len = 0;
3073
3074 MS_BOOL status = TRUE;
3075
3076 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3077 win_len = tmp;
3078 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3079 win_len = (win_len<<8)|tmp;
3080
3081 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3082
3083 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3084
3085 return status;
3086 }
3087
INTERN_DVBT_Show_td_coeff(void)3088 void INTERN_DVBT_Show_td_coeff(void)
3089 {
3090 MS_U8 status = true;
3091 MS_U8 w1 = 0,w2 = 0,reg = 0;
3092
3093 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3094 w1 = reg;
3095
3096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3097 w2 = reg;
3098
3099 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
3100
3101 return;
3102 }
3103
3104 /********************************************************
3105 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
3106 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
3107 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3108 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3109 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
3110 * FFT ( b14) : 0~1 => 2K, 8K
3111 ********************************/
INTERN_DVBT_Show_Modulation_info(void)3112 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
3113 {
3114 MS_U16 tps_info;
3115
3116 // printf("[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
3117
3118 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
3119 {
3120 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
3121 MS_U8 constel = tps_info&0x0007;
3122 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
3123 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
3124 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
3125 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
3126
3127 printf("tps=0x%x ",tps_info);
3128
3129 switch(fft)
3130 {
3131 case 0:
3132 printf("mode = 2K,");
3133 break;
3134 case 1:
3135 printf("mode = 8K,");
3136 break;
3137 default:
3138 printf("mode = unknow,");
3139 break;
3140 }
3141 switch(constel)
3142 {
3143 case 0:
3144 printf(" QPSK, ");
3145 break;
3146 case 1:
3147 printf("16QAM, ");
3148 break;
3149 case 2:
3150 printf("64QAM, ");
3151 break;
3152 default:
3153 printf("unknow QAM, ");
3154 break;
3155 }
3156 switch(gi)
3157 {
3158 case 0:
3159 printf("GI=1/32, ");
3160 break;
3161 case 1:
3162 printf("GI=1/16, ");
3163 break;
3164 case 2:
3165 printf("GI= 1/8, ");
3166 break;
3167 case 3:
3168 printf("GI= 1/4, ");
3169 break;
3170 default:
3171 printf("unknow GI, ");
3172 break;
3173 }
3174
3175 switch(hp_cr)
3176 {
3177 case 0:
3178 printf("HP_CR=1/2, ");
3179 break;
3180 case 1:
3181 printf("HP_CR=2/3, ");
3182 break;
3183 case 2:
3184 printf("HP_CR=3/4, ");
3185 break;
3186 case 3:
3187 printf("HP_CR=5/6, ");
3188 break;
3189 case 4:
3190 printf("HP_CR=7/8, ");
3191 break;
3192 default:
3193 printf("unknow hp_cr, ");
3194 break;
3195 }
3196
3197 switch(lp_cr)
3198 {
3199 case 0:
3200 printf("LP_CR=1/2, ");
3201 break;
3202 case 1:
3203 printf("LP_CR=2/3, ");
3204 break;
3205 case 2:
3206 printf("LP_CR=3/4, ");
3207 break;
3208 case 3:
3209 printf("LP_CR=5/6, ");
3210 break;
3211 case 4:
3212 printf("LP_CR=7/8, ");
3213 break;
3214 default:
3215 printf("unknow lp_cr, ");
3216 break;
3217 }
3218
3219 printf(" Hiearchy=0x%x\n",hiearchy);
3220
3221 // printf("\n");
3222 return TRUE;
3223 }
3224 else
3225 {
3226 printf("INVALID\n");
3227 return FALSE;
3228 }
3229 }
3230
3231
3232
3233
INTERN_DVBT_Show_BER_PacketErr(void)3234 void INTERN_DVBT_Show_BER_PacketErr(void)
3235 {
3236 float f_ber = 0;
3237 MS_U16 packetErr = 0;
3238 INTERN_DVBT_GetPostViterbiBer(&f_ber);
3239 INTERN_DVBT_GetPacketErr(&packetErr);
3240
3241 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3242 return;
3243 }
3244
INTERN_DVBT_Show_Lock_Info(void)3245 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
3246 {
3247
3248 printf("[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
3249 return false;
3250 }
3251
3252
INTERN_DVBT_Show_Demod_Info(void)3253 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
3254 {
3255 MS_U8 demod_state = 0;
3256 MS_BOOL status = true;
3257 static MS_U8 counter = 0;
3258
3259 INTERN_DVBT_get_demod_state(&demod_state);
3260
3261 printf("==========[dvbt]state=%d\n",demod_state);
3262 if (demod_state < 5)
3263 {
3264 INTERN_DVBT_Show_Demod_Version();
3265 INTERN_DVBT_Show_AGC_Info();
3266 INTERN_DVBT_Show_ACI_CI();
3267 }
3268 else if(demod_state < 8)
3269 {
3270 INTERN_DVBT_Show_Demod_Version();
3271 INTERN_DVBT_Show_AGC_Info();
3272 INTERN_DVBT_Show_ACI_CI();
3273 INTERN_DVBT_Show_ChannelLength();
3274 INTERN_DVBT_Get_CFO();
3275 INTERN_DVBT_Get_SFO();
3276 INTERN_DVBT_Show_td_coeff();
3277 }
3278 else if(demod_state < 11)
3279 {
3280 INTERN_DVBT_Show_Demod_Version();
3281 INTERN_DVBT_Show_AGC_Info();
3282 INTERN_DVBT_Show_ACI_CI();
3283 INTERN_DVBT_Show_ChannelLength();
3284 INTERN_DVBT_Get_CFO();
3285 INTERN_DVBT_Get_SFO();
3286 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3287 INTERN_DVBT_Get_SYA_status();
3288 INTERN_DVBT_Show_td_coeff();
3289 }
3290 else if((demod_state == 11) && ((counter%4) == 0))
3291 {
3292 INTERN_DVBT_Show_Demod_Version();
3293 INTERN_DVBT_Show_AGC_Info();
3294 INTERN_DVBT_Show_ACI_CI();
3295 INTERN_DVBT_Show_ChannelLength();
3296 INTERN_DVBT_Get_CFO();
3297 INTERN_DVBT_Get_SFO();
3298 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3299 INTERN_DVBT_Get_SYA_status();
3300 INTERN_DVBT_Show_td_coeff();
3301 INTERN_DVBT_Show_Modulation_info();
3302 INTERN_DVBT_Show_BER_PacketErr();
3303 }
3304 else
3305 status = false;
3306
3307 printf("===========================\n");
3308 counter++;
3309
3310 return status;
3311 }
3312 #endif
3313
3314