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Searched refs:_virtRegBase (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c134 static MS_VIRT _virtRegBase = 0; variable
197 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
198 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
199 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
200 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
211 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
213 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
267 #define TSP_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x6600UL + ((addr)<<2UL))))
287 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
327 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
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/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c134 static MS_VIRT _virtRegBase = 0; variable
200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
201 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
202 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
203 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
214 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
216 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
272 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1400UL + ((addr)<<2UL))))
326 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
410 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
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/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c134 static MS_VIRT _virtRegBase = 0; variable
200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
201 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
202 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
203 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
214 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
216 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
272 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1400UL + ((addr)<<2UL))))
326 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
410 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
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/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c134 static MS_VIRT _virtRegBase = 0; variable
200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
201 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
202 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
203 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
214 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
216 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
268 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1400UL + ((addr)<<2UL))))
318 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
395 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
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/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c134 static MS_VIRT _virtRegBase = 0; variable
200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
201 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
202 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
203 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
214 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
216 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
268 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1400UL + ((addr)<<2UL))))
318 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
395 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
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/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c129 static MS_VIRT _virtRegBase = 0; variable
196 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
197 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
198 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
199 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
209 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
211 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
267 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1400UL + ((addr)<<2UL))))
314 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
389 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
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/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c125 static MS_VIRT _virtRegBase = 0; variable
178 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
180 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
203 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
295 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
296 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
297 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
298 #define ADDR_INDR_WRITE0 (_virtRegBase+ 0x2b2cUL)
299 #define ADDR_INDR_WRITE1 (_virtRegBase+ 0x2b30UL)
300 #define ADDR_INDR_READ0 (_virtRegBase+ 0x2b34UL)
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/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c125 static MS_VIRT _virtRegBase = 0; variable
179 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
181 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
204 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
296 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
297 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
298 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
299 #define ADDR_INDR_WRITE0 (_virtRegBase+ 0x2b2cUL)
300 #define ADDR_INDR_WRITE1 (_virtRegBase+ 0x2b30UL)
301 #define ADDR_INDR_READ0 (_virtRegBase+ 0x2b34UL)
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/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c129 static MS_VIRT _virtRegBase = 0; variable
195 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
197 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
253 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1400UL + ((addr)<<2UL))))
300 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
375 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
386 #define TSP_TS_SAMPLE_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x21400 + ((addr)<<2))))
489 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
490 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
491 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
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/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c125 static MS_VIRT _virtRegBase = 0; variable
179 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
181 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
204 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
299 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
300 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
301 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
302 #define ADDR_INDR_WRITE0 (_virtRegBase+ 0x2b2cUL)
303 #define ADDR_INDR_WRITE1 (_virtRegBase+ 0x2b30UL)
304 #define ADDR_INDR_READ0 (_virtRegBase+ 0x2b34UL)
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/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/tee/
H A DhalTSP_tee.c110 static MS_VIRT _virtRegBase = 0; variable
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27E00 + ((addr)<<2))))
118 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0xE0400 + ((addr)<<2))))
129 _virtRegBase = virtBankAddr; in HAL_TSP_Tee_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/tee/
H A DhalTSP_tee.c110 static MS_VIRT _virtRegBase = 0; variable
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3800 + ((addr)<<2))))
118 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0xE0400 + ((addr)<<2))))
129 _virtRegBase = virtBankAddr; in HAL_TSP_Tee_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/tee/
H A DhalTSP_tee.c110 static MS_VIRT _virtRegBase = 0; variable
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3800 + ((addr)<<2))))
128 _virtRegBase = virtBankAddr; in HAL_TSP_Tee_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/tee/
H A DhalTSP_tee.c110 static MS_VIRT _virtRegBase = 0; variable
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3800 + ((addr)<<2))))
128 _virtRegBase = virtBankAddr; in HAL_TSP_Tee_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/tee/
H A DhalTSP_tee.c110 static MS_VIRT _virtRegBase = 0; variable
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3800 + ((addr)<<2))))
128 _virtRegBase = virtBankAddr; in HAL_TSP_Tee_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/tee/
H A DhalTSP_tee.c110 static MS_VIRT _virtRegBase = 0; variable
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3800 + ((addr)<<2))))
128 _virtRegBase = virtBankAddr; in HAL_TSP_Tee_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/tee/
H A DhalTSP_tee.c110 static MS_VIRT _virtRegBase = 0; variable
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3800 + ((addr)<<2))))
128 _virtRegBase = virtBankAddr; in HAL_TSP_Tee_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/fq/
H A DhalFQ.c94 static MS_VIRT _virtRegBase = 0; variable
114 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<…
161 _virtRegBase = virtBankAddr; in HAL_FQ_SetBank()
162 _REGFIQ = (REG_FIQ*)(_virtRegBase + FQ_REG_CTRL_BASE); in HAL_FQ_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/fq/
H A DhalFQ.c94 static MS_VIRT _virtRegBase = 0; variable
114 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<…
161 _virtRegBase = virtBankAddr; in HAL_FQ_SetBank()
162 _REGFIQ = (REG_FIQ*)(_virtRegBase + FQ_REG_CTRL_BASE); in HAL_FQ_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/fq/
H A DhalFQ.c94 static MS_VIRT _virtRegBase = 0; variable
115 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<…
162 _virtRegBase = virtBankAddr; in HAL_FQ_SetBank()
163 _REGFIQ = (REG_FIQ*)(_virtRegBase + FQ_REG_CTRL_BASE); in HAL_FQ_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/fq/
H A DhalFQ.c94 static MS_VIRT _virtRegBase = 0; variable
115 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<…
162 _virtRegBase = virtBankAddr; in HAL_FQ_SetBank()
163 _REGFIQ = (REG_FIQ*)(_virtRegBase + FQ_REG_CTRL_BASE); in HAL_FQ_SetBank()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/mooney/dscmb/
H A DhalDSCMB.c107 #define REG_BASE_BANK _virtRegBase
121 static MS_VIRT _virtRegBase = 0x0UL; variable
/utopia/UTPA2-700.0.x/modules/dscmb/hal/mainz/dscmb/
H A DhalDSCMB.c107 #define REG_BASE_BANK _virtRegBase
121 static MS_VIRT _virtRegBase = 0x0UL; variable
/utopia/UTPA2-700.0.x/modules/dscmb/hal/messi/dscmb/
H A DhalDSCMB.c107 #define REG_BASE_BANK _virtRegBase
121 static MS_VIRT _virtRegBase = 0x0UL; variable