125 static MS_VIRT _virtRegBase = 0;  variable
178 #define TSP_INT_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
180 #define TSP_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
203 #define TSP_TOP_REG(addr)           (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
295 #define ADDR_INDR_CTRL          (_virtRegBase+ 0x2b20UL)
296 #define ADDR_INDR_ADDR0         (_virtRegBase+ 0x2b24UL)
297 #define ADDR_INDR_ADDR1         (_virtRegBase+ 0x2b28UL)
298 #define ADDR_INDR_WRITE0        (_virtRegBase+ 0x2b2cUL)
299 #define ADDR_INDR_WRITE1        (_virtRegBase+ 0x2b30UL)
300 #define ADDR_INDR_READ0         (_virtRegBase+ 0x2b34UL)
301 #define ADDR_INDR_READ1         (_virtRegBase+ 0x2b38UL)
304 #define XBYTE_1591              (_virtRegBase+ 0x2a0cUL)  // TsRec_Head21_Mid20
305 #define XBYTE_15A4              (_virtRegBase+ 0x2a10UL)  // TsRec_Mid21_Tail20
306 #define XBYTE_15A6              (_virtRegBase+ 0x2b48UL)  // TsRec_Mid
344 #define TSP_SEM_AEON              (_virtRegBase+ 0xC1480UL)   //TSP_HW_SEMAPHORE0, TS3 0x20
345 #define TSP_SEM_ORDER             (_virtRegBase+ 0xC1484UL)  // TSP_HW_SEMAPHORE1, TS3 0x21
346 #define TSP_SEM_MIPS              (_virtRegBase+ 0xC1488UL)  // TSP_HW_SEMAPHORE2, TS3 0x22
1082 #define ADDR_PVR_HEAD20         (_virtRegBase+ 0x2a04)  in HAL_TSP_PVR_SetBuffer()
1083 #define ADDR_PVR_HEAD21         (_virtRegBase+ 0x2a08)  in HAL_TSP_PVR_SetBuffer()
1084 #define ADDR_PVR_MID20          (_virtRegBase+ 0x2a0c)  in HAL_TSP_PVR_SetBuffer()
1085 #define ADDR_PVR_MID21          (_virtRegBase+ 0x2a10)  in HAL_TSP_PVR_SetBuffer()
1086 #define ADDR_PVR_TAIL20         (_virtRegBase+ 0x2a14)  in HAL_TSP_PVR_SetBuffer()
1087 #define ADDR_PVR_TAIL21         (_virtRegBase+ 0x2a18)  in HAL_TSP_PVR_SetBuffer()
1939 #define ADDR_AVFIFO_STATUS         (_virtRegBase+ 0x2adc)
1969     _virtRegBase = u32NonPmBankAddr;  in HAL_TSP_SetBank()
1970     _TspCtrl  = (REG_Ctrl*)(_virtRegBase  + REG_CTRL_BASE);  in HAL_TSP_SetBank()
1971     _TspCtrl2 = (REG_Ctrl2*)(_virtRegBase + REG_CTRL_MMFIBASE);  in HAL_TSP_SetBank()
1972     _TspCtrl3 = (REG_Ctrl3*)(_virtRegBase + REG_CTRL_BASE_TS3);  in HAL_TSP_SetBank()
2761         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
2762 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_TSP_DISABLE|CLK_TSP_INVERT…  in HAL_TSP_PowerCtrl()
2765         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
2766 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_DISABLE|CLK_PAR_INVERT…  in HAL_TSP_PowerCtrl()
2768         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
2769             SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_CLK_192)));  in HAL_TSP_PowerCtrl()
2772 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L …  in HAL_TSP_PowerCtrl()
2778         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
2779 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|…  in HAL_TSP_PowerCtrl()
2782         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
2783 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|…  in HAL_TSP_PowerCtrl()
2786         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),  in HAL_TSP_PowerCtrl()
2787             SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_SYN_STC0_432M));  in HAL_TSP_PowerCtrl()
2790         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
2791 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_STC_DISABLE|CLK_STC_INVERT…  in HAL_TSP_PowerCtrl()
2794         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),  in HAL_TSP_PowerCtrl()
2795 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INV…  in HAL_TSP_PowerCtrl()
2798         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE),  in HAL_TSP_PowerCtrl()
2799 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), (CKG2_TSP_TS_SAMPLE_DISAB…  in HAL_TSP_PowerCtrl()
2805 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
2808 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB…  in HAL_TSP_PowerCtrl()
2811 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB…  in HAL_TSP_PowerCtrl()
2814 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
2817 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
2820 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe…  in HAL_TSP_PowerCtrl()
2823 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_v…  in HAL_TSP_PowerCtrl()