Lines Matching refs:_virtRegBase
134 static MS_VIRT _virtRegBase = 0; variable
197 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
198 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
199 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
200 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
211 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
213 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
267 #define TSP_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x6600UL + ((addr)<<2UL))))
287 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
327 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
337 #define TSP_TS_SAMPLE_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x21600 + ((addr)<<2))))
440 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
441 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
442 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
443 #define ADDR_INDR_WRITE0 (_virtRegBase+ 0x2b2cUL)
444 #define ADDR_INDR_WRITE1 (_virtRegBase+ 0x2b30UL)
445 #define ADDR_INDR_READ0 (_virtRegBase+ 0x2b34UL)
446 #define ADDR_INDR_READ1 (_virtRegBase+ 0x2b38UL)
448 #define ADDR_MOBF_FILEIN (_virtRegBase+ 0x2a2cUL)
451 #define XBYTE_1591 (_virtRegBase+ 0x2a0cUL) // TsRec_Head21_Mid20
452 #define XBYTE_15A4 (_virtRegBase+ 0x2a10UL) // TsRec_Mid21_Tail20
453 #define XBYTE_15A6 (_virtRegBase+ 0x2b48UL) // TsRec_Mid
491 #define TSP_SEM_AEON (_virtRegBase+ 0x2a34UL) //sw_mail_box0
492 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1
493 #define TSP_SEM_MIPS (_virtRegBase+ 0x2b5cUL) // sw_mail_box2
704 #define ADDR_HWINT2 (_virtRegBase+ 0x2db0UL)
1143 #define ADDR_SWINT2_L (_virtRegBase+ 0x2db4UL)
1144 #define ADDR_SWINT2_H (_virtRegBase+ 0x2db8UL)
1478 #define ADDR_PVR_HEAD20 (_virtRegBase+ 0x2a04UL) in HAL_TSP_PVR_SetBuffer()
1479 #define ADDR_PVR_HEAD21 (_virtRegBase+ 0x2a08UL) in HAL_TSP_PVR_SetBuffer()
1480 #define ADDR_PVR_MID20 (_virtRegBase+ 0x2a0cUL) in HAL_TSP_PVR_SetBuffer()
1481 #define ADDR_PVR_MID21 (_virtRegBase+ 0x2a10UL) in HAL_TSP_PVR_SetBuffer()
1482 #define ADDR_PVR_TAIL20 (_virtRegBase+ 0x2a14UL) in HAL_TSP_PVR_SetBuffer()
1483 #define ADDR_PVR_TAIL21 (_virtRegBase+ 0x2a18UL) in HAL_TSP_PVR_SetBuffer()
2954 _virtRegBase = virtBankAddr; in HAL_TSP_SetBank()
2956 _TspCtrl = (REG_Ctrl*)(_virtRegBase + REG_CTRL_BASE); in HAL_TSP_SetBank()
2957 _TspCtrl2 = (REG_Ctrl2*)(_virtRegBase + REG_CTRL_MMFIBASE); in HAL_TSP_SetBank()
2958 _TspCtrl3 = (REG_Ctrl3*)(_virtRegBase + REG_CTRL_TSP3); in HAL_TSP_SetBank()
2959 _TspCtrl4 = (REG_Ctrl4*)(_virtRegBase + REG_CTRL_TSP4); in HAL_TSP_SetBank()
2960 _TspCtrl5 = (REG_Ctrl5*)(_virtRegBase + REG_CTRL_TSP5); in HAL_TSP_SetBank()
2961 _TspCtrl6 = (REG_Ctrl6*)(_virtRegBase + REG_CTRL_TSP6); in HAL_TSP_SetBank()
2962 _TspSample = (REG_TS_Sample*)(_virtRegBase + REG_CTRL_TS_SAMPLE); in HAL_TSP_SetBank()
3753 #define ADDR_SWINT2_L (_virtRegBase+ 0x2db4UL)
3754 #define ADDR_SWINT2_H (_virtRegBase+ 0x2db8UL)
4201 _HAL_REG32L_W((REG32_L *)(_virtRegBase+u32RegClkSrc), in HAL_TSP_SetPVRTimeStampClk()
4202 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+u32RegClkSrc)) & ~u32RegClkMask) | (u32Clk << u32RegShift)… in HAL_TSP_SetPVRTimeStampClk()
4374 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS4_FIQ), RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe… in HAL_TSP_PowerCtrl()
4381 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L … in HAL_TSP_PowerCtrl()
4387 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_SW_CLK), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtR… in HAL_TSP_PowerCtrl()
4390 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN), in HAL_TSP_PowerCtrl()
4391 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN)) & ~CKG_CLK_STCSYN_MASK) | CKG_CLK_STCSYN_… in HAL_TSP_PowerCtrl()
4392 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN), in HAL_TSP_PowerCtrl()
4393 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN)) & ~CKG_CLK_STC1SYN_MASK) | CKG_CLK_STC1SY… in HAL_TSP_PowerCtrl()
4394 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1), in HAL_TSP_PowerCtrl()
4395 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1)) & ~CKG_CLK_STC2SYN_MASK) | CKG_CLK_STC2S… in HAL_TSP_PowerCtrl()
4396 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1), in HAL_TSP_PowerCtrl()
4397 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1)) & ~CKG_CLK_STC3SYN_MASK) | CKG_CLK_STC3S… in HAL_TSP_PowerCtrl()
4413 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS2), in HAL_TSP_PowerCtrl()
4414 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS2)), (CLK_TS2_DISABLE|CLK_TS2_INVERT|CLK_… in HAL_TSP_PowerCtrl()
4417 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TSP_TSFI), in HAL_TSP_PowerCtrl()
4418 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG1_TSP_TSFI)), (CKG1_TSP_TSFI_DISABLE|CKG1_TS… in HAL_TSP_PowerCtrl()
4421 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), in HAL_TSP_PowerCtrl()
4422 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR)), (CLK_STC_DISABLE|CLK_STC_IN… in HAL_TSP_PowerCtrl()
4425 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC), in HAL_TSP_PowerCtrl()
4426 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC)) & ~(CLK_STC0_DISABLE|CLK_STC0_INVERT|CLK_STC… in HAL_TSP_PowerCtrl()
4429 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC), in HAL_TSP_PowerCtrl()
4430 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC)) & ~(CLK_STC1_DISABLE|CLK_STC1_INVERT|CLK_STC… in HAL_TSP_PowerCtrl()
4434 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), in HAL_TSP_PowerCtrl()
4435 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INV… in HAL_TSP_PowerCtrl()
4438 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TS_SAMPLE), in HAL_TSP_PowerCtrl()
4439 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG1_TS_SAMPLE)), (CLK1_TS_SAMPLE_DISABLE|CLK1_… in HAL_TSP_PowerCtrl()
4443 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0), in HAL_TSP_PowerCtrl()
4444 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0)) & ~(CLK_STC_TSIF0_DISABLE|CLK_STC_… in HAL_TSP_PowerCtrl()
4445 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0), in HAL_TSP_PowerCtrl()
4446 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0)) & ~(CLK_STC_MM0_DISABLE|CLK_STC_MM… in HAL_TSP_PowerCtrl()
4449 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1), in HAL_TSP_PowerCtrl()
4450 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_MM1_DISABLE|CLK_STC_MM1… in HAL_TSP_PowerCtrl()
4451 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1), in HAL_TSP_PowerCtrl()
4452 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PV… in HAL_TSP_PowerCtrl()
4455 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2), in HAL_TSP_PowerCtrl()
4456 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_I… in HAL_TSP_PowerCtrl()
4462 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS4_FIQ), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB… in HAL_TSP_PowerCtrl()
4465 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtR… in HAL_TSP_PowerCtrl()
4476 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS2), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+… in HAL_TSP_PowerCtrl()
4479 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TSP_TSFI),SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg… in HAL_TSP_PowerCtrl()
4483 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_vir… in HAL_TSP_PowerCtrl()
4486 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC),SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBa… in HAL_TSP_PowerCtrl()
4489 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC),SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBa… in HAL_TSP_PowerCtrl()
4492 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_vir… in HAL_TSP_PowerCtrl()
4495 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe… in HAL_TSP_PowerCtrl()
4498 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0), in HAL_TSP_PowerCtrl()
4499 …SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0)), (CLK_STC_TSIF0_DISABLE|C… in HAL_TSP_PowerCtrl()
4502 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1), in HAL_TSP_PowerCtrl()
4503 …SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_… in HAL_TSP_PowerCtrl()
4506 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2), in HAL_TSP_PowerCtrl()
4507 … SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)), CLK_STC_PVR2_DISABLE)); in HAL_TSP_PowerCtrl()
4527 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS4_FIQ), RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe… in HAL_TSP_PowerCtrl()
4530 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), in HAL_TSP_PowerCtrl()
4531 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR)), (CLK_TSP_DISABLE|CLK_TSP_IN… in HAL_TSP_PowerCtrl()
4534 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L … in HAL_TSP_PowerCtrl()
4540 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_SW_CLK), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtR… in HAL_TSP_PowerCtrl()
4543 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN), in HAL_TSP_PowerCtrl()
4544 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN)) & ~CKG_CLK_STCSYN_MASK) | CKG_CLK_STCSYN_… in HAL_TSP_PowerCtrl()
4545 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN), in HAL_TSP_PowerCtrl()
4546 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN)) & ~CKG_CLK_STC1SYN_MASK) | CKG_CLK_STC1SY… in HAL_TSP_PowerCtrl()
4547 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1), in HAL_TSP_PowerCtrl()
4548 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1)) & ~CKG_CLK_STC2SYN_MASK) | CKG_CLK_STC2S… in HAL_TSP_PowerCtrl()
4549 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1), in HAL_TSP_PowerCtrl()
4550 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_CLK_STCSYN1)) & ~CKG_CLK_STC3SYN_MASK) | CKG_CLK_STC3S… in HAL_TSP_PowerCtrl()
4553 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), in HAL_TSP_PowerCtrl()
4554 …(RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR)), (CLK_PAR_DISABLE|CLK_PAR_I… in HAL_TSP_PowerCtrl()
4557 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), in HAL_TSP_PowerCtrl()
4558 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|… in HAL_TSP_PowerCtrl()
4561 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), in HAL_TSP_PowerCtrl()
4562 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|… in HAL_TSP_PowerCtrl()
4565 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS2), in HAL_TSP_PowerCtrl()
4566 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS2)), (CLK_TS2_DISABLE|CLK_TS2_INVERT|CLK_… in HAL_TSP_PowerCtrl()
4569 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TSP_TSFI), in HAL_TSP_PowerCtrl()
4570 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG1_TSP_TSFI)), (CKG1_TSP_TSFI_DISABLE|CKG1_TS… in HAL_TSP_PowerCtrl()
4573 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), in HAL_TSP_PowerCtrl()
4574 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR)), (CLK_STC_DISABLE|CLK_STC_IN… in HAL_TSP_PowerCtrl()
4577 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC), in HAL_TSP_PowerCtrl()
4578 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC)) & ~(CLK_STC0_DISABLE|CLK_STC0_INVERT|CLK_STC… in HAL_TSP_PowerCtrl()
4581 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC), in HAL_TSP_PowerCtrl()
4582 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC)) & ~(CLK_STC1_DISABLE|CLK_STC1_INVERT|CLK_STC… in HAL_TSP_PowerCtrl()
4586 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), in HAL_TSP_PowerCtrl()
4587 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INV… in HAL_TSP_PowerCtrl()
4590 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TS_SAMPLE), in HAL_TSP_PowerCtrl()
4591 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG1_TS_SAMPLE)), (CLK1_TS_SAMPLE_DISABLE|CLK1_… in HAL_TSP_PowerCtrl()
4595 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0), in HAL_TSP_PowerCtrl()
4596 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0)) & ~(CLK_STC_TSIF0_DISABLE|CLK_STC_… in HAL_TSP_PowerCtrl()
4597 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0), in HAL_TSP_PowerCtrl()
4598 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0)) & ~(CLK_STC_MM0_DISABLE|CLK_STC_MM… in HAL_TSP_PowerCtrl()
4601 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1), in HAL_TSP_PowerCtrl()
4602 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_MM1_DISABLE|CLK_STC_MM1… in HAL_TSP_PowerCtrl()
4603 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1), in HAL_TSP_PowerCtrl()
4604 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PV… in HAL_TSP_PowerCtrl()
4607 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2), in HAL_TSP_PowerCtrl()
4608 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_I… in HAL_TSP_PowerCtrl()
4614 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS4_FIQ), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB… in HAL_TSP_PowerCtrl()
4617 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtR… in HAL_TSP_PowerCtrl()
4620 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB… in HAL_TSP_PowerCtrl()
4623 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB… in HAL_TSP_PowerCtrl()
4626 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS2), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+… in HAL_TSP_PowerCtrl()
4629 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG1_TSP_TSFI),SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg… in HAL_TSP_PowerCtrl()
4633 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_vir… in HAL_TSP_PowerCtrl()
4636 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC),SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBa… in HAL_TSP_PowerCtrl()
4639 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC),SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBa… in HAL_TSP_PowerCtrl()
4642 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0_PAR), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_vir… in HAL_TSP_PowerCtrl()
4645 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe… in HAL_TSP_PowerCtrl()
4648 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0), in HAL_TSP_PowerCtrl()
4649 …SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_TSIF0_MM0)), (CLK_STC_TSIF0_DISABLE|C… in HAL_TSP_PowerCtrl()
4652 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1), in HAL_TSP_PowerCtrl()
4653 …SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_… in HAL_TSP_PowerCtrl()
4656 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2), in HAL_TSP_PowerCtrl()
4657 … SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)), CLK_STC_PVR2_DISABLE)); in HAL_TSP_PowerCtrl()