129 static MS_VIRT       _virtRegBase   = 0;  variable
196 #define TSP_TSP0_REG(addr)          (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2…
197 #define TSP_TSP1_REG(addr)          (*((volatile MS_U16*)(_virtRegBase + 0x2C00UL + ((addr)<<2UL))))
198 #define TSP_TSP3_REG(addr)          (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP3 + ((addr)<<2…
199 #define TSP_TSP5_REG(addr)          (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_TSP5 + ((addr)<<2…
209 #define TSP_INT_REG(addr)           (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
211 #define TSP_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
267 #define TSP_CLKGEN2_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x1400UL + ((addr)<<2UL))))
314 #define TSP_TOP_REG(addr)           (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
389 #define TSP_TSO0_REG(addr)           (*((volatile MS_U16*)(_virtRegBase + 0x27400UL + ((addr)<<2UL)…
400 #define TSP_TS_SAMPLE_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x21400 + ((addr)<<2))))
503 #define ADDR_INDR_CTRL          (_virtRegBase+ 0x2b20UL)
504 #define ADDR_INDR_ADDR0         (_virtRegBase+ 0x2b24UL)
505 #define ADDR_INDR_ADDR1         (_virtRegBase+ 0x2b28UL)
506 #define ADDR_INDR_WRITE0        (_virtRegBase+ 0x2b2cUL)
507 #define ADDR_INDR_WRITE1        (_virtRegBase+ 0x2b30UL)
508 #define ADDR_INDR_READ0         (_virtRegBase+ 0x2b34UL)
509 #define ADDR_INDR_READ1         (_virtRegBase+ 0x2b38UL)
511 #define ADDR_MOBF_FILEIN        (_virtRegBase+ 0x2a2cUL)
514 #define XBYTE_1591              (_virtRegBase+ 0x2a0cUL)  // TsRec_Head21_Mid20
515 #define XBYTE_15A4              (_virtRegBase+ 0x2a10UL)  // TsRec_Mid21_Tail20
516 #define XBYTE_15A6              (_virtRegBase+ 0x2b48UL)  // TsRec_Mid
554 #define TSP_SEM_AEON              (_virtRegBase+ 0x2a34UL)  //sw_mail_box0
555 #define TSP_SEM_ORDER             (_virtRegBase+ 0x2b58UL)  // sw_mail_box1
556 #define TSP_SEM_MIPS              (_virtRegBase+ 0x2b5cUL)  // sw_mail_box2
767 #define ADDR_HWINT2         (_virtRegBase+ 0x2db0UL)
1190 #define ADDR_SWINT2_L           (_virtRegBase+ 0x2db4UL)
1191 #define ADDR_SWINT2_H           (_virtRegBase+ 0x2db8UL)
1529 #define ADDR_PVR_HEAD20         (_virtRegBase+ 0x2a04UL)  in HAL_TSP_PVR_SetBuffer()
1530 #define ADDR_PVR_HEAD21         (_virtRegBase+ 0x2a08UL)  in HAL_TSP_PVR_SetBuffer()
1531 #define ADDR_PVR_MID20          (_virtRegBase+ 0x2a0cUL)  in HAL_TSP_PVR_SetBuffer()
1532 #define ADDR_PVR_MID21          (_virtRegBase+ 0x2a10UL)  in HAL_TSP_PVR_SetBuffer()
1533 #define ADDR_PVR_TAIL20         (_virtRegBase+ 0x2a14UL)  in HAL_TSP_PVR_SetBuffer()
1534 #define ADDR_PVR_TAIL21         (_virtRegBase+ 0x2a18UL)  in HAL_TSP_PVR_SetBuffer()
3018     _virtRegBase   = virtBankAddr;  in HAL_TSP_SetBank()
3020     _TspCtrl   = (REG_Ctrl*)(_virtRegBase  + REG_CTRL_BASE);  in HAL_TSP_SetBank()
3021     _TspCtrl2  = (REG_Ctrl2*)(_virtRegBase + REG_CTRL_MMFIBASE);  in HAL_TSP_SetBank()
3022     _TspCtrl3  = (REG_Ctrl3*)(_virtRegBase + REG_CTRL_TSP3);  in HAL_TSP_SetBank()
3023     _TspCtrl4  = (REG_Ctrl4*)(_virtRegBase + REG_CTRL_TSP4);  in HAL_TSP_SetBank()
3024     _TspCtrl5  = (REG_Ctrl5*)(_virtRegBase + REG_CTRL_TSP5);  in HAL_TSP_SetBank()
3025     _TspSample = (REG_TS_Sample*)(_virtRegBase + REG_CTRL_TS_SAMPLE);  in HAL_TSP_SetBank()
3728 #define ADDR_SWINT2_L           (_virtRegBase+ 0x2db4UL)
3729 #define ADDR_SWINT2_H           (_virtRegBase+ 0x2db8UL)
4268         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
4269 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_TSP_DISABLE|CLK_TSP_INVERT…  in HAL_TSP_PowerCtrl()
4272 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L …  in HAL_TSP_PowerCtrl()
4278         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
4279 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_DISABLE|CLK_PAR_INVERT…  in HAL_TSP_PowerCtrl()
4282         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
4283 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|…  in HAL_TSP_PowerCtrl()
4286         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
4287 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|…  in HAL_TSP_PowerCtrl()
4290         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS2_TSGP),  in HAL_TSP_PowerCtrl()
4291 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS2_TSGP)), (CLK_TS2_DISABLE|CLK_TS2_INVERT…  in HAL_TSP_PowerCtrl()
4294         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TSFI),  in HAL_TSP_PowerCtrl()
4295 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TSFI)), (CKG2_TSP_TSFI_DISABKE|CKG2_TS…  in HAL_TSP_PowerCtrl()
4298         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),  in HAL_TSP_PowerCtrl()
4299 …SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_SYN_STC0_432M|CLK_SYN_STC1_…  in HAL_TSP_PowerCtrl()
4302         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
4303 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_STC_DISABLE|CLK_STC_INVERT…  in HAL_TSP_PowerCtrl()
4306         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
4307 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_STC1_DISABLE|CLK_STC1_INVE…  in HAL_TSP_PowerCtrl()
4310         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),  in HAL_TSP_PowerCtrl()
4311 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INV…  in HAL_TSP_PowerCtrl()
4314         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE),  in HAL_TSP_PowerCtrl()
4315 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), (CKG2_TSP_TS_SAMPLE_DISAB…  in HAL_TSP_PowerCtrl()
4320 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
4323 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB…  in HAL_TSP_PowerCtrl()
4326 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB…  in HAL_TSP_PowerCtrl()
4329 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS2_TSGP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
4332 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TSFI), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe…  in HAL_TSP_PowerCtrl()
4335 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
4338 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
4341 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
4344 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe…  in HAL_TSP_PowerCtrl()
4347 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_v…  in HAL_TSP_PowerCtrl()