125 static MS_VIRT _virtRegBase = 0;  variable
179 #define TSP_INT_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
181 #define TSP_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
204 #define TSP_TOP_REG(addr)           (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
299 #define ADDR_INDR_CTRL          (_virtRegBase+ 0x2b20UL)
300 #define ADDR_INDR_ADDR0         (_virtRegBase+ 0x2b24UL)
301 #define ADDR_INDR_ADDR1         (_virtRegBase+ 0x2b28UL)
302 #define ADDR_INDR_WRITE0        (_virtRegBase+ 0x2b2cUL)
303 #define ADDR_INDR_WRITE1        (_virtRegBase+ 0x2b30UL)
304 #define ADDR_INDR_READ0         (_virtRegBase+ 0x2b34UL)
305 #define ADDR_INDR_READ1         (_virtRegBase+ 0x2b38UL)
308 #define XBYTE_1591              (_virtRegBase+ 0x2a0cUL)  // TsRec_Head21_Mid20
309 #define XBYTE_15A4              (_virtRegBase+ 0x2a10UL)  // TsRec_Mid21_Tail20
310 #define XBYTE_15A6              (_virtRegBase+ 0x2b48UL)  // TsRec_Mid
348 #define TSP_SEM_AEON              (_virtRegBase+ 0xC1480UL)   //TSP_HW_SEMAPHORE0, TS3 0x20
349 #define TSP_SEM_ORDER             (_virtRegBase+ 0xC1484UL)  // TSP_HW_SEMAPHORE1, TS3 0x21
350 #define TSP_SEM_MIPS              (_virtRegBase+ 0xC1488UL)  // TSP_HW_SEMAPHORE2, TS3 0x22
1086 #define ADDR_PVR_HEAD20         (_virtRegBase+ 0x2a04)  in HAL_TSP_PVR_SetBuffer()
1087 #define ADDR_PVR_HEAD21         (_virtRegBase+ 0x2a08)  in HAL_TSP_PVR_SetBuffer()
1088 #define ADDR_PVR_MID20          (_virtRegBase+ 0x2a0c)  in HAL_TSP_PVR_SetBuffer()
1089 #define ADDR_PVR_MID21          (_virtRegBase+ 0x2a10)  in HAL_TSP_PVR_SetBuffer()
1090 #define ADDR_PVR_TAIL20         (_virtRegBase+ 0x2a14)  in HAL_TSP_PVR_SetBuffer()
1091 #define ADDR_PVR_TAIL21         (_virtRegBase+ 0x2a18)  in HAL_TSP_PVR_SetBuffer()
1961 #define ADDR_AVFIFO_STATUS         (_virtRegBase+ 0x2adc)
1993     _virtRegBase = u32NonPmBankAddr;  in HAL_TSP_SetBank()
1994     _TspCtrl  = (REG_Ctrl*)(_virtRegBase  + REG_CTRL_BASE);  in HAL_TSP_SetBank()
1995     _TspCtrl2 = (REG_Ctrl2*)(_virtRegBase + REG_CTRL_MMFIBASE);  in HAL_TSP_SetBank()
1996     _TspCtrl3 = (REG_Ctrl3*)(_virtRegBase + REG_CTRL_BASE_TS3);  in HAL_TSP_SetBank()
2779         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
2780 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_TSP_DISABLE|CLK_TSP_INVERT…  in HAL_TSP_PowerCtrl()
2783         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
2784 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_DISABLE|CLK_PAR_INVERT…  in HAL_TSP_PowerCtrl()
2787 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L …  in HAL_TSP_PowerCtrl()
2793         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
2794 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|…  in HAL_TSP_PowerCtrl()
2797         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
2798 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|…  in HAL_TSP_PowerCtrl()
2801         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),  in HAL_TSP_PowerCtrl()
2802             SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_SYN_STC0_432M));  in HAL_TSP_PowerCtrl()
2805         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
2806 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_STC_DISABLE|CLK_STC_INVERT…  in HAL_TSP_PowerCtrl()
2809         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),  in HAL_TSP_PowerCtrl()
2810 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INV…  in HAL_TSP_PowerCtrl()
2813         _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE),  in HAL_TSP_PowerCtrl()
2814 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), (CKG2_TSP_TS_SAMPLE_DISAB…  in HAL_TSP_PowerCtrl()
2820 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
2823 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB…  in HAL_TSP_PowerCtrl()
2826 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegB…  in HAL_TSP_PowerCtrl()
2829 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
2832 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtReg…  in HAL_TSP_PowerCtrl()
2835 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRe…  in HAL_TSP_PowerCtrl()
2838 …_HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_v…  in HAL_TSP_PowerCtrl()