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Searched refs:FDP_REG_BASE (Results 1 – 25 of 69) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBT.c1977 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1986 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1992 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1998 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
2029 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
2030 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
2033 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2036 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x4d, &reg); in INTERN_DVBT_GetSNR()
2039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x4c, &reg); in INTERN_DVBT_GetSNR()
2042 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x4b, &reg); in INTERN_DVBT_GetSNR()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT.c1634 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1643 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1649 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1655 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1686 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1687 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1690 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1706 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1712 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT.c1588 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1597 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1603 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1609 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1640 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1641 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1644 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
1663 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1666 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
H A DhalDMD_INTERN_DVBT2.c2268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2269 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2271 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2273 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2276 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2279 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2292 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2312 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c1640 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1649 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1655 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1661 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1693 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1696 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1712 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
1715 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1718 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT.c1833 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1842 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1848 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1854 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1887 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1890 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1906 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
1909 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1912 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
H A DhalDMD_INTERN_DVBT2.c2764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2765 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2767 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2769 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2772 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2775 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2787 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2790 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2800 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2803 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT.c1975 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1984 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1990 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1996 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
2028 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
2029 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
2032 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2048 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
2051 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
2054 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
H A DhalDMD_INTERN_DVBT2.c2547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2548 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2550 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2552 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2558 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2568 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2571 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2591 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBT.c1944 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1953 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1959 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1965 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1997 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
2000 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
2019 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
2022 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT.c1833 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1842 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1848 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1854 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1887 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1890 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1906 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
1909 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1912 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
H A DhalDMD_INTERN_DVBT2.c2764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2765 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2767 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2769 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2772 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2775 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2787 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2790 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2800 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2803 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBT.c1971 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1980 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1986 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1992 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
2023 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
2024 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
2027 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2043 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT_GetSNR()
2046 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
2049 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT.c1735 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1744 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1750 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1756 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1788 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1809 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8] in INTERN_DVBT_Get_CELL_ID()
[all …]
H A DhalDMD_INTERN_DVBT2.c2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2755 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT.c1735 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1744 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1750 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1756 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1788 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1809 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8] in INTERN_DVBT_Get_CELL_ID()
[all …]
H A DhalDMD_INTERN_DVBT2.c2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2755 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT.c1735 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1744 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1750 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1756 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1788 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1809 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8] in INTERN_DVBT_Get_CELL_ID()
[all …]
H A DhalDMD_INTERN_DVBT2.c2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2755 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT.c1735 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1744 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1750 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1756 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1788 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1809 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8] in INTERN_DVBT_Get_CELL_ID()
[all …]
H A DhalDMD_INTERN_DVBT2.c2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2755 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT.c1735 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1744 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1750 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1756 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1788 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1809 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8] in INTERN_DVBT_Get_CELL_ID()
[all …]
H A DhalDMD_INTERN_DVBT2.c2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2755 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT.c1735 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE) in INTERN_DVBT_Get_TPS_Info()
1744 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1750 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1756 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE ) in INTERN_DVBT_Get_TPS_Info()
1788 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT_GetSNR()
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT_GetSNR()
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
1809 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz); in INTERN_DVBT_GetSNR()
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT_GetSNR()
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8] in INTERN_DVBT_Get_CELL_ID()
[all …]
H A DhalDMD_INTERN_DVBT2.c2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, &reg_frz); in INTERN_DVBT2_Get_FreqOffset()
2717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01); in INTERN_DVBT2_Get_FreqOffset()
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01); in INTERN_DVBT2_Get_FreqOffset()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, &reg); in INTERN_DVBT2_Get_FreqOffset()
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, &reg); in INTERN_DVBT2_Get_FreqOffset()
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, &reg); in INTERN_DVBT2_Get_FreqOffset()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, &reg); in INTERN_DVBT2_Get_FreqOffset()
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, &reg); in INTERN_DVBT2_Get_FreqOffset()
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &reg); in INTERN_DVBT2_Get_FreqOffset()
2755 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01)); in INTERN_DVBT2_Get_FreqOffset()
[all …]

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