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93 ////////////////////////////////////////////////////////////////////////////////
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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #include "ULog.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
133
134 #define TDE_REG_BASE 0x2400UL
135 #define DIV_REG_BASE 0x2500UL
136 #define TR_REG_BASE 0x2600UL
137 #define FTN_REG_BASE 0x2700UL
138 #define FTNEXT_REG_BASE 0x2800UL
139
140
141
142 #if 0//ENABLE_SCAN_ONELINE_MSG
143 #define DBG_INTERN_DVBT_ONELINE(x) x
144 #else
145 #define DBG_INTERN_DVBT_ONELINE(x) // x
146 #endif
147
148 #ifdef MS_DEBUG
149 #define DBG_INTERN_DVBT(x) x
150 #define DBG_GET_SIGNAL(x) x
151 #define DBG_INTERN_DVBT_TIME(x) x
152 #define DBG_INTERN_DVBT_LOCK(x) x
153 #else
154 #define DBG_INTERN_DVBT(x) //x
155 #define DBG_GET_SIGNAL(x) //x
156 #define DBG_INTERN_DVBT_TIME(x) // x
157 #define DBG_INTERN_DVBT_LOCK(x) //x
158 #endif
159 #define DBG_DUMP_LOAD_DSP_TIME 0
160
161 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
162 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
163 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
164 #define INTERN_DVBT_INTERNAL_DEBUG 1
165
166 #define SIGNAL_LEVEL_OFFSET 0.00
167 #define TAKEOVERPOINT -59.0
168 #define TAKEOVERRANGE 0.5
169 #define LOG10_OFFSET -0.21
170 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
171 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
172
173
174 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
175 #define TUNER_VPP 2
176 #define IF_AGC_VPP 2
177 #else
178 #define TUNER_VPP 1
179 #define IF_AGC_VPP 2
180 #endif
181
182 #if (TUNER_VPP == 1)
183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
184 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
186 #endif
187
188 /*BEG INTERN_DVBT_DSPREG_TABLE*/
189 #define D_DMD_DVBT_PARAM_VERSION 0x01
190 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
191 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
192 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
193 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
194 #define D_DMD_DVBT_OP_DCR_EN 0x01
195 #define D_DMD_DVBT_OP_IIS_EN 0x01
196 #define D_DMD_DVBT_OP_IQB_EN 0x00
197 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
198 #define D_DMD_DVBT_OP_ACI_EN 0x01
199 #define D_DMD_DVBT_OP_CCI_EN 0x01
200 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
201 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
202 #define D_DMD_DVBT_CFG_BW 0x00 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
203 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
204 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
205 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
206 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
207 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
208 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
209 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
210 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
211 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
212 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
213 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
214 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
215 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
216 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
217 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
218 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
219 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
220 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
221 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
222
223 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
224 #define D_DMD_DVBT_CFG_FC_H 0x4E
225 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
226 #define D_DMD_DVBT_CFG_FS_H 0x5D
227 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
228
229 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
230 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
231 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
232 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
233 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
234 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
235 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
236 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
237 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
238 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
239 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
240 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
241
242 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
243 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
244 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
245 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
246 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
247 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
248 #else
249 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
250 #endif
251 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
252 //#define DMD_DVBT_CHECKSUM 0x00
253 /*END INTERN_DVBT_DSPREG_TABLE*/
254 #define DVBT_FS 45474 // 24000
255 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
256 #define FC_L 0x20 // 0323 jason
257 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
258 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
259 #define SET_ZIF 0x00
260 #define IQB_EN 0x00
261
262 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
263 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
264 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
265 #define CSTL 0x02 //0:QPSK 1:16 2: 64
266 #define HIER 0x00
267 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
268 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
269 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
270 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
271 #define LP_SEL 0x00 // LP select
272 #define IQ_SWAP 0x00 //0x01
273 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
274 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
275 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
276 #define TS_SER 0
277 #define TS_INV 0
278 #define FIF_H (MS_U8)(( (((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))>>8)
279 #define FIF_L (MS_U8)(( ((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))
280 #define IF_INV_PWM 0x00
281 #define T_LOWIF 1
282
283 // Need to update when:
284 // Case#1: New add DSP parameters
285 // Case#2: Use exist DSP parameters to another applications/functions
286 #define UTOPIA_DRIVER_VERSION 0x01 // Update by user.
287
288 MS_U8 INTERN_DVBT_DSPREG[] =
289 {
290 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
291 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
292 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
293 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
294 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
295 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
296 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
297 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
298 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
299 /*
300 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
301 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
302 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
303 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
304 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
305 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
306 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
307 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
308 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
309 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
310 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
311 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
312 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
313 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
314 */
315 };
316 /*END INTERN_DVBT_DSPREG_TABLE*/
317 //-----------------------------------------------------------------------
318 /****************************************************************
319 *Local Variables *
320 ****************************************************************/
321 static MS_BOOL bFECLock=0;
322 static MS_BOOL bTPSLock = 0;
323 static MS_U32 u32ChkScanTimeStart = 0;
324 static MS_U32 u32FecFirstLockTime=0;
325 static MS_U32 u32FecLastLockTime=0;
326 static float fViterbiBerFiltered=-1;
327 //Global Variables
328 S_CMDPKTREG gsCmdPacket;
329 //U8 gCalIdacCh0, gCalIdacCh1;
330
331 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
332 MS_U8 INTERN_DVBT_table[] = {
333 #include "fwDMD_INTERN_DVBT.dat"
334 };
335
336 #endif
337
338 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
339 {
340 { _QPSK , _CR1Y2, -93},
341 { _QPSK , _CR2Y3, -91},
342 { _QPSK , _CR3Y4, -90},
343 { _QPSK , _CR5Y6, -89},
344 { _QPSK , _CR7Y8, -88},
345
346 { _16QAM , _CR1Y2, -87},
347 { _16QAM , _CR2Y3, -85},
348 { _16QAM , _CR3Y4, -84},
349 { _16QAM , _CR5Y6, -83},
350 { _16QAM , _CR7Y8, -82},
351
352 { _64QAM , _CR1Y2, -82},
353 { _64QAM , _CR2Y3, -80},
354 { _64QAM , _CR3Y4, -78},
355 { _64QAM , _CR5Y6, -77},
356 { _64QAM , _CR7Y8, -76},
357 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
358 };
359
360
361
362 static void INTERN_DVBT_SignalQualityReset(void);
363 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
364
INTERN_DVBT_SignalQualityReset(void)365 static void INTERN_DVBT_SignalQualityReset(void)
366 {
367 u32FecFirstLockTime=0;
368 fViterbiBerFiltered=-1;
369 }
370
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)371 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
372 {
373 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
374 MS_BOOL status = TRUE;
375 MS_U16 u16DspAddr = 0;
376
377 ULOGD("DEMOD","INTERN_DVBT_DSPReg_Init\n");
378
379 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
380 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
381
382 if (u8DVBT_DSPReg != NULL)
383 {
384 /*temp solution until new dsp table applied.*/
385 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
386 if (u8DVBT_DSPReg[0] >= 1)
387 {
388 u8DVBT_DSPReg+=2;
389 for (idx = 0; idx<u8Size; idx++)
390 {
391 u16DspAddr = *u8DVBT_DSPReg;
392 u8DVBT_DSPReg++;
393 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
394 u8DVBT_DSPReg++;
395 u8Mask = *u8DVBT_DSPReg;
396 u8DVBT_DSPReg++;
397 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
398 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
399 u8DVBT_DSPReg++;
400 DBG_INTERN_DVBT(ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
401 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
402 }
403 }
404 else
405 {
406 ULOGE("DEMOD","FATAL: parameter version incorrect\n");
407 }
408 }
409
410 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_PARAM_VERSION, UTOPIA_DRIVER_VERSION) != TRUE)
411 {
412 ULOGD("DEMOD","INTERN_DVBT_DSPReg_Init NG\n");
413 return FALSE;
414 }
415
416 return status;
417 }
418
419 /***********************************************************************************
420 Subject: Command Packet Interface
421 Function: INTERN_DVBT_Cmd_Packet_Send
422 Parmeter:
423 Return: MS_BOOL
424 Remark:
425 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)426 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
427 {
428 MS_U8 status = true, indx;
429 MS_U8 reg_val=0, timeout = 0;
430 return TRUE;
431 //MsOS_ObtainMutex(_s32_Demod_DVBT_Mutex, MSOS_WAIT_FOREVER);
432 // ==== Command Phase ===================
433 ULOGD("DEMOD","--->INTERN_DVBT (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
434 pCmdPacket->param[0],pCmdPacket->param[1],
435 pCmdPacket->param[2],pCmdPacket->param[3],
436 pCmdPacket->param[4],pCmdPacket->param[5] );
437
438 // wait _BIT_END clear
439 do
440 {
441 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
442 if((reg_val & _BIT_END) != _BIT_END)
443 {
444 break;
445 }
446 MsOS_DelayTask(5);
447 if (timeout++ > 200)
448 {
449 ULOGE("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
450 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
451 return false;
452 }
453 } while (1);
454
455 // set cmd_3:0 and _BIT_START
456 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
457 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
459
460
461 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
462 // wait _BIT_START clear
463 do
464 {
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
466 if((reg_val & _BIT_START) != _BIT_START)
467 {
468 break;
469 }
470 MsOS_DelayTask(5);
471 if (timeout++ > 200)
472 {
473 ULOGE("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
474 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
475 return false;
476 }
477 } while (1);
478
479 // ==== Data Phase ======================
480
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
482
483 for (indx = 0; indx < param_cnt; indx++)
484 {
485 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
486 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
487
488 // set param[indx] and _BIT_DRQ
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
490 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
492
493 // wait _BIT_DRQ clear
494 do
495 {
496 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
497 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
498 {
499 break;
500 }
501 MsOS_DelayTask(5);
502 if (timeout++ > 200)
503 {
504 ULOGE("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
505 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
506 return false;
507 }
508 } while (1);
509 }
510
511 // ==== End Phase =======================
512
513 // set _BIT_END to finish command
514 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
516 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
517 return status;
518 }
519
520
521 /***********************************************************************************
522 Subject: Command Packet Interface
523 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
524 Parmeter:
525 Return: MS_BOOL
526 Remark:
527 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)528 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
529 {
530 return TRUE;
531 }
532
533 /***********************************************************************************
534 Subject: SoftStop
535 Function: INTERN_DVBT_SoftStop
536 Parmeter:
537 Return: MS_BOOL
538 Remark:
539 ************************************************************************************/
540
INTERN_DVBT_SoftStop(void)541 MS_BOOL INTERN_DVBT_SoftStop ( void )
542 {
543 #if 1
544 MS_U16 u8WaitCnt=0;
545
546 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
547 {
548 ULOGE("DEMOD",">> MB Busy!\n");
549 return FALSE;
550 }
551
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
553
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
555 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
556
557 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
558 {
559 #if TEST_EMBEDED_DEMOD
560 MsOS_DelayTask(1); // << Ken 20090629
561 #endif
562 if (u8WaitCnt++ >= 0xFF)
563 {
564 ULOGE("DEMOD",">> DVBT SoftStop Fail!\n");
565 return FALSE;
566 }
567 }
568
569 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
571 #endif
572 return TRUE;
573 }
574
575
576 /***********************************************************************************
577 Subject: Reset
578 Function: INTERN_DVBT_Reset
579 Parmeter:
580 Return: MS_BOOL
581 Remark:
582 ************************************************************************************/
583 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)584 MS_BOOL INTERN_DVBT_Reset ( void )
585 {
586 ULOGD("DEMOD"," @INTERN_DVBT_reset\n");
587
588 //ULOGD("DEMOD","INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime());
589
590 INTERN_DVBT_SoftStop();
591
592
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
594 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
595 MsOS_DelayTask(5);
596 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
597 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
598 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
599 MsOS_DelayTask(5);
600
601 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
602 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
603
604 bFECLock = FALSE;
605 bTPSLock = FALSE;
606 u32ChkScanTimeStart = MsOS_GetSystemTime();
607 return TRUE;
608 }
609
610 /***********************************************************************************
611 Subject: Exit
612 Function: INTERN_DVBT_Exit
613 Parmeter:
614 Return: MS_BOOL
615 Remark:
616 ************************************************************************************/
INTERN_DVBT_Exit(void)617 MS_BOOL INTERN_DVBT_Exit ( void )
618 {
619
620 INTERN_DVBT_SoftStop();
621
622 return TRUE;
623 }
624
625 /***********************************************************************************
626 Subject: Load DSP code to chip
627 Function: INTERN_DVBT_LoadDSPCode
628 Parmeter:
629 Return: MS_BOOL
630 Remark:
631 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)632 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
633 {
634 MS_U8 udata = 0x00;
635 MS_U16 i;
636 MS_U16 fail_cnt=0;
637
638 #if (DBG_DUMP_LOAD_DSP_TIME==1)
639 MS_U32 u32Time;
640 #endif
641
642
643 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
644 BININFO BinInfo;
645 MS_BOOL bResult;
646 MS_U32 u32GEAddr;
647 MS_U8 Data;
648 MS_S8 op;
649 MS_U32 srcaddr;
650 MS_U32 len;
651 MS_U32 SizeBy4K;
652 MS_U16 u16Counter=0;
653 MS_U8 *pU8Data;
654 #endif
655
656
657
658 // MDrv_Sys_DisableWatchDog();
659
660
661 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
662 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
663 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
664 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
665 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
666 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
667
668 //// Load code thru VDMCU_IF ////
669 ULOGD("DEMOD",">Load Code...\n");
670 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
671 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
672 {
673 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
674 }
675 #else
676 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
677 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
678 if ( bResult != PASS )
679 {
680 return FALSE;
681 }
682 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
683
684 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
685 InfoBlock_Flash_2_Checking_Start(&BinInfo);
686 #endif
687
688 #if OBA2
689 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
690 #else
691 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
692 #endif
693
694 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
695 InfoBlock_Flash_2_Checking_End(&BinInfo);
696 #endif
697
698 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
699 SizeBy4K=BinInfo.B_Len/0x1000;
700 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
701
702 #if (DBG_DUMP_LOAD_DSP_TIME==1)
703 u32Time = msAPI_Timer_GetTime0();
704 #endif
705
706 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
707
708 for (i=0;i<=SizeBy4K;i++)
709 {
710 if(i==SizeBy4K)
711 len=BinInfo.B_Len%0x1000;
712 else
713 len=0x1000;
714
715 srcaddr = u32GEAddr+(0x1000*i);
716 //ULOGD("DEMOD","\t i = %08X\n", i);
717 //ULOGD("DEMOD","\t len = %08X\n", len);
718 op = 1;
719 u16Counter = 0 ;
720 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
721 while(len--)
722 {
723 u16Counter ++ ;
724 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
725 //pU8Data = (U8 *)(srcaddr|0x80000000);
726 #if OBA2
727 pU8Data = (U8 *)(srcaddr);
728 #else
729 pU8Data = (U8 *)(srcaddr|0x80000000);
730 #endif
731 Data = *pU8Data;
732
733 #if 0
734 if(u16Counter < 0x100)
735 ULOGD("DEMOD","0x%bx,", Data);
736 #endif
737 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
738
739 srcaddr += op;
740 }
741 // ULOGD("DEMOD","\n\n\n");
742 }
743
744 #if (DBG_DUMP_LOAD_DSP_TIME==1)
745 ULOGD("DEMOD","------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
746 #endif
747
748 #endif
749
750 //// Content verification ////
751 ULOGD("DEMOD",">Verify Code...\n");
752
753 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
754 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
755
756 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
757 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
758 {
759 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
760 if (udata != INTERN_DVBT_table[i])
761 {
762 ULOGE("DEMOD",">fail add = 0x%x\n", i);
763 ULOGE("DEMOD",">code = 0x%x\n", INTERN_DVBT_table[i]);
764 ULOGE("DEMOD",">data = 0x%x\n", udata);
765
766 if (fail_cnt++ > 10)
767 {
768 ULOGE("DEMOD",">DVB-T DSP Loadcode fail!");
769 return false;
770 }
771 }
772 }
773 #else
774 for (i=0;i<=SizeBy4K;i++)
775 {
776 if(i==SizeBy4K)
777 len=BinInfo.B_Len%0x1000;
778 else
779 len=0x1000;
780
781 srcaddr = u32GEAddr+(0x1000*i);
782 //ULOGD("DEMOD","\t i = %08LX\n", i);
783 //ULOGD("DEMOD","\t len = %08LX\n", len);
784 op = 1;
785 u16Counter = 0 ;
786 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
787 while(len--)
788 {
789 u16Counter ++ ;
790 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
791 //pU8Data = (U8 *)(srcaddr|0x80000000);
792 #if OBA2
793 pU8Data = (U8 *)(srcaddr);
794 #else
795 pU8Data = (U8 *)(srcaddr|0x80000000);
796 #endif
797 Data = *pU8Data;
798
799 #if 0
800 if(u16Counter < 0x100)
801 ULOGD("DEMOD","0x%bx,", Data);
802 #endif
803 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
804 if (udata != Data)
805 {
806 ULOGE("DEMOD",">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
807 ULOGE("DEMOD",">code = 0x%x\n", Data);
808 ULOGE("DEMOD",">data = 0x%x\n", udata);
809
810 if (fail_cnt++ > 10)
811 {
812 ULOGE("DEMOD",">DVB-T DSP Loadcode fail!");
813 return false;
814 }
815 }
816
817 srcaddr += op;
818 }
819 // ULOGD("DEMOD","\n\n\n");
820 }
821 #endif
822
823 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
824 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
825 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
826 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
827
828 ULOGD("DEMOD",">DSP Loadcode done.");
829 //while(load_data_variable);
830
831
832 return TRUE;
833 }
834
835 /***********************************************************************************
836 Subject: DVB-T CLKGEN initialized function
837 Function: INTERN_DVBT_Power_On_Initialization
838 Parmeter:
839 Return: MS_BOOL
840 Remark:
841 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)842 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
843 {
844 MS_U8 temp_val;
845 MS_U8 udatatemp = 0x00;
846 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
847 // HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
848
849 // Release vivaldi2mi_bridge reset
850 // [0] reg_vivaldi2mi_bridge_rst
851 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
852 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
853 // HAL_DMD_RIU_WriteByte(0x11208E, (HAL_DMD_RIU_ReadByte(0x11208E)&(~(BIT(0)))));
854
855 // ----------------------------------------------
856 // start demod CLKGEN setting
857 // ----------------------------------------------
858 // *** Set register at CLKGEN1
859 // enable DMD MCU clock "bit[0] set 0"
860 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
861 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
862 // CLK_DMDMCU clock setting
863 // [0] disable clock
864 // [1] invert clock
865 // [4:2]
866 // 000:170 MHz(MPLL_DIV_BUf)
867 // 001:160MHz
868 // 010:144MHz
869 // 011:123MHz
870 // 100:108MHz
871 // 101:mem_clcok
872 // 110:mem_clock div 2
873 // 111:select XTAL
874 HAL_DMD_RIU_WriteByte(0x10331f,0x00);//5566
875 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
876
877 // set parallet ts clock
878 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
879 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
880
881 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b
882 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
883 temp_val|=0x07;
884 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
885
886 HAL_DMD_RIU_WriteByte(0x103300,0x17);
887
888 // enable atsc, DVBTC ts clock
889 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
890 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
891 HAL_DMD_RIU_WriteByte(0x103309,0x00);
892 HAL_DMD_RIU_WriteByte(0x103308,0x00);
893
894 // enable dvbc adc clock
895 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
896 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
897 HAL_DMD_RIU_WriteByte(0x103315,0x00);
898 HAL_DMD_RIU_WriteByte(0x103314,0x00);
899
900 udatatemp = HAL_DMD_RIU_ReadByte(0x111f2a);//5566
901 HAL_DMD_RIU_WriteByte(0x111f2a,udatatemp&0xF8);//5566
902
903 // Reset TS divider
904 HAL_DMD_RIU_WriteByte(0x103302,0x01);
905 HAL_DMD_RIU_WriteByte(0x103302,0x00);
906
907 // enable vif DAC clock
908 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
909 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
910 // HAL_DMD_RIU_WriteByte(0x10331b,0x00);
911 // HAL_DMD_RIU_WriteByte(0x10331a,0x00);
912
913 // Select MPLLDIV17
914 // [0] : reg_atsc_adc_sel_mplldiv2
915 // [1] : reg_atsc_eq_sel_mplldiv2
916 // [2] : reg_eq25_sel_mplldiv3
917 // [3] : reg_p4_cfo_sel_eq25
918 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
919 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
920 // HAL_DMD_RIU_WriteByte(0x111f28,0x03);
921
922 // *** Set register at CLKGEN_DMD
923 // enable atsc clock
924 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
925 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
926 // HAL_DMD_RIU_WriteByte(0x111f03,0x04);
927 // HAL_DMD_RIU_WriteByte(0x111f02,0x04);
928 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
929 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
930 // HAL_DMD_RIU_WriteByte(0x111f05,0x00);
931 // HAL_DMD_RIU_WriteByte(0x111f04,0x00);
932 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
933 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
934 // HAL_DMD_RIU_WriteByte(0x111f07,0x04);
935 // HAL_DMD_RIU_WriteByte(0x111f06,0x04);
936
937 // enable clk_atsc_adcd_sync
938 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
939 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
940 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
941 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
942
943 // enable dvbt inner clock
944 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
945 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
946 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
947 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
948
949 // enable dvbt inner clock
950 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
951 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
952 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
953 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
954
955 // enable dvbt inner clock
956 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
957 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
958 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
959 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
960
961 // enable dvbc outer clock
962 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
963 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
964 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
965 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
966
967 // enable dvbc inner-c clock
968 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
969 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
970 // HAL_DMD_RIU_WriteByte(0x111f15,0x00);
971 // HAL_DMD_RIU_WriteByte(0x111f14,0x00);
972
973 // enable dvbc eq clock
974 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
975 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
976 // HAL_DMD_RIU_WriteByte(0x111f17,0x00);
977 // HAL_DMD_RIU_WriteByte(0x111f16,0x00);
978
979 // enable sram clock
980 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
981 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
982 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
983 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
984
985 // select clock
986 // [3:0] : reg_ckg_frontend
987 // [0] : disable clock
988 // [1] : invert clock
989 // [3:2]: Select clock source
990 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
991 // 01: select clk_dmdadc (48 MHz, DVBT/C)
992 // 10: reserved
993 // 11: select DFT_CLK
994 // [7:4] : reg_ckg_tr
995 // [0] : disable clock
996 // [1] : invert clock
997 // [3:2]: Select clock source
998 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
999 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1000 // 10: reserved
1001 // 11: select DFT_CLK
1002 // [11:8]: reg_ckg_acifir
1003 // [0] : disable clock
1004 // [1] : invert clock
1005 // [3:2]: Select clock source
1006 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
1007 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1008 // 10: clk_vif_ssc_mux (43.2~50.82 MHz, VIF)
1009 // 11: select DFT_CLK
1010 // [15:12]: reg_ckg_frontend_d2
1011 // [0] : disable clock
1012 // [1] : invert clock
1013 // [3:2]: Select clock source
1014 // 00: clk_dmdadc_div2
1015 // 01: clk_dmplldiv17_div4(12.705 MHz)
1016 // 10: reserved
1017 // 11: select DFT_CLK
1018 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1019 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1020 // HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1021 // HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1022
1023 // enable isdbt clock
1024 // [2:0] : reg_ckg_isdbt_inner1x
1025 // [0] : disable clock
1026 // [1] : invert clock
1027 // [3:2]: Select clock source
1028 // 00: clk_dmplldiv10_div4(21.6MHz, ISDBT only)
1029 // 01: reserved
1030 // 10: reserved
1031 // 11: DFT_CLK
1032 // [6:4]: reg_ckg_isdbt_inner2x
1033 // [0] : disable clock
1034 // [1] : invert clock
1035 // [2]: Select clock source
1036 // 00: clk_dmplldiv10_div2(43.2MHz,ISDBT only)
1037 // 01: reserved
1038 // 10: reserved
1039 // 11: DFT_CLK
1040 // [10:8] : reg_ckg_isdbt_inner4x
1041 // [0] : disable clock
1042 // [1] : invert clock
1043 // [3:2]: Select clock source
1044 // 00: clk_dmplldiv10(86.4 MHz, DVBT only)
1045 // 01: reserved
1046 // 10: reserved
1047 // 11: DFT_CLK
1048 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1049 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1050 // HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1051 // HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1052
1053
1054 // enable isdbt outer clock
1055 // [3:0] : reg_ckg_isdbt_outer1x
1056 // [0] : disable clock
1057 // [1] : invert clock
1058 // [3:2]: Select clock source
1059 // 00: isdbt_clk6_lat (6 MHz)
1060 // 01: isdbt_clk8_lat (8 MHz)
1061 // 10: reserved
1062 // 11: DFT_CLK
1063 // [6:4]: reg_ckg_isdbt_outer4x
1064 // [0] : disable clock
1065 // [1] : invert clock
1066 // [3:2]: Select clock source
1067 // 00: isdbt_clk24_lat(24 MHz)
1068 // 01: isdbt_clk32_lat(32 MHz)
1069 // 10: reserved
1070 // 11: DFT_CLK
1071 // [10:8]: reg_ckg_isdbt_outer6x
1072 // [0] : disable clock
1073 // [1] : invert clock
1074 // [2] : Select clock source
1075 // 00: isdbt_clk36_lat(36 MHz)
1076 // 01: isdbt_clk48_lat(48 MHz)
1077 // 10: reserved
1078 // 11: DFT_CLK
1079 // [14:12]: reg_ckg_isdbt_outer12x
1080 // [0] : disable clock
1081 // [1] : invert clock
1082 // [2] : Select clock source
1083 // 00: isdbt_clk72_lat(72 MHz)
1084 // 01: isdbt_clk96_lat(96 MHz)
1085 // 10: reserved
1086 // 11: DFT_CLK
1087 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1088 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1089 // HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1090 // HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1091
1092 // Enable ISDBT clk_outer_div
1093 // reg_clk_isdbt_outer_div_en[0]
1094 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1095 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1096 // HAL_DMD_RIU_WriteByte(0x111f46,0x01);
1097
1098 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1099 // [1:0] : reg_ckg_dvbtc_sram4_isdbt_inner4x
1100 // [0]: disable clock
1101 // [1]: invert clock
1102 // [5:4] : reg_ckg_dvbtc_sram4_isdbt_outer6x
1103 // [0]: disable clock
1104 // [1]: invert clock
1105 // [9:8] : reg_ckg_adc1x_eq1x
1106 // [0]: disable clock
1107 // [1]: invert clock
1108 // [13:12] : reg_ckg_adc0p5x_eq0p5x
1109 // [0]: disable clock
1110 // [1]: invert clock
1111 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1112 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1113 HAL_DMD_RIU_WriteByte(0x111f49,0x00);
1114 HAL_DMD_RIU_WriteByte(0x111f48,0x00);
1115
1116 // [1:0] : reg_ckg_isdbt_outer6x_dvbt_inner1x
1117 // [0]: disable clock
1118 // [1]: invert clock
1119 // [5:4] : reg_ckg_isdbt_outer6x_dvbt_inner2x
1120 // [0]: disable clock
1121 // [1]: invert clock
1122 // [9:8] : reg_ckg_isdbt_outer6x_dvbt_outer2x
1123 // [0]: disable clock
1124 // [1]: invert clock
1125 // [13:12]: reg_ckg_isdbt_outer6x_dvbt_outer2x_c
1126 // [0]: disable clock
1127 // [1]: invert clock
1128 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1129 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1130 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
1131 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
1132
1133 // enable isdbt outer clock_rs
1134 // [7:4] : reg_ckg_isdbt_outer_rs
1135 // [0] : disable clock
1136 // [1] : invert clock
1137 // [3:2]: Select clock source
1138 // 00: isdbt_clk36_lat (36 MHz)
1139 // 01: isdbt_clk48_lat (48 MHz)
1140 // 10: clk_dmplldiv3_div4(72 MHz)
1141 // 11: isdbt_clk96_buf (96 MHz)
1142 // enable share isdbt &dvbt logic clock
1143 // [1:0] : reg_ckg_isdbt_inner2x_dvbt_inner2x
1144 // [0]: disable clock
1145 // [1]: invert clock
1146 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1147 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1148 // HAL_DMD_RIU_WriteByte(0x111f4c,0x00);
1149 HAL_DMD_RIU_WriteByte(0x111f4d,0x00);
1150 HAL_DMD_RIU_WriteByte(0x111f4c,0x10);
1151
1152 // enable vif clock
1153 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1154 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1155 // HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
1156 // HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
1157
1158 // enable DEMODE-DMA clock
1159 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1160 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1161 // HAL_DMD_RIU_WriteByte(0x111f21,0x00);
1162 // HAL_DMD_RIU_WriteByte(0x111f20,0x00);
1163
1164 // select clock
1165 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1166 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1167 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1168 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1169
1170
1171 // [15:12]: reg_ckg_dtmb_sram_dump
1172 // [0] : disable clock
1173 // [1] : invert clock
1174 // [3:2]: Select clock source
1175 // 00: dtmb_clk18_buf(16 MHz)
1176 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1177 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1178 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1179 HAL_DMD_RIU_WriteByte(0x111f71,0x18);
1180 HAL_DMD_RIU_WriteByte(0x111f70,0x81);
1181
1182 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1183 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1184
1185 HAL_DMD_RIU_WriteByte(0x111f4f,0x0c);
1186 HAL_DMD_RIU_WriteByte(0x111f4e,0x40);
1187
1188 HAL_DMD_RIU_WriteByte(0x111f51,0x48);
1189 HAL_DMD_RIU_WriteByte(0x111f50,0x44);
1190
1191 // Enable SAWLESS clock
1192 // reg_ckg_adcd_d2 @0x12[3:0]
1193 // reg_ckg_adcd_d4 @0x12[7:4]
1194 // reg_ckg_adcd_d6 @0x12[11:8]
1195 // reg_ckg_adcd_d12@0x12[15:12]
1196 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1197 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1198 // wriu 0x111f25 0x00
1199 // wriu 0x111f24 0x00
1200 // HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1201 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1202
1203 // ----------------------------------------------
1204 // start demod CLKGEN setting
1205 // ----------------------------------------------
1206
1207 // reg_allpad_in=0
1208 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1209 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1210 // HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1211 // HAL_DMD_RIU_WriteByte(0x101ea0,0x00);
1212
1213 // reg_ts1config=2
1214 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1215 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1216 //HAL_DMD_RIU_WriteByte(0x101eaf,0x10);
1217 //HAL_DMD_RIU_WriteByte(0x101eae,0x00);
1218
1219 // select DMD MCU
1220 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1221 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1222 // begin BY temp patch
1223 // HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1224 // HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1225 // end
1226 // HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1227
1228 // wriu 0x111f81 0x00
1229 // wriu 0x111f80 0x00
1230 // wriu 0x111f83 0x00
1231 // wriu 0x111f82 0x00
1232 // wriu 0x111f85 0x00
1233 // wriu 0x111f84 0x00
1234 // wriu 0x111f87 0x00
1235 // wriu 0x111f86 0x00
1236 // wriu 0x111f89 0x44
1237 // wriu 0x111f88 0x44
1238 // wriu 0x111f8b 0x00
1239 // wriu 0x111f8a 0x44
1240
1241 HAL_DMD_RIU_WriteByte(0x111f81,0x00);
1242 HAL_DMD_RIU_WriteByte(0x111f80,0x00);
1243
1244 HAL_DMD_RIU_WriteByte(0x111f83,0x00);
1245 HAL_DMD_RIU_WriteByte(0x111f82,0x00);
1246
1247 HAL_DMD_RIU_WriteByte(0x111f85,0x00);
1248 HAL_DMD_RIU_WriteByte(0x111f84,0x00);
1249
1250 HAL_DMD_RIU_WriteByte(0x111f87,0x00);
1251 HAL_DMD_RIU_WriteByte(0x111f86,0x00);
1252
1253 HAL_DMD_RIU_WriteByte(0x111f89,0x44);
1254 HAL_DMD_RIU_WriteByte(0x111f88,0x44);
1255
1256 HAL_DMD_RIU_WriteByte(0x111f8b,0x00);
1257 HAL_DMD_RIU_WriteByte(0x111f8a,0x44);
1258
1259 HAL_DMD_RIU_WriteByte(0x111f8d,0x18);
1260 HAL_DMD_RIU_WriteByte(0x111f8c,0x00);
1261
1262 HAL_DMD_RIU_WriteByte(0x111f8f,0x00);
1263 HAL_DMD_RIU_WriteByte(0x111f8e,0x40);
1264 // ----------------------------------------------
1265 // Turn TSP
1266 // ----------------------------------------------
1267 // turn on ts1_clk, ts0_clk
1268 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1269 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1270 // check TSP work or not
1271 //HAL_DMD_RIU_WriteByte(0x100b51,0x00);
1272 //HAL_DMD_RIU_WriteByte(0x100b50,0x00);
1273
1274 // stream2miu_en, activate rst_wadr
1275 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1276 // HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1277 // stream2miu_en, turn off rst_wadr
1278 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1279 // wriu 0x000e13 0x01
1280 //HAL_DMD_RIU_WriteByte(0x000e13,0x01);
1281 // udatatemp = HAL_DMD_RIU_ReadByte(0x000e13);
1282 // HAL_DMD_RIU_WriteByte(0x000e13, udatatemp&0xFB);//Set 0e12,Bit10=0,
1283 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1284 }
1285
1286 /***********************************************************************************
1287 Subject: Power on initialized function
1288 Function: INTERN_DVBT_Power_On_Initialization
1289 Parmeter:
1290 Return: MS_BOOL
1291 Remark:
1292 ************************************************************************************/
1293
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)1294 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
1295 {
1296 MS_U16 status = true;
1297 MS_U8 cData = 0;
1298 //U8 cal_done;
1299 ULOGD("DEMOD","INTERN_DVBT_Power_On_Initialization\n");
1300
1301 #if defined(PWS_ENABLE)
1302 Mapi_PWS_Stop_VDMCU();
1303 #endif
1304
1305 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
1306 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1307 //// Firmware download //////////
1308 ULOGD("DEMOD","INTERN_DVBT Load DSP...\n");
1309 //MsOS_DelayTask(100);
1310
1311
1312 {
1313 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1314 {
1315 ULOGE("DEMOD","DVB-T Load DSP Code Fail\n");
1316 return FALSE;
1317 }
1318 else
1319 {
1320 ULOGD("DEMOD","DVB-T Load DSP Code OK\n");
1321 }
1322 }
1323
1324
1325 //// MCU Reset //////////
1326 ULOGD("DEMOD","INTERN_DVBT Reset...\n");
1327 if (INTERN_DVBT_Reset() == FALSE)
1328 {
1329 ULOGE("DEMOD","Fail\n");
1330 return FALSE;
1331 }
1332 else
1333 {
1334 ULOGD("DEMOD","OK\n");
1335 }
1336
1337 // reset FDP
1338 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1339 // SRAM setting, DVB-T use it.
1340 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1341 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1342 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1343
1344 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1345 return status;
1346 }
1347
1348 /************************************************************************************************
1349 Subject: Driving control
1350 Function: INTERN_DVBT_Driving_Control
1351 Parmeter: bInversionEnable : TRUE For High
1352 Return: void
1353 Remark:
1354 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1355 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1356 {
1357 MS_U8 u8Temp;
1358
1359 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1360
1361 if (bEnable)
1362 {
1363 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1364 }
1365 else
1366 {
1367 u8Temp = u8Temp & (~0x01);
1368 }
1369
1370 ULOGD("DEMOD","---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp);
1371 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1372 }
1373 /************************************************************************************************
1374 Subject: Clk Inversion control
1375 Function: INTERN_DVBT_Clk_Inversion_Control
1376 Parmeter: bInversionEnable : TRUE For Inversion Action
1377 Return: void
1378 Remark:
1379 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1380 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1381 {
1382 MS_U8 u8Temp;
1383
1384 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1385
1386 if (bInversionEnable)
1387 {
1388 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1389 }
1390 else
1391 {
1392 u8Temp = u8Temp & (~0x02);
1393 }
1394
1395 ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp);
1396 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1397 }
1398 /************************************************************************************************
1399 Subject: Transport stream serial/parallel control
1400 Function: INTERN_DVBT_Serial_Control
1401 Parmeter: bEnable : TRUE For serial
1402 Return: MS_BOOL :
1403 Remark:
1404 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1405 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1406 {
1407 MS_U8 status = true;
1408 MS_U8 temp_val;
1409 ULOGD("DEMOD"," @INTERN_DVBT_ts... u8TSClk=%d\n",u8TSClk);
1410
1411 return status;
1412 if (u8TSClk == 0xFF) u8TSClk=0x13;
1413 if (bEnable) //Serial mode for TS pad
1414 {
1415 // serial
1416 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1417 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1418
1419 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1420 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1421 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1422
1423 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1424 temp_val|=0x04;
1425 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1426 #else
1427 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1428 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1429 temp_val|=0x07;
1430 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1431 #endif
1432 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1433 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1434
1435 //// INTERN_DVBT TS Control: Serial //////////
1436 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1437
1438 gsCmdPacket.param[0] = TS_SERIAL;
1439 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1440 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1441 #else
1442 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1443 #endif
1444 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1445 }
1446 else
1447 {
1448 //parallel
1449 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1450 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1451
1452 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1453 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1454 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1455 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1456 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1457 temp_val|=0x05;
1458 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1459 #else
1460 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1461 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1462 temp_val|=0x07;
1463 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1464 #endif
1465
1466 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1467 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1468
1469 //// INTERN_DVBT TS Control: Parallel //////////
1470 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1471
1472 gsCmdPacket.param[0] = TS_PARALLEL;
1473 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1474 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1475 #else
1476 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1477 #endif
1478 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1479 }
1480
1481 ULOGD("DEMOD","---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] );
1482
1483 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1484 return status;
1485 }
1486
1487 /************************************************************************************************
1488 Subject: TS1 output control
1489 Function: INTERN_DVBT_PAD_TS1_Enable
1490 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1491 Return: void
1492 Remark:
1493 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1494 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1495 {
1496 ULOGD("DEMOD"," @INTERN_DVBT_TS1_Enable... \n");
1497
1498 if(flag) // PAD_TS1 Enable TS CLK PAD
1499 {
1500 //ULOGD("DEMOD","=== TS1_Enable ===\n");
1501 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1502 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1503 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1504 }
1505 else // PAD_TS1 Disable TS CLK PAD
1506 {
1507 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1508 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1509 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1510 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1511 }
1512 }
1513
1514 /************************************************************************************************
1515 Subject: channel change config
1516 Function: INTERN_DVBT_Config
1517 Parmeter: BW: bandwidth
1518 Return: MS_BOOL :
1519 Remark:
1520 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1521 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1522 {
1523 MS_U8 bandwidth;
1524 MS_U8 status = true;
1525
1526 //ULOGD("DEMOD"," @INTERN_DVBT_config %d %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap);
1527 //ULOGD("DEMOD","INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime());
1528
1529 if (u8TSClk == 0xFF) u8TSClk=0x13;
1530 switch(BW)
1531 {
1532 case E_DMD_RF_CH_BAND_6MHz:
1533 bandwidth = 1;
1534 break;
1535 case E_DMD_RF_CH_BAND_7MHz:
1536 bandwidth = 2;
1537 break;
1538 case E_DMD_RF_CH_BAND_8MHz:
1539 default:
1540 bandwidth = 3;
1541 break;
1542 }
1543
1544 status &= INTERN_DVBT_Reset();
1545
1546 // BW mode
1547 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1548 // TS mode
1549 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1550 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1551 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1552 // Hierarchy mode
1553 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1554 // FC
1555 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1557 // FS
1558 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1559 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1560 // IQSwap
1561 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1562
1563 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1564 // Fif
1565 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1566 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1567
1568 return status;
1569 }
1570 /************************************************************************************************
1571 Subject: enable hw to lock channel
1572 Function: INTERN_DVBT_Active
1573 Parmeter: bEnable
1574 Return: MS_BOOL
1575 Remark:
1576 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1577 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1578 {
1579 MS_U8 status = true;
1580 MS_U8 reg_frz = 0, reg_frza = 0;
1581
1582 ULOGD("DEMOD"," @INTERN_DVBT_active\n");
1583
1584 //// INTERN_DVBT Finite State Machine on/off //////////
1585 #if 0
1586 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1587
1588 gsCmdPacket.param[0] = (MS_U8)bEnable;
1589 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1590 #else
1591 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1592 #endif
1593 INTERN_DVBT_SignalQualityReset();
1594
1595 #if (1)//vesion check here
1596 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBT_N_PARAM_VERSION, ®_frz);
1597 ULOGD("DEMOD","##########DVBT------>(Driver) = 0x%x #########\n",reg_frz);
1598 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBT_N_OP_RFAGC_EN, ®_frza);
1599 ULOGD("DEMOD","##########DVBT------>(FW) = 0x%x #########\n",reg_frza);
1600 if (reg_frz < reg_frza)
1601 {
1602 while(1)
1603 ULOGD("DEMOD","##########--------->Abnormal case, please update demod utopia driver version!!! #########\n");
1604 }
1605 else{
1606 ULOGD("DEMOD","##########--------->Normal case! #########\n");
1607 }
1608 #endif
1609
1610 return status;
1611 }
1612 /************************************************************************************************
1613 Subject: Return lock status
1614 Function: INTERN_DVBT_Lock
1615 Parmeter: eStatus :
1616 Return: MS_BOOL
1617 Remark:
1618 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1619 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1620 {
1621 float fBER=0.0f;
1622
1623 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1624 {
1625 if (bFECLock == FALSE)
1626 {
1627 u32FecFirstLockTime = MsOS_GetSystemTime();
1628 ULOGD("DEMOD","++++++++[DEMOD]dvbt lock\n");
1629 }
1630
1631 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1632 {
1633 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1634 {
1635 if(fViterbiBerFiltered <= 0.0)
1636 fViterbiBerFiltered = fBER;
1637 else
1638 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1639 }
1640 ULOGD("DEMOD","[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered);
1641 }
1642 u32FecLastLockTime = MsOS_GetSystemTime();
1643 bFECLock = TRUE;
1644 return E_DMD_LOCK;
1645 }
1646 else
1647 {
1648 INTERN_DVBT_SignalQualityReset();
1649 if (bFECLock == TRUE)
1650 {
1651 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1652 {
1653 return E_DMD_LOCK;
1654 }
1655 }
1656 bFECLock = FALSE;
1657 }
1658
1659 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1660 {
1661 ULOGD("DEMOD","==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1662 return E_DMD_UNLOCK;
1663 }
1664
1665 if(!bTPSLock)
1666 {
1667 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1668 {
1669 ULOGD("DEMOD","==> INTERN_DVBT_Lock -- TPSLock \n");
1670 bTPSLock = TRUE;
1671 }
1672 }
1673 if(bTPSLock)
1674 {
1675 //ULOGD("DEMOD","TPSLock %ld\n",MsOS_GetSystemTime());
1676 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1677 {
1678 return E_DMD_CHECKING;
1679 }
1680 }
1681 else
1682 {
1683 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1684 {
1685 return E_DMD_CHECKING;
1686 }
1687 }
1688 return E_DMD_UNLOCK;
1689
1690 }
1691
1692
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1693 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1694 {
1695 MS_U16 u16Address = 0;
1696 MS_U8 cData = 0;
1697 MS_U8 cBitMask = 0;
1698
1699 switch( eStatus )
1700 {
1701 case E_DMD_COFDM_FEC_LOCK:
1702 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1703
1704 if (cData == 0x0B)
1705 {
1706 return TRUE;
1707 }
1708 else
1709 {
1710 return FALSE; // continuously un-lock
1711 }
1712 break;
1713
1714 case E_DMD_COFDM_PSYNC_LOCK:
1715 u16Address = 0x232C; //FEC: P-sync Lock,
1716 cBitMask = BIT(1);
1717 break;
1718
1719 case E_DMD_COFDM_TPS_LOCK:
1720 u16Address = 0x2222; //TPS HW Lock,
1721 cBitMask = BIT(1);
1722 break;
1723
1724 case E_DMD_COFDM_DCR_LOCK:
1725 u16Address = 0x2737; //DCR Lock,
1726 cBitMask = BIT(0);
1727 break;
1728
1729 case E_DMD_COFDM_AGC_LOCK:
1730 u16Address = 0x271D; //AGC Lock,
1731 cBitMask = BIT(0);
1732 break;
1733
1734 case E_DMD_COFDM_MODE_DET:
1735 u16Address = 0x24CF; //Mode CP Detect,
1736 cBitMask = BIT(4);
1737 break;
1738
1739 case E_DMD_COFDM_TPS_EVER_LOCK:
1740 u16Address = 0x20C0; //TPS Ever Lock,
1741 cBitMask = BIT(3);
1742 break;
1743
1744 case E_DMD_COFDM_NO_CHANNEL:
1745 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1746 cBitMask = BIT(7);
1747 break;
1748
1749 default:
1750 return FALSE;
1751 }
1752
1753 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1754 return FALSE;
1755
1756 if ((cData & cBitMask) == cBitMask)
1757 {
1758 return TRUE;
1759 }
1760
1761 return FALSE;
1762
1763 }
1764
1765 /****************************************************************************
1766 Subject: To get the Post viterbi BER
1767 Function: INTERN_DVBT_GetPostViterbiBer
1768 Parmeter: Quility
1769 Return: E_RESULT_SUCCESS
1770 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1771 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1772 We will not read the Period, and have the "/256/8"
1773 *****************************************************************************/
INTERN_DVBT_GetPostViterbiBer(float * ber)1774 MS_BOOL INTERN_DVBT_GetPostViterbiBer(float *ber)
1775 {
1776 MS_BOOL status = true;
1777 MS_U8 reg=0, reg_frz=0;
1778 MS_U16 BitErrPeriod;
1779 MS_U32 BitErr;
1780 MS_U16 PktErr;
1781
1782 /////////// Post-Viterbi BER /////////////
1783
1784 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1785 {
1786 *ber = (float)-1.0;
1787 return false;
1788 }
1789 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1790 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1791 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1792
1793 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1794 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1796 BitErrPeriod = reg;
1797
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1799 BitErrPeriod = (BitErrPeriod << 8)|reg;
1800
1801 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1802 // 0x6b [15:8] reg_bit_err_num_15_8
1803 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1804 // 0x6d [15:8] reg_bit_err_num_31_24
1805 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1806 BitErr = reg;
1807
1808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1809 BitErr = (BitErr << 8)|reg;
1810
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1812 BitErr = (BitErr << 8)|reg;
1813
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1815 BitErr = (BitErr << 8)|reg;
1816
1817 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1818 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1819 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1820 PktErr = reg;
1821
1822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1823 PktErr = (PktErr << 8)|reg;
1824
1825 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1826 reg_frz=reg_frz&(~0x03);
1827 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1828
1829 if (BitErrPeriod == 0 ) //protect 0
1830 BitErrPeriod = 1;
1831
1832 if (BitErr <=0 )
1833 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1834 else
1835 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1836
1837
1838 DBG_GET_SIGNAL(ULOGD("DEMOD","INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1839 DBG_GET_SIGNAL(ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1840
1841 return status;
1842 }
1843
1844 /****************************************************************************
1845 Subject: To get the Pre viterbi BER
1846 Function: INTERN_DVBT_GetPreViterbiBer
1847 Parmeter: ber
1848 Return: E_RESULT_SUCCESS
1849 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1850 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1851 We will not read the Period, and have the "/256/8"
1852 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1853 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1854 {
1855 MS_U8 status = true;
1856 MS_U8 reg=0, reg_frz=0;
1857 MS_U16 BitErrPeriod;
1858 MS_U32 BitErr;
1859 MS_BOOL BEROver;
1860
1861 // bank 7 0x10 [3] reg_rd_freezeber
1862 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1863 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1864
1865 // bank 7 0x16 [7:0] reg_ber_timerl
1866 // [15:8] reg_ber_timerm
1867 // bank 7 0x18 [5:0] reg_ber_timerh
1868 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1869 BitErrPeriod = reg&0x3f;
1870
1871 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1872 BitErrPeriod = (BitErrPeriod << 8)|reg;
1873
1874 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1875 BitErrPeriod = (BitErrPeriod << 8)|reg;
1876
1877 // bank 7 0x1e [7:0] reg_ber_7_0
1878 // [15:8] reg_ber_15_8
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1880 BitErr = reg;
1881
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1883 BitErr = (BitErr << 8)|reg;
1884
1885 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1887 if (reg & 0x10)
1888 BEROver = true;
1889 else
1890 BEROver = false;
1891
1892 if (BitErrPeriod ==0 )//protect 0
1893 BitErrPeriod=1;
1894
1895 if (BEROver)
1896 {
1897 *ber = 1;
1898 ULOGD("DEMOD","BER is over\n");
1899 }
1900 else
1901 {
1902 if (BitErr <=0 )
1903 *ber=0.5 / (float)(BitErrPeriod * 256);
1904 else
1905 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1906 }
1907
1908 // bank 7 0x10 [3] reg_rd_freezeber
1909 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1910
1911 return status;
1912 }
1913
1914 /****************************************************************************
1915 Subject: To get the Packet error
1916 Function: INTERN_DVBT_GetPacketErr
1917 Parmeter: pktErr
1918 Return: E_RESULT_SUCCESS
1919 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1920 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1921 We will not read the Period, and have the "/256/8"
1922 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1923 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1924 {
1925 MS_BOOL status = true;
1926 MS_U8 reg = 0, reg_frz = 0;
1927 MS_U16 PktErr;
1928
1929 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1930 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1931 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1932
1933 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1934 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1935 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1936 PktErr = reg;
1937
1938 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1939 PktErr = (PktErr << 8)|reg;
1940
1941 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1942 reg_frz=reg_frz&(~0x03);
1943 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1944
1945 DBG_GET_SIGNAL(ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1946
1947 *u16PktErr = PktErr;
1948
1949 return status;
1950 }
1951
1952 /****************************************************************************
1953 Subject: To get the DVBT parameter
1954 Function: INTERN_DVBT_Get_TPS_Info
1955 Parmeter: point to return parameter
1956 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1957 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1958 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1959 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1960 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1961 FFT ( b14) : 0~1 => 2K, 8K
1962 Priority(bit 15) : 0~1=> HP,LP
1963 Return: TRUE
1964 FALSE
1965 Remark: The TPS parameters will be available after TPS lock
1966 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1967 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1968 {
1969 MS_U8 u8Temp;
1970
1971 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1972 return FALSE;
1973
1974 if ((u8Temp& 0x02) != 0x02)
1975 {
1976 return FALSE; //TPS unlock
1977 }
1978 else
1979 {
1980 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1981 return FALSE;
1982
1983 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1984 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1985
1986 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1987 return FALSE;
1988
1989 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1990 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1991
1992 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1993 return FALSE;
1994
1995 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
1996 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
1997
1998 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
1999 return FALSE;
2000
2001 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
2002
2003 }
2004 return TRUE;
2005 }
2006
2007
2008 /****************************************************************************
2009 Subject: Read the signal to noise ratio (SNR)
2010 Function: INTERN_DVBT_GetSNR
2011 Parmeter: None
2012 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2013 Remark:
2014 *****************************************************************************/
INTERN_DVBT_GetSNR(void)2015 float INTERN_DVBT_GetSNR (void)
2016 {
2017 MS_U8 status = true;
2018 MS_U8 reg=0, reg_frz=0;
2019 MS_U32 noise_power;
2020 float snr;
2021
2022 // bank 6 0xfe [0] reg_fdp_freeze
2023 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2024 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2025
2026 // bank 6 0xff [0] reg_fdp_load
2027 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2028
2029 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
2030 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
2031 noise_power = reg & 0x07;
2032
2033 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
2034 noise_power = (noise_power << 8)|reg;
2035
2036 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
2037 noise_power = (noise_power << 8)|reg;
2038
2039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
2040 noise_power = (noise_power << 8)|reg;
2041
2042 // bank 6 0x26 [5:4] reg_transmission_mode
2043 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2044
2045 // bank 6 0xfe [0] reg_fdp_freeze
2046 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
2047
2048 // bank 6 0xff [0] reg_fdp_load
2049 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2050
2051 #if 1 // copy from DEMOD2\mxlib\hal\miami\demod\halDMD_INTERN_DVBT.c
2052 noise_power = noise_power/2;
2053 noise_power /=1280;
2054 // noisepower = (rand()%256)*256;
2055 if (noise_power==0)//protect value 0
2056 noise_power=1;
2057
2058 #ifdef MSOS_TYPE_LINUX
2059 snr = 10*log10f((float)noise_power);
2060 #else
2061 snr = 10*Log10Approx((float)noise_power);
2062 #endif
2063
2064
2065 #else
2066 noise_power = noise_power/2;
2067
2068 if ((reg&0x30)==0x00) //2K
2069 {
2070 if (noise_power<1512)
2071 snr = 0;
2072 else
2073 #ifdef MSOS_TYPE_LINUX
2074 snr = 10*log10f((float)noise_power/1512);
2075 #else
2076 snr = 10*Log10Approx((float)noise_power/1512);
2077 #endif
2078 }
2079 //else if ((reg&0x30)==0x10)//8K
2080 else
2081 {
2082 if (noise_power<6048)
2083 snr = 0;
2084 else
2085 #ifdef MSOS_TYPE_LINUX
2086 snr = 10*log10f((float)noise_power/6048);
2087 #else
2088 snr = 10*Log10Approx((float)noise_power/6048);
2089 #endif
2090 }
2091 /* ignore 4K
2092 else //4K
2093 {
2094 if (noise_power<3024)
2095 snr = 0;
2096 else
2097 snr = 10*Log10Approx(noise_power/3024);
2098 }
2099 */
2100 #endif
2101
2102 if (status == true)
2103 return snr;
2104 else
2105 return -1;
2106
2107 }
2108
2109 /****************************************************************************
2110 Subject: To check if Hierarchy on
2111 Function: INTERN_DVBT_Is_HierarchyOn
2112 Parmeter:
2113 Return: BOOLEAN
2114 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)2115 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
2116 {
2117 MS_U16 u16_tmp;
2118
2119 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
2120 return FALSE;
2121 //ULOGD("DEMOD","u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
2122 if(u16_tmp&0x38)
2123 {
2124 return TRUE;
2125 }
2126 return FALSE;
2127 }
2128
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2129 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2130 {
2131 MS_U8 status = true;
2132 float ch_power_db = 0.0f;
2133 float ch_power_ref = 11.0f;
2134 float ch_power_rel = 0.0f;
2135 MS_U8 u8_index = 0;
2136 MS_U16 tps_info_qam,tps_info_cr;
2137
2138 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2139 {
2140 *strength = 0;
2141 return TRUE;
2142 }
2143 //ULOGD("DEMOD","INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime());
2144
2145 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
2146 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
2147 /* Actually, it's more reasonable, that signal level depended on cable input power level
2148 * thougth the signal isn't dvb-t signal.
2149 */
2150
2151 // use pointer of IFAGC table to identify
2152 // case 1: RFAGC from SAR, IFAGC controlled by demod
2153 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2154 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2155 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
2156 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2157 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2158 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
2159 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
2160
2161
2162 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
2163 ULOGE("DEMOD","[dvbt]TPS qam parameter retrieve failure\n");
2164
2165 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
2166 ULOGE("DEMOD","[dvbt]TPS cr parameter retrieve failure\n");
2167
2168
2169 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2170 {
2171 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
2172 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
2173 {
2174 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2175 break;
2176 }
2177 else
2178 {
2179 u8_index++;
2180 }
2181 }
2182
2183 if (ch_power_ref > 10.0f)
2184 *strength = 0;
2185 else
2186 {
2187 ch_power_rel = ch_power_db - ch_power_ref;
2188
2189 if ( ch_power_rel < -15.0f )
2190 {
2191 *strength = 0;
2192 }
2193 else if ( ch_power_rel < 0.0f )
2194 {
2195 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2196 }
2197 else if ( ch_power_rel < 20 )
2198 {
2199 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2200 }
2201 else if ( ch_power_rel < 35.0f )
2202 {
2203 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2204 }
2205 else
2206 {
2207 *strength = 100;
2208 }
2209 }
2210
2211 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2212 {
2213 *strength = 0;
2214 return TRUE;
2215 }
2216
2217 DBG_GET_SIGNAL(ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2218 DBG_GET_SIGNAL(ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength));
2219
2220 return status;
2221 }
2222
2223 /****************************************************************************
2224 Subject: To get the DVT Signal quility
2225 Function: INTERN_DVBT_GetSignalQuality
2226 Parmeter: Quility
2227 Return: E_RESULT_SUCCESS
2228 E_RESULT_FAILURE
2229 Remark: Here we have 4 level range
2230 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2231 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2232 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2233 <4>.4th Range => Quality <10
2234 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2235 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2236 {
2237 float ber_sqi;
2238 float fber;
2239 float cn_rec = 0;
2240 float cn_nordig_p1 = 0;
2241 float cn_rel = 0;
2242
2243 MS_U8 status = true;
2244 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
2245 MS_U16 u16_tmp;
2246
2247 //ULOGD("DEMOD","INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime());
2248
2249 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
2250 {
2251
2252 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2253 {
2254 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2255 }
2256 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
2257 if(fViterbiBerFiltered<= 0.0)
2258 {
2259 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
2260 {
2261 ULOGE("DEMOD","GetPostViterbiBer Fail!\n");
2262 return FALSE;
2263 }
2264 fViterbiBerFiltered = fber;
2265 }
2266 else
2267 {
2268 fber = fViterbiBerFiltered;
2269 }
2270
2271 if (fber > 1.0E-3)
2272 ber_sqi = 0.0;
2273 else if (fber > 8.5E-7)
2274 #ifdef MSOS_TYPE_LINUX
2275 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2276 #else
2277 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2278 #endif
2279 else
2280 ber_sqi = 100.0;
2281
2282 cn_rec = INTERN_DVBT_GetSNR();
2283
2284 if (cn_rec == -1) //get SNR return fail
2285 status = false;
2286
2287 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2288 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2289 tps_cnstl = 0xff;
2290 tps_cr = 0xff;
2291 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
2292 tps_cnstl = (MS_U8)u16_tmp&0x07;
2293 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
2294 tps_cr = (MS_U8)u16_tmp&0x07;
2295
2296 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
2297 {
2298 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
2299 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
2300 {
2301 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
2302 break;
2303 }
2304 }
2305
2306 // 0,5, snr offset
2307 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
2308
2309 // patch....
2310 // Noridg SQI,
2311 // 64QAM, CR34, GI14, SNR 22dB.
2312 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
2313 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
2314 {
2315 cn_rel += 1.5f;
2316 }
2317
2318 if (cn_rel < -7.0f)
2319 {
2320 *quality = 0;
2321 }
2322 else if (cn_rel < 3.0)
2323 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
2324 else
2325 *quality = (MS_U16)ber_sqi;
2326 }
2327 else
2328 {
2329 *quality = 0;
2330 }
2331
2332 DBG_GET_SIGNAL(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2333 DBG_GET_SIGNAL(ULOGD("DEMOD","BER = %8.3e\n", fber));
2334 DBG_GET_SIGNAL(ULOGD("DEMOD","Signal Quility = %d\n", *quality));
2335 return status;
2336 }
2337
2338 /****************************************************************************
2339 Subject: To get the Cell ID
2340 Function: INTERN_DVBT_Get_CELL_ID
2341 Parmeter: point to return parameter cell_id
2342
2343 Return: TRUE
2344 FALSE
2345 Remark:
2346 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2347 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2348 {
2349 MS_U8 status = true;
2350 MS_U8 value1=0;
2351 MS_U8 value2=0;
2352
2353 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2354 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2355
2356 *cell_id = ((MS_U16)value1<<8)|value2;
2357 return status;
2358 }
2359 /*
2360 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2361 {
2362 #define SQI_LOOP_NUM 50
2363 U8 inn = 0;
2364 WORD sqi = 0;
2365 WORD ave_sqi = 0;
2366 WORD ave_num = 0;
2367 while(inn++<SQI_LOOP_NUM)
2368 {
2369 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2370 {
2371 ULOGD("DEMOD","[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2372 ave_sqi+=sqi;
2373 ave_num++;
2374 }
2375 MsOS_DelayTask(50);
2376 }
2377
2378 if(ave_num != 0 )
2379 *quality = ave_sqi/ave_num;
2380
2381 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2382 }
2383 */
2384 /****************************************************************************
2385 Subject: To get the DVBT Carrier Freq Offset
2386 Function: INTERN_DVBT_Get_FreqOffset
2387 Parmeter: Frequency offset (in KHz), bandwidth
2388 Return: E_RESULT_SUCCESS
2389 E_RESULT_FAILURE
2390 Remark:
2391 *****************************************************************************/
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2392 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2393 {
2394 float N, FreqB;
2395 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2396 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2397 MS_U8 reg_frz=0, reg=0;
2398 MS_U8 status;
2399
2400 FreqB = (float)u8BW * 8 / 7;
2401
2402 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2403
2404 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2405
2406 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2407 RegCfoTd = reg;
2408
2409 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2410 RegCfoTd = (RegCfoTd << 8)|reg;
2411
2412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2413 RegCfoTd = (RegCfoTd << 8)|reg;
2414
2415 FreqCfoTd = (float)RegCfoTd;
2416
2417 if (RegCfoTd & 0x800000)
2418 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2419
2420 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2421
2422 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2423
2424 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2425 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2426
2427 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2428
2429 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2430 RegCfoFd = reg;
2431
2432 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2433 RegCfoFd = (RegCfoFd << 8)|reg;
2434
2435 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2436 RegCfoFd = (RegCfoFd << 8)|reg;
2437
2438 FreqCfoFd = (float)RegCfoFd;
2439
2440 if (RegCfoFd & 0x800000)
2441 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2442
2443 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2444
2445 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2446 RegIcfo = reg & 0x07;
2447
2448 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2449 RegIcfo = (RegIcfo << 8)|reg;
2450
2451 FreqIcfo = (float)RegIcfo;
2452
2453 if (RegIcfo & 0x400)
2454 FreqIcfo = FreqIcfo - (float)0x800;
2455
2456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2457 reg = reg & 0x30;
2458
2459 switch (reg)
2460 {
2461 case 0x00: N = 2048; break;
2462 case 0x20: N = 4096; break;
2463 case 0x10:
2464 default: N = 8192; break;
2465 }
2466
2467 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2468 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2469 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2470 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2471 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2472 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2473 // DBG_GET_SIGNAL(ULOGD("DEMOD","FCFO = %f\n", FreqCfoFd));
2474 // DBG_GET_SIGNAL(ULOGD("DEMOD","TCFO = %f\n", FreqCfoTd));
2475 // DBG_GET_SIGNAL(ULOGD("DEMOD","ICFO = %f\n", FreqIcfo));
2476 DBG_GET_SIGNAL(ULOGD("DEMOD","CFOE = %f\n", *pFreqOff));
2477
2478 if (status == TRUE)
2479 return TRUE;
2480 else
2481 return FALSE;
2482 }
2483
2484
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2485 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2486 {
2487
2488 bPowerOn = bPowerOn;
2489 }
2490
INTERN_DVBT_Power_Save(void)2491 MS_BOOL INTERN_DVBT_Power_Save(void)
2492 {
2493
2494 return TRUE;
2495 }
2496
2497 /****************************************************************************
2498 Subject: To get the DVBT constellation parameter
2499 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2500 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2501 Return: TRUE
2502 FALSE
2503 Remark: The TPS parameters will be available after TPS lock
2504 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2505 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2506 {
2507 MS_U8 tps_param;
2508
2509 //@@++ Arki 20100125
2510 if (eSignalType == TS_MODUL_MODE)
2511 {
2512 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2513 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2514 }
2515
2516 if (eSignalType == TS_CODE_RATE)
2517 {
2518 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2519 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2520 }
2521
2522 if (eSignalType == TS_GUARD_INTERVAL)
2523 {
2524 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2525 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2526 }
2527
2528 if (eSignalType == TS_FFX_VALUE)
2529 {
2530 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2531 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2532 }
2533 //@@-- Arki 20100125
2534 return TRUE;
2535 }
2536
INTERN_DVBT_Version(MS_U16 * ver)2537 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2538 {
2539
2540 MS_U8 status = true;
2541 MS_U8 tmp = 0;
2542 MS_U16 u16_INTERN_DVBT_Version;
2543
2544 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2545 u16_INTERN_DVBT_Version = tmp;
2546 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2547 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2548 *ver = u16_INTERN_DVBT_Version;
2549
2550 return status;
2551 }
2552
INTERN_DVBT_Version_minor(MS_U8 * ver2)2553 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2554 {
2555
2556 MS_U8 status = true;
2557
2558 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2559
2560 return status;
2561 }
2562
2563
INTERN_DVBT_Show_Demod_Version(void)2564 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2565 {
2566
2567 MS_BOOL status = true;
2568 MS_U16 u16_INTERN_DVBT_Version;
2569 MS_U8 u8_minor_ver = 0;
2570
2571 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2572 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2573 ULOGD("DEMOD","[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2574
2575 return status;
2576 }
2577
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2578 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2579 {
2580 MS_U8 u8_index = 0;
2581 MS_BOOL bRet = false;
2582
2583 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2584 {
2585 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2586 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2587 {
2588 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2589 bRet = true;
2590 break;
2591 }
2592 else
2593 {
2594 u8_index++;
2595 }
2596 }
2597 return bRet;
2598 }
2599
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2600 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2601 {
2602 MS_U8 u8_index = 0;
2603 MS_BOOL bRet = false;
2604
2605 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2606 {
2607 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2608 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2609 {
2610 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2611 bRet = true;
2612 break;
2613 }
2614 else
2615 {
2616 u8_index++;
2617 }
2618 }
2619 return bRet;
2620 }
2621
2622
2623 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2624 void INTERN_DVBT_get_demod_state(MS_U8* state)
2625 {
2626 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2627 return;
2628 }
2629
INTERN_DVBT_Show_ChannelLength(void)2630 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2631 {
2632 MS_U8 status = true;
2633 MS_U8 tmp = 0;
2634 MS_U16 len = 0;
2635 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2636 len = tmp;
2637 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2638 len = (len<<8)|tmp;
2639 ULOGD("DEMOD","[dvbt]Hw_channel=%d\n",len);
2640 return status;
2641 }
2642
INTERN_DVBT_Show_SW_ChannelLength(void)2643 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2644 {
2645 MS_U8 status = true;
2646 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2647 MS_U16 sw_len = 0;
2648 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2649 sw_len = tmp;
2650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2651 sw_len = (sw_len<<8)|tmp;
2652 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2653 peak_num = tmp;
2654 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2655 insideGI = tmp&0x01;
2656 stoptracking = (tmp&0x02)>>1;
2657 flag_short_echo = (tmp&0x0C)>>2;
2658 fsa_mode = (tmp&0x30)>>4;
2659
2660 ULOGD("DEMOD","[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2661 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2662
2663 return status;
2664 }
2665
INTERN_DVBT_Show_ACI_CI(void)2666 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2667 {
2668
2669 #define BIT4 0x10
2670 MS_U8 status = true;
2671 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2672
2673 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2674 digACI = (tmp&BIT4)>>4;
2675
2676 // get flag_CI
2677 // 0: No interference
2678 // 1: CCI
2679 // 2: in-band ACI
2680 // 3: N+1 ACI
2681 // flag_ci = (tmp&0xc0)>>6;
2682 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2683 flag_CI = (tmp&0xC0)>>6;
2684 td_coef = (tmp&0x0C)>>2;
2685
2686 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2687
2688 ULOGD("DEMOD","[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2689
2690 return status;
2691 }
2692
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2693 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2694 {
2695 MS_U8 status = true;
2696 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2697 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2698 fd = tmp;
2699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2700 ch_len = tmp;
2701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2702 snr_sel = (tmp>>4)&0x03;
2703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2704 pertone_num = tmp;
2705
2706 ULOGD("DEMOD","[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2707
2708 return status;
2709 }
2710
INTERN_DVBT_Get_CFO(void)2711 MS_BOOL INTERN_DVBT_Get_CFO(void)
2712 {
2713
2714 float N = 0, FreqB = 0;
2715 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2716 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2717 MS_U8 reg_frz = 0, reg = 0;
2718 MS_U8 status = 0;
2719 MS_U8 u8BW = 8;
2720
2721 FreqB = (float)u8BW * 8 / 7;
2722
2723 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2724
2725 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2726
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2728 RegCfoTd = reg;
2729
2730 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2731 RegCfoTd = (RegCfoTd << 8)|reg;
2732
2733 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2734 RegCfoTd = (RegCfoTd << 8)|reg;
2735
2736 FreqCfoTd = (float)RegCfoTd;
2737
2738 if (RegCfoTd & 0x800000)
2739 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2740
2741 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2742
2743 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2744
2745 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2746 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2747
2748 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2749
2750 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2751 RegCfoFd = reg;
2752
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2754 RegCfoFd = (RegCfoFd << 8)|reg;
2755
2756 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2757 RegCfoFd = (RegCfoFd << 8)|reg;
2758
2759 FreqCfoFd = (float)RegCfoFd;
2760
2761 if (RegCfoFd & 0x800000)
2762 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2763
2764 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2765
2766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2767 RegIcfo = reg & 0x07;
2768
2769 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2770 RegIcfo = (RegIcfo << 8)|reg;
2771
2772 FreqIcfo = (float)RegIcfo;
2773
2774 if (RegIcfo & 0x400)
2775 FreqIcfo = FreqIcfo - (float)0x800;
2776
2777 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2778 reg = reg & 0x30;
2779
2780 switch (reg)
2781 {
2782 case 0x00: N = 2048; break;
2783 case 0x20: N = 4096; break;
2784 case 0x10:
2785 default: N = 8192; break;
2786 }
2787
2788 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2790 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2791 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2792 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2793
2794 ULOGD("DEMOD","[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2795
2796 return status;
2797
2798 }
INTERN_DVBT_Get_SFO(void)2799 MS_BOOL INTERN_DVBT_Get_SFO(void)
2800 {
2801 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2802 MS_BOOL status = true;
2803 MS_U8 reg = 0;
2804 float FreqB = 9.143, FreqS = 45.473; //20.48
2805 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2806 float sfo_value = 0;
2807
2808 // get Reg_TDP_SFO,
2809 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2810 Reg_TDP_SFO = reg;
2811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2812 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2813 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2814 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2815
2816 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2817
2818 // get Reg_FDP_SFO,
2819 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2820 Reg_FDP_SFO = reg;
2821 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2822 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2823 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2824 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2825
2826 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2827
2828 // get Reg_FSA_SFO,
2829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2830 Reg_FSA_SFO = reg;
2831 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2832 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2833 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2834 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2835
2836 // get Reg_FSA_IN,
2837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2838 Reg_FSA_IN = reg;
2839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2840 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2841 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2842
2843 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2844 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2845
2846 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2847 // ULOGD("DEMOD","\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2848 ULOGD("DEMOD","[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2849
2850
2851 return status;
2852 }
2853
INTERN_DVBT_Get_SYA_status(void)2854 void INTERN_DVBT_Get_SYA_status(void)
2855 {
2856 MS_U8 status = true;
2857 MS_U8 sya_k = 0,reg = 0;
2858 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2859
2860 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2861 sya_k = reg;
2862
2863 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2864 sya_th = reg;
2865 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2866 sya_th = (sya_th<<8)|reg;
2867
2868 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2869 sya_offset = reg;
2870 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2871 sya_offset = (sya_offset<<8)|reg;
2872
2873 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2874 len_m = reg;
2875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2876 len_m = (len_m<<8)|reg;
2877
2878 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2879 len_b = reg;
2880 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2881 len_b = (len_b<<8)|reg;
2882
2883
2884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2885 len_a = reg;
2886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2887 len_a = (len_a<<8)|reg;
2888
2889
2890 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2891 tracking_reg = reg;
2892
2893
2894 ULOGD("DEMOD","[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2895 ULOGD("DEMOD","[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2896
2897 return;
2898 }
2899
INTERN_DVBT_Get_cci_status(void)2900 void INTERN_DVBT_Get_cci_status(void)
2901 {
2902 MS_U8 status = true;
2903 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2904
2905 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2906 cci_fsweep = reg;
2907
2908 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2909 cci_kp = reg;
2910
2911 ULOGD("DEMOD","[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2912
2913 return;
2914 }
2915
INTERN_DVBT_Show_PRESFO_Info(void)2916 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2917 {
2918 MS_U8 tmp = 0;
2919 MS_BOOL status = TRUE;
2920 ULOGD("DEMOD","\n[SFO]");
2921 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2922 ULOGD("DEMOD","[%x]",tmp);
2923 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2924 ULOGD("DEMOD","[%x]",tmp);
2925 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2926 ULOGD("DEMOD","[%x]",tmp);
2927 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2928 ULOGD("DEMOD","[%x]",tmp);
2929 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2930 ULOGD("DEMOD","[%x]",tmp);
2931 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2932 ULOGD("DEMOD","[%x]",tmp);
2933 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2934 ULOGD("DEMOD","[%x]",tmp);
2935 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2936 ULOGD("DEMOD","[%x][End]",tmp);
2937
2938 return status;
2939 }
2940
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2941 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2942 {
2943 MS_BOOL status = true;
2944
2945 *locktime = 0xffff;
2946 ULOGE("DEMOD","[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2947
2948 status = false;
2949 return status;
2950 }
2951
2952
INTERN_DVBT_Show_Lock_Time_Info(void)2953 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2954 {
2955 MS_U16 locktime = 0;
2956 MS_BOOL status = TRUE;
2957 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2958 ULOGD("DEMOD","[DVBT]lock_time = %d ms\n",locktime);
2959 return status;
2960 }
2961
INTERN_DVBT_Show_BER_Info(void)2962 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2963 {
2964 MS_U8 tmp = 0;
2965 MS_BOOL status = TRUE;
2966 ULOGD("DEMOD","\n[BER]");
2967 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2968 ULOGD("DEMOD","[%x,",tmp);
2969 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2970 ULOGD("DEMOD","%x]",tmp);
2971 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2972 ULOGD("DEMOD","[%x,",tmp);
2973 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2974 ULOGD("DEMOD","%x]",tmp);
2975 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2976 ULOGD("DEMOD","[%x,",tmp);
2977 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2978 ULOGD("DEMOD","%x][End]",tmp);
2979
2980 return status;
2981
2982 }
2983
2984
INTERN_DVBT_Show_AGC_Info(void)2985 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2986 {
2987 MS_U8 tmp = 0;
2988 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2989 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2990 MS_U16 if_agc_err = 0;
2991 MS_BOOL status = TRUE;
2992 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2993
2994 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2995 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2997 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2998 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2999 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
3000
3001
3002 // select IF gain to read
3003 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3004 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
3005
3006 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3007 if_agc_gain = tmp;
3008 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3009 if_agc_gain = (if_agc_gain<<8)|tmp;
3010
3011
3012 // select d1 gain to read.
3013 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3014 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3015
3016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3017 d1_gain = tmp;
3018 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3019 d1_gain = (d1_gain<<8)|tmp;
3020
3021 // select d2 gain to read.
3022 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3023 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3024
3025 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3026 d2_gain = tmp;
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3028 d2_gain = (d2_gain<<8)|tmp;
3029
3030 // select IF gain err to read
3031 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3032 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3033
3034 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3035 if_agc_err = tmp;
3036 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3037 if_agc_err = (if_agc_err<<8)|tmp;
3038
3039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3040 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3041 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3042
3043
3044
3045 ULOGD("DEMOD","[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3046 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3047
3048 ULOGD("DEMOD","[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3049 ULOGD("DEMOD","[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3050
3051 return status;
3052
3053 }
3054
INTERN_DVBT_Show_WIN_Info(void)3055 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
3056 {
3057 MS_U8 tmp = 0;
3058 MS_U8 trigger = 0;
3059 MS_U16 win_len = 0;
3060
3061 MS_BOOL status = TRUE;
3062
3063 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3064 win_len = tmp;
3065 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3066 win_len = (win_len<<8)|tmp;
3067
3068 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3069
3070 ULOGD("DEMOD","[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3071
3072 return status;
3073 }
3074
INTERN_DVBT_Show_td_coeff(void)3075 void INTERN_DVBT_Show_td_coeff(void)
3076 {
3077 MS_U8 status = true;
3078 MS_U8 w1 = 0,w2 = 0,reg = 0;
3079
3080 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3081 w1 = reg;
3082
3083 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3084 w2 = reg;
3085
3086 ULOGD("DEMOD","[td]w1=0x%x, w2=0x%x\n",w1,w2);
3087
3088 return;
3089 }
3090
3091 /********************************************************
3092 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
3093 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
3094 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3095 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3096 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
3097 * FFT ( b14) : 0~1 => 2K, 8K
3098 ********************************/
INTERN_DVBT_Show_Modulation_info(void)3099 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
3100 {
3101 MS_U16 tps_info;
3102
3103 // ULOGD("DEMOD","[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
3104
3105 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
3106 {
3107 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
3108 MS_U8 constel = tps_info&0x0007;
3109 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
3110 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
3111 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
3112 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
3113
3114 ULOGD("DEMOD","tps=0x%x ",tps_info);
3115
3116 switch(fft)
3117 {
3118 case 0:
3119 ULOGD("DEMOD","mode = 2K,");
3120 break;
3121 case 1:
3122 ULOGD("DEMOD","mode = 8K,");
3123 break;
3124 default:
3125 ULOGE("DEMOD","mode = unknow,");
3126 break;
3127 }
3128 switch(constel)
3129 {
3130 case 0:
3131 ULOGD("DEMOD"," QPSK, ");
3132 break;
3133 case 1:
3134 ULOGD("DEMOD","16QAM, ");
3135 break;
3136 case 2:
3137 ULOGD("DEMOD","64QAM, ");
3138 break;
3139 default:
3140 ULOGE("DEMOD","unknow QAM, ");
3141 break;
3142 }
3143 switch(gi)
3144 {
3145 case 0:
3146 ULOGD("DEMOD","GI=1/32, ");
3147 break;
3148 case 1:
3149 ULOGD("DEMOD","GI=1/16, ");
3150 break;
3151 case 2:
3152 ULOGD("DEMOD","GI= 1/8, ");
3153 break;
3154 case 3:
3155 ULOGD("DEMOD","GI= 1/4, ");
3156 break;
3157 default:
3158 ULOGE("DEMOD","unknow GI, ");
3159 break;
3160 }
3161
3162 switch(hp_cr)
3163 {
3164 case 0:
3165 ULOGD("DEMOD","HP_CR=1/2, ");
3166 break;
3167 case 1:
3168 ULOGD("DEMOD","HP_CR=2/3, ");
3169 break;
3170 case 2:
3171 ULOGD("DEMOD","HP_CR=3/4, ");
3172 break;
3173 case 3:
3174 ULOGD("DEMOD","HP_CR=5/6, ");
3175 break;
3176 case 4:
3177 ULOGD("DEMOD","HP_CR=7/8, ");
3178 break;
3179 default:
3180 ULOGE("DEMOD","unknow hp_cr, ");
3181 break;
3182 }
3183
3184 switch(lp_cr)
3185 {
3186 case 0:
3187 ULOGD("DEMOD","LP_CR=1/2, ");
3188 break;
3189 case 1:
3190 ULOGD("DEMOD","LP_CR=2/3, ");
3191 break;
3192 case 2:
3193 ULOGD("DEMOD","LP_CR=3/4, ");
3194 break;
3195 case 3:
3196 ULOGD("DEMOD","LP_CR=5/6, ");
3197 break;
3198 case 4:
3199 ULOGD("DEMOD","LP_CR=7/8, ");
3200 break;
3201 default:
3202 ULOGE("DEMOD","unknow lp_cr, ");
3203 break;
3204 }
3205
3206 ULOGD("DEMOD"," Hiearchy=0x%x\n",hiearchy);
3207
3208 // ULOGD("DEMOD","\n");
3209 return TRUE;
3210 }
3211 else
3212 {
3213 ULOGE("DEMOD","INVALID\n");
3214 return FALSE;
3215 }
3216 }
3217
3218
3219
3220
INTERN_DVBT_Show_BER_PacketErr(void)3221 void INTERN_DVBT_Show_BER_PacketErr(void)
3222 {
3223 float f_ber = 0;
3224 MS_U16 packetErr = 0;
3225 INTERN_DVBT_GetPostViterbiBer(&f_ber);
3226 INTERN_DVBT_GetPacketErr(&packetErr);
3227
3228 ULOGE("DEMOD","[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3229 return;
3230 }
3231
INTERN_DVBT_Show_Lock_Info(void)3232 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
3233 {
3234
3235 ULOGE("DEMOD","[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
3236 return false;
3237 }
3238
3239
INTERN_DVBT_Show_Demod_Info(void)3240 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
3241 {
3242 MS_U8 demod_state = 0;
3243 MS_BOOL status = true;
3244 static MS_U8 counter = 0;
3245
3246 INTERN_DVBT_get_demod_state(&demod_state);
3247
3248 ULOGD("DEMOD","==========[dvbt]state=%d\n",demod_state);
3249 if (demod_state < 5)
3250 {
3251 INTERN_DVBT_Show_Demod_Version();
3252 INTERN_DVBT_Show_AGC_Info();
3253 INTERN_DVBT_Show_ACI_CI();
3254 }
3255 else if(demod_state < 8)
3256 {
3257 INTERN_DVBT_Show_Demod_Version();
3258 INTERN_DVBT_Show_AGC_Info();
3259 INTERN_DVBT_Show_ACI_CI();
3260 INTERN_DVBT_Show_ChannelLength();
3261 INTERN_DVBT_Get_CFO();
3262 INTERN_DVBT_Get_SFO();
3263 INTERN_DVBT_Show_td_coeff();
3264 }
3265 else if(demod_state < 11)
3266 {
3267 INTERN_DVBT_Show_Demod_Version();
3268 INTERN_DVBT_Show_AGC_Info();
3269 INTERN_DVBT_Show_ACI_CI();
3270 INTERN_DVBT_Show_ChannelLength();
3271 INTERN_DVBT_Get_CFO();
3272 INTERN_DVBT_Get_SFO();
3273 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3274 INTERN_DVBT_Get_SYA_status();
3275 INTERN_DVBT_Show_td_coeff();
3276 }
3277 else if((demod_state == 11) && ((counter%4) == 0))
3278 {
3279 INTERN_DVBT_Show_Demod_Version();
3280 INTERN_DVBT_Show_AGC_Info();
3281 INTERN_DVBT_Show_ACI_CI();
3282 INTERN_DVBT_Show_ChannelLength();
3283 INTERN_DVBT_Get_CFO();
3284 INTERN_DVBT_Get_SFO();
3285 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3286 INTERN_DVBT_Get_SYA_status();
3287 INTERN_DVBT_Show_td_coeff();
3288 INTERN_DVBT_Show_Modulation_info();
3289 INTERN_DVBT_Show_BER_PacketErr();
3290 }
3291 else
3292 status = false;
3293
3294 ULOGD("DEMOD","===========================\n");
3295 counter++;
3296
3297 return status;
3298 }
3299 #endif
3300
3301