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93 ////////////////////////////////////////////////////////////////////////////////
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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #define TEST_EMBEDED_DEMOD 0
129 //U8 load_data_variable=1;
130 //-----------------------------------------------------------------------
131 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
132
133 #define TDE_REG_BASE 0x2400
134 #define DIV_REG_BASE 0x2500
135 #define TR_REG_BASE 0x2600
136 #define FTN_REG_BASE 0x2700
137 #define FTNEXT_REG_BASE 0x2800
138
139
140
141 #if 0//ENABLE_SCAN_ONELINE_MSG
142 #define DBG_INTERN_DVBT_ONELINE(x) x
143 #else
144 #define DBG_INTERN_DVBT_ONELINE(x) // x
145 #endif
146
147 #ifdef MS_DEBUG
148 #define DBG_INTERN_DVBT(x) x
149 #define DBG_GET_SIGNAL(x) x
150 #define DBG_INTERN_DVBT_TIME(x) x
151 #define DBG_INTERN_DVBT_LOCK(x) x
152 #else
153 #define DBG_INTERN_DVBT(x) //x
154 #define DBG_GET_SIGNAL(x) //x
155 #define DBG_INTERN_DVBT_TIME(x) // x
156 #define DBG_INTERN_DVBT_LOCK(x) //x
157 #endif
158 #define DBG_DUMP_LOAD_DSP_TIME 0
159
160 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
161 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
162 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
163 #define INTERN_DVBT_INTERNAL_DEBUG 1
164
165 #define SIGNAL_LEVEL_OFFSET 0.00
166 #define TAKEOVERPOINT -59.0
167 #define TAKEOVERRANGE 0.5
168 #define LOG10_OFFSET -0.21
169 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
170 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
171
172
173 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
174 #define TUNER_VPP 2
175 #define IF_AGC_VPP 2
176 #else
177 #define TUNER_VPP 1
178 #define IF_AGC_VPP 2
179 #endif
180
181 #if (TUNER_VPP == 1)
182 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
183 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
185 #endif
186
187 /*BEG INTERN_DVBT_DSPREG_TABLE*/
188 #define D_DMD_DVBT_PARAM_VERSION 0x01
189 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
190 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
191 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
192 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
193 #define D_DMD_DVBT_OP_DCR_EN 0x01
194 #define D_DMD_DVBT_OP_IIS_EN 0x01
195 #define D_DMD_DVBT_OP_IQB_EN 0x00
196 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
197 #define D_DMD_DVBT_OP_ACI_EN 0x01
198 #define D_DMD_DVBT_OP_CCI_EN 0x01
199 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
200 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
201 #define D_DMD_DVBT_CFG_BW 0x00 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
202 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
203 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
204 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
205 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
206 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
207 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
208 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
209 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
210 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
211 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
212 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
213 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
214 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x10
215 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
216 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
217 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x00 //0xB0 YP for sensitivity test
218 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x06
219 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
220 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
221
222 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
223 #define D_DMD_DVBT_CFG_FC_H 0x4E
224 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
225 #define D_DMD_DVBT_CFG_FS_H 0x5D
226 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
227
228 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
229 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
230 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
231 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
232 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
233 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
234 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
235 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
236 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
237 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
238 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
239 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
240
241 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
242 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
243 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
244 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
245 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
246 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
247 #else
248 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
249 #endif
250 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
251
252 /*END INTERN_DVBT_DSPREG_TABLE*/
253 #define DVBT_FS 48000
254 #define FC_H 0xA7 // 43000, Fc = Fs - IF = 48000 - 5000 = 43000(0xA7F8)
255 #define FC_L 0xF8
256 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
257 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
258 #define SET_ZIF 0x00
259 #define IQB_EN 0x00
260
261 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
262 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
263 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
264 #define CSTL 0x02 //0:QPSK 1:16 2: 64
265 #define HIER 0x00
266 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
267 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
268 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
269 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
270 #define LP_SEL 0x00 // LP select
271 #define IQ_SWAP 0x00
272 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
273 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
274 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
275 #define TS_SER 0
276 #define TS_INV 0
277 #define FIF_H (MS_U8)(( (((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))>>8)
278 #define FIF_L (MS_U8)(( ((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))
279 #define IF_INV_PWM 0x00
280 #define T_LOWIF 1
281
282 MS_U8 INTERN_DVBT_DSPREG[] =
283 {
284 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
285 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
286 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
287 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
288 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
289 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
290 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
292 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
293 /*
294 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
295 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
296 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
297 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
298 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
299 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
300 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
301 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
302 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
303 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
304 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
305 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
306 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
307 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
308 */
309 };
310 /*END INTERN_DVBT_DSPREG_TABLE*/
311 //-----------------------------------------------------------------------
312 /****************************************************************
313 *Local Variables *
314 ****************************************************************/
315 static MS_BOOL bFECLock=0;
316 static MS_BOOL bTPSLock = 0;
317 static MS_U32 u32ChkScanTimeStart = 0;
318 static MS_U32 u32FecFirstLockTime=0;
319 static MS_U32 u32FecLastLockTime=0;
320 static float fViterbiBerFiltered=-1;
321 //Global Variables
322 S_CMDPKTREG gsCmdPacket;
323 //U8 gCalIdacCh0, gCalIdacCh1;
324
325 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
326 MS_U8 INTERN_DVBT_table[] = {
327 #include "fwDMD_INTERN_DVBT.dat"
328 };
329
330 #endif
331
332 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
333 {
334 { _QPSK , _CR1Y2, -93},
335 { _QPSK , _CR2Y3, -91},
336 { _QPSK , _CR3Y4, -90},
337 { _QPSK , _CR5Y6, -89},
338 { _QPSK , _CR7Y8, -88},
339
340 { _16QAM , _CR1Y2, -87},
341 { _16QAM , _CR2Y3, -85},
342 { _16QAM , _CR3Y4, -84},
343 { _16QAM , _CR5Y6, -83},
344 { _16QAM , _CR7Y8, -82},
345
346 { _64QAM , _CR1Y2, -82},
347 { _64QAM , _CR2Y3, -80},
348 { _64QAM , _CR3Y4, -78},
349 { _64QAM , _CR5Y6, -77},
350 { _64QAM , _CR7Y8, -76},
351 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
352 };
353
354
355
356 static void INTERN_DVBT_SignalQualityReset(void);
357 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
358
INTERN_DVBT_SignalQualityReset(void)359 static void INTERN_DVBT_SignalQualityReset(void)
360 {
361 u32FecFirstLockTime=0;
362 fViterbiBerFiltered=-1;
363 }
364
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)365 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
366 {
367 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
368 MS_BOOL status = TRUE;
369 MS_U16 u16DspAddr = 0;
370
371 DBG_INTERN_DVBT(printf("INTERN_DVBT_DSPReg_Init\n"));
372
373 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
374 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
375
376 if (u8DVBT_DSPReg != NULL)
377 {
378 /*temp solution until new dsp table applied.*/
379 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
380 if (u8DVBT_DSPReg[0] >= 1)
381 {
382 u8DVBT_DSPReg+=2;
383 for (idx = 0; idx<u8Size; idx++)
384 {
385 u16DspAddr = *u8DVBT_DSPReg;
386 u8DVBT_DSPReg++;
387 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
388 u8DVBT_DSPReg++;
389 u8Mask = *u8DVBT_DSPReg;
390 u8DVBT_DSPReg++;
391 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
392 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
393 u8DVBT_DSPReg++;
394 printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite);
395 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
396 }
397 }
398 else
399 {
400 printf("FATAL: parameter version incorrect\n");
401 }
402 }
403
404 return status;
405 }
406
407 /***********************************************************************************
408 Subject: Command Packet Interface
409 Function: INTERN_DVBT_Cmd_Packet_Send
410 Parmeter:
411 Return: MS_BOOL
412 Remark:
413 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)414 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
415 {
416 return TRUE;
417
418 }
419
420
421 /***********************************************************************************
422 Subject: Command Packet Interface
423 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
424 Parmeter:
425 Return: MS_BOOL
426 Remark:
427 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)428 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
429 {
430 return TRUE;
431 }
432
433 /***********************************************************************************
434 Subject: SoftStop
435 Function: INTERN_DVBT_SoftStop
436 Parmeter:
437 Return: MS_BOOL
438 Remark:
439 ************************************************************************************/
440
INTERN_DVBT_SoftStop(void)441 MS_BOOL INTERN_DVBT_SoftStop ( void )
442 {
443 #if 1
444 MS_U16 u8WaitCnt=0;
445
446 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
447 {
448 printf(">> MB Busy!\n");
449 return FALSE;
450 }
451
452 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
453
454 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
455 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
456
457 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
458 {
459 #if TEST_EMBEDED_DEMOD
460 MsOS_DelayTask(1); // << Ken 20090629
461 #endif
462 if (u8WaitCnt++ >= 0x7FF)
463 {
464 printf(">> DVBT SoftStop Fail!\n");
465 return FALSE;
466 }
467 }
468
469 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
470 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
471 #endif
472 return TRUE;
473 }
474
475
476 /***********************************************************************************
477 Subject: Reset
478 Function: INTERN_DVBT_Reset
479 Parmeter:
480 Return: MS_BOOL
481 Remark:
482 ************************************************************************************/
483 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)484 MS_BOOL INTERN_DVBT_Reset ( void )
485 {
486 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_reset\n"));
487
488 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime()));
489
490 INTERN_DVBT_SoftStop();
491
492
493 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
494 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
495 MsOS_DelayTask(5);
496 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
497 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
498 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
499 MsOS_DelayTask(5);
500
501 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
502 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
503
504 bFECLock = FALSE;
505 bTPSLock = FALSE;
506 u32ChkScanTimeStart = MsOS_GetSystemTime();
507 return TRUE;
508 }
509
510 /***********************************************************************************
511 Subject: Exit
512 Function: INTERN_DVBT_Exit
513 Parmeter:
514 Return: MS_BOOL
515 Remark:
516 ************************************************************************************/
INTERN_DVBT_Exit(void)517 MS_BOOL INTERN_DVBT_Exit ( void )
518 {
519
520 INTERN_DVBT_SoftStop();
521
522
523 return TRUE;
524 }
525
526 /***********************************************************************************
527 Subject: Load DSP code to chip
528 Function: INTERN_DVBT_LoadDSPCode
529 Parmeter:
530 Return: MS_BOOL
531 Remark:
532 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)533 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
534 {
535 MS_U8 udata = 0x00;
536 MS_U16 i;
537 MS_U16 fail_cnt=0;
538
539 #if (DBG_DUMP_LOAD_DSP_TIME==1)
540 MS_U32 u32Time;
541 #endif
542
543
544 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
545 BININFO BinInfo;
546 MS_BOOL bResult;
547 MS_U32 u32GEAddr;
548 MS_U8 Data;
549 MS_S8 op;
550 MS_U32 srcaddr;
551 MS_U32 len;
552 MS_U32 SizeBy4K;
553 MS_U16 u16Counter=0;
554 MS_U8 *pU8Data;
555 #endif
556
557
558
559 // MDrv_Sys_DisableWatchDog();
560
561
562 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
563 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
564 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
565 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
566 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
567 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
568
569 //// Load code thru VDMCU_IF ////
570 DBG_INTERN_DVBT(printf(">Load Code...\n"));
571 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
572 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
573 {
574 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
575 }
576 #else
577 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
578 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
579 if ( bResult != PASS )
580 {
581 return FALSE;
582 }
583 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
584
585 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
586 InfoBlock_Flash_2_Checking_Start(&BinInfo);
587 #endif
588
589 #if OBA2
590 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
591 #else
592 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
593 #endif
594
595 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
596 InfoBlock_Flash_2_Checking_End(&BinInfo);
597 #endif
598
599 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
600 SizeBy4K=BinInfo.B_Len/0x1000;
601 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
602
603 #if (DBG_DUMP_LOAD_DSP_TIME==1)
604 u32Time = msAPI_Timer_GetTime0();
605 #endif
606
607 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
608
609 for (i=0;i<=SizeBy4K;i++)
610 {
611 if(i==SizeBy4K)
612 len=BinInfo.B_Len%0x1000;
613 else
614 len=0x1000;
615
616 srcaddr = u32GEAddr+(0x1000*i);
617 //printf("\t i = %08X\n", i);
618 //printf("\t len = %08X\n", len);
619 op = 1;
620 u16Counter = 0 ;
621 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
622 while(len--)
623 {
624 u16Counter ++ ;
625 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
626 //pU8Data = (U8 *)(srcaddr|0x80000000);
627 #if OBA2
628 pU8Data = (U8 *)(srcaddr);
629 #else
630 pU8Data = (U8 *)(srcaddr|0x80000000);
631 #endif
632 Data = *pU8Data;
633
634 #if 0
635 if(u16Counter < 0x100)
636 printf("0x%bx,", Data);
637 #endif
638 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
639
640 srcaddr += op;
641 }
642 // printf("\n\n\n");
643 }
644
645 #if (DBG_DUMP_LOAD_DSP_TIME==1)
646 printf("------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
647 #endif
648
649 #endif
650
651 //// Content verification ////
652 DBG_INTERN_DVBT(printf(">Verify Code...\n"));
653
654 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
655 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
656
657 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
658 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
659 {
660 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
661 if (udata != INTERN_DVBT_table[i])
662 {
663 printf(">fail add = 0x%x\n", i);
664 printf(">code = 0x%x\n", INTERN_DVBT_table[i]);
665 printf(">data = 0x%x\n", udata);
666
667 if (fail_cnt++ > 10)
668 {
669 printf(">DVB-T DSP Loadcode fail!");
670 return false;
671 }
672 }
673 }
674 #else
675 for (i=0;i<=SizeBy4K;i++)
676 {
677 if(i==SizeBy4K)
678 len=BinInfo.B_Len%0x1000;
679 else
680 len=0x1000;
681
682 srcaddr = u32GEAddr+(0x1000*i);
683 //printf("\t i = %08LX\n", i);
684 //printf("\t len = %08LX\n", len);
685 op = 1;
686 u16Counter = 0 ;
687 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
688 while(len--)
689 {
690 u16Counter ++ ;
691 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
692 //pU8Data = (U8 *)(srcaddr|0x80000000);
693 #if OBA2
694 pU8Data = (U8 *)(srcaddr);
695 #else
696 pU8Data = (U8 *)(srcaddr|0x80000000);
697 #endif
698 Data = *pU8Data;
699
700 #if 0
701 if(u16Counter < 0x100)
702 printf("0x%bx,", Data);
703 #endif
704 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
705 if (udata != Data)
706 {
707 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
708 printf(">code = 0x%x\n", Data);
709 printf(">data = 0x%x\n", udata);
710
711 if (fail_cnt++ > 10)
712 {
713 printf(">DVB-T DSP Loadcode fail!");
714 return false;
715 }
716 }
717
718 srcaddr += op;
719 }
720 // printf("\n\n\n");
721 }
722 #endif
723
724 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
725 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
726 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
727 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
728
729 DBG_INTERN_DVBT(printf(">DSP Loadcode done."));
730 //while(load_data_variable);
731
732
733
734 return TRUE;
735 }
736
737 /***********************************************************************************
738 Subject: DVB-T CLKGEN initialized function
739 Function: INTERN_DVBT_Power_On_Initialization
740 Parmeter:
741 Return: MS_BOOL
742 Remark:
743 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)744 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
745 {
746 MS_U8 temp_val;
747 MS_U8 udatatemp = 0x00;
748 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
749 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
750 // ----------------------------------------------
751 // start demod CLKGEN setting
752 // ----------------------------------------------
753 // *** Set register at CLKGEN1
754 // enable DMD MCU clock "bit[0] set 0"
755 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
756 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
757 // CLK_DMDMCU clock setting
758 // [0] disable clock
759 // [1] invert clock
760 // [4:2]
761 // 000:170 MHz(MPLL_DIV_BUf)
762 // 001:160MHz
763 // 010:144MHz
764 // 011:123MHz
765 // 100:108MHz
766 // 101:mem_clcok
767 // 110:mem_clock div 2
768 // 111:select XTAL
769 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
770 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
771
772 // set parallet ts clock
773 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
774 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
775
776 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b
777 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
778 temp_val|=0x07;
779 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
780
781 //HAL_DMD_RIU_WriteByte(0x103300,0x17);
782 HAL_DMD_RIU_WriteByte(0x103300,0x14); // arthur 2016.10.17
783
784 // enable atsc, DVBTC ts clock
785 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
786 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
787 HAL_DMD_RIU_WriteByte(0x103309,0x00);
788 HAL_DMD_RIU_WriteByte(0x103308,0x00);
789
790 // enable dvbc adc clock
791 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
792 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
793 HAL_DMD_RIU_WriteByte(0x103315,0x00);
794 HAL_DMD_RIU_WriteByte(0x103314,0x00);
795
796
797
798
799 // Select MPLLDIV2
800 // [0] : reg_fed_srd_on
801 // [1] : reg_dvbt_new_tdsfo_on
802 // [2] : reg_dvbc_p4_cfo_on
803 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h15, 2'b01, 16'h0001);
804 // wriu 0x111f2a 0x01
805 udatatemp = HAL_DMD_RIU_ReadByte(0x111f2a);
806 HAL_DMD_RIU_WriteByte(0x111f2a,udatatemp&0xF8);
807
808
809
810 // enable clk_atsc_adcd_sync
811 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
812 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
813 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
814 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
815
816 // enable dvbt inner clock
817 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
818 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
819 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
820 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
821
822 // enable dvbt inner clock
823 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
824 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
825 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
826 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
827
828 // enable dvbt inner clock
829 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
830 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
831 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
832 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
833
834 // enable dvbc outer clock
835 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
836 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
837 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
838 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
839
840 // enable dvbc inner-c clock
841 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
842 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
843 //HAL_DMD_RIU_WriteByte(0x111f15,0x00);
844 //HAL_DMD_RIU_WriteByte(0x111f14,0x00);
845
846 // enable dvbc eq clock
847 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
848 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
849 //HAL_DMD_RIU_WriteByte(0x111f17,0x00);
850 //HAL_DMD_RIU_WriteByte(0x111f16,0x00);
851
852 // enable sram clock
853 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
854 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
855 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
856 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
857
858 // enable isdbt clock
859 // [2:0] : reg_ckg_isdbt_inner1x
860 // [0] : disable clock
861 // [1] : invert clock
862 // [3:2]: Select clock source
863 // 00: clk_dmplldiv10_div4(21.6MHz, ISDBT only)
864 // 01: reserved
865 // 10: reserved
866 // 11: DFT_CLK
867 // [6:4]: reg_ckg_isdbt_inner2x
868 // [0] : disable clock
869 // [1] : invert clock
870 // [2]: Select clock source
871 // 00: clk_dmplldiv10_div2(43.2MHz,ISDBT only)
872 // 01: reserved
873 // 10: reserved
874 // 11: DFT_CLK
875 // [10:8] : reg_ckg_isdbt_inner4x
876 // [0] : disable clock
877 // [1] : invert clock
878 // [3:2]: Select clock source
879 // 00: clk_dmplldiv10(86.4 MHz, DVBT only)
880 // 01: reserved
881 // 10: reserved
882 // 11: DFT_CLK
883 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
884 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
885 // HAL_DMD_RIU_WriteByte(0x111f43,0x00);
886 // HAL_DMD_RIU_WriteByte(0x111f42,0x00);
887
888 HAL_DMD_RIU_WriteByte(0x111f43,0x00);
889 HAL_DMD_RIU_WriteByte(0x111f42,0x00);
890
891 HAL_DMD_RIU_WriteByte(0x111f45,0x00);
892 HAL_DMD_RIU_WriteByte(0x111f44,0x00);
893
894 HAL_DMD_RIU_WriteByte(0x111f46,0x01);
895 // [9:8] : reg_ckg_adc1x_eq1x
896 // [0]: disable clock
897 // [1]: invert clock
898 // [13:12] : reg_ckg_adc0p5x_eq0p5x
899 // [0]: disable clock
900 // [1]: invert clock
901 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
902 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
903 // wriu 0x111f49 0x00 // nike
904 // wriu 0x111f48 0x00 // nike
905 HAL_DMD_RIU_WriteByte(0x111f49,0x00);
906 HAL_DMD_RIU_WriteByte(0x111f48,0x00);
907
908 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
909 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
910
911 HAL_DMD_RIU_WriteByte(0x111f4d,0x00);
912 HAL_DMD_RIU_WriteByte(0x111f4c,0x00);
913 HAL_DMD_RIU_WriteByte(0x111f4e,0x00);
914
915
916 // enable vif clock
917 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
918 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
919 //HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
920 //HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
921
922 // enable DEMODE-DMA clock
923 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
924 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
925 //HAL_DMD_RIU_WriteByte(0x111f21,0x00);
926 //HAL_DMD_RIU_WriteByte(0x111f20,0x00);
927
928 // select clock
929 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
930 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
931 // HAL_DMD_RIU_WriteByte(0x111f23,0x00);
932 // HAL_DMD_RIU_WriteByte(0x111f22,0x00);
933 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
934 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
935
936 HAL_DMD_RIU_WriteByte(0x111f51,0x00);
937 HAL_DMD_RIU_WriteByte(0x111f50,0x88);
938 // ----------------------------------------------
939 // start demod CLKGEN setting
940 // ----------------------------------------------
941 // select DMD MCU
942 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
943 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
944 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
945
946 // stream2miu_en, activate rst_wadr
947 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
948 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
949 // stream2miu_en, turn off rst_wadr
950 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
951
952 }
953
954 /***********************************************************************************
955 Subject: Power on initialized function
956 Function: INTERN_DVBT_Power_On_Initialization
957 Parmeter:
958 Return: MS_BOOL
959 Remark:
960 ************************************************************************************/
961
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)962 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
963 {
964 MS_U16 status = true;
965 MS_U8 cData = 0;
966 //U8 cal_done;
967 DBG_INTERN_DVBT(printf("INTERN_DVBT_Power_On_Initialization\n"));
968
969 #if defined(PWS_ENABLE)
970 Mapi_PWS_Stop_VDMCU();
971 #endif
972
973 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
974 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
975 //// Firmware download //////////
976 DBG_INTERN_DVBT(printf("INTERN_DVBT Load DSP...\n"));
977 //MsOS_DelayTask(100);
978
979 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
980 {
981 if (INTERN_DVBT_LoadDSPCode() == FALSE)
982 {
983 printf("DVB-T Load DSP Code Fail\n");
984 return FALSE;
985 }
986 else
987 {
988 DBG_INTERN_DVBT(printf("DVB-T Load DSP Code OK\n"));
989 }
990 }
991
992
993 //// MCU Reset //////////
994 DBG_INTERN_DVBT(printf("INTERN_DVBT Reset...\n"));
995 if (INTERN_DVBT_Reset() == FALSE)
996 {
997 DBG_INTERN_DVBT(printf("Fail\n"));
998 return FALSE;
999 }
1000 else
1001 {
1002 DBG_INTERN_DVBT(printf("OK\n"));
1003 }
1004
1005 // reset FDP
1006 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1007 // SRAM setting, DVB-T use it.
1008 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1009 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1010 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1011
1012 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1013 return status;
1014 }
1015
1016 /************************************************************************************************
1017 Subject: Driving control
1018 Function: INTERN_DVBT_Driving_Control
1019 Parmeter: bInversionEnable : TRUE For High
1020 Return: void
1021 Remark:
1022 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1023 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1024 {
1025 MS_U8 u8Temp;
1026
1027 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1028
1029 if (bEnable)
1030 {
1031 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1032 }
1033 else
1034 {
1035 u8Temp = u8Temp & (~0x01);
1036 }
1037
1038 DBG_INTERN_DVBT(printf("---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1039 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1040 }
1041 /************************************************************************************************
1042 Subject: Clk Inversion control
1043 Function: INTERN_DVBT_Clk_Inversion_Control
1044 Parmeter: bInversionEnable : TRUE For Inversion Action
1045 Return: void
1046 Remark:
1047 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1048 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1049 {
1050 MS_U8 u8Temp;
1051
1052 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1053
1054 if (bInversionEnable)
1055 {
1056 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1057 }
1058 else
1059 {
1060 u8Temp = u8Temp & (~0x02);
1061 }
1062
1063 DBG_INTERN_DVBT(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1064 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1065 }
1066 /************************************************************************************************
1067 Subject: Transport stream serial/parallel control
1068 Function: INTERN_DVBT_Serial_Control
1069 Parmeter: bEnable : TRUE For serial
1070 Return: MS_BOOL :
1071 Remark:
1072 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1073 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1074 {
1075 MS_U8 status = true;
1076 MS_U8 temp_val;
1077 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_ts... u8TSClk=%d\n",u8TSClk));
1078
1079 return status;
1080
1081 if (u8TSClk == 0xFF) u8TSClk=0x17;
1082 if (bEnable) //Serial mode for TS pad
1083 {
1084 // serial
1085 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1086 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1087
1088 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1089 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1090 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1091
1092 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1093 temp_val|=0x04;
1094 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1095 #else
1096 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1097 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1098 temp_val|=0x07;
1099 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1100 #endif
1101
1102 }
1103 else
1104 {
1105 //parallel
1106 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1107 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1108
1109 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1110 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1111 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1112 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1113 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1114 temp_val|=0x05;
1115 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1116 #else
1117 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1118 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1119 temp_val|=0x07;
1120 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1121 #endif
1122 }
1123
1124 DBG_INTERN_DVBT(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1125
1126 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1127 return status;
1128 }
1129
1130 /************************************************************************************************
1131 Subject: TS1 output control
1132 Function: INTERN_DVBT_PAD_TS1_Enable
1133 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1134 Return: void
1135 Remark:
1136 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1137 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1138 {
1139 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_TS1_Enable... \n"));
1140
1141 if(flag) // PAD_TS1 Enable TS CLK PAD
1142 {
1143 //printf("=== TS1_Enable ===\n");
1144 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1145 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1146 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1147 }
1148 else // PAD_TS1 Disable TS CLK PAD
1149 {
1150 //printf("=== TS1_Disable ===\n");
1151 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1152 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1153 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1154 }
1155 }
1156
1157 /************************************************************************************************
1158 Subject: channel change config
1159 Function: INTERN_DVBT_Config
1160 Parmeter: BW: bandwidth
1161 Return: MS_BOOL :
1162 Remark:
1163 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1164 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1165 {
1166 MS_U8 bandwidth;
1167 MS_U8 status = true;
1168 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_config %d %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap));
1169 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime()));
1170
1171 if (u8TSClk == 0xFF) u8TSClk=0x13;
1172 switch(BW)
1173 {
1174 case E_DMD_RF_CH_BAND_6MHz:
1175 bandwidth = 1;
1176 break;
1177 case E_DMD_RF_CH_BAND_7MHz:
1178 bandwidth = 2;
1179 break;
1180 case E_DMD_RF_CH_BAND_8MHz:
1181 default:
1182 bandwidth = 3;
1183 break;
1184 }
1185
1186 status &= INTERN_DVBT_Reset();
1187
1188 // BW mode
1189 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1190 // TS mode
1191 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1192 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1193 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1194 // Hierarchy mode
1195 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1196 // FC
1197 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1198 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1199 // FS
1200 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1201 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1202 // IQSwap
1203 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1204
1205 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1206 // Fif
1207 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1208 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1209
1210 return status;
1211 }
1212 /************************************************************************************************
1213 Subject: enable hw to lock channel
1214 Function: INTERN_DVBT_Active
1215 Parmeter: bEnable
1216 Return: MS_BOOL
1217 Remark:
1218 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1219 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1220 {
1221 MS_U8 status = true;
1222
1223 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_active\n"));
1224 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1225 INTERN_DVBT_SignalQualityReset();
1226
1227 return status;
1228 }
1229 /************************************************************************************************
1230 Subject: Return lock status
1231 Function: INTERN_DVBT_Lock
1232 Parmeter: eStatus :
1233 Return: MS_BOOL
1234 Remark:
1235 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1236 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1237 {
1238 float fBER=0.0f;
1239
1240 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1241 {
1242 if (bFECLock == FALSE)
1243 {
1244 u32FecFirstLockTime = MsOS_GetSystemTime();
1245 DBG_INTERN_DVBT(printf("++++++++[utopia]dvbt lock\n"));
1246 }
1247
1248 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1249 {
1250 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1251 {
1252 if(fViterbiBerFiltered <= 0.0)
1253 fViterbiBerFiltered = fBER;
1254 else
1255 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1256 }
1257 DBG_INTERN_DVBT(printf("[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered));
1258 }
1259 u32FecLastLockTime = MsOS_GetSystemTime();
1260 bFECLock = TRUE;
1261 return E_DMD_LOCK;
1262 }
1263 else
1264 {
1265 INTERN_DVBT_SignalQualityReset();
1266 if (bFECLock == TRUE)
1267 {
1268 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1269 {
1270 return E_DMD_LOCK;
1271 }
1272 }
1273 bFECLock = FALSE;
1274 }
1275
1276 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1277 {
1278 printf("==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1279 return E_DMD_UNLOCK;
1280 }
1281
1282 if(!bTPSLock)
1283 {
1284 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1285 {
1286 DBG_INTERN_DVBT(printf("==> INTERN_DVBT_Lock -- TPSLock \n"););
1287 bTPSLock = TRUE;
1288 }
1289 }
1290 if(bTPSLock)
1291 {
1292 DBG_INTERN_DVBT(printf("TPSLock %ld\n",MsOS_GetSystemTime()));
1293 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1294 {
1295 return E_DMD_CHECKING;
1296 }
1297 }
1298 else
1299 {
1300 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1301 {
1302 return E_DMD_CHECKING;
1303 }
1304 }
1305 return E_DMD_UNLOCK;
1306
1307 }
1308
1309
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1310 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1311 {
1312 MS_U16 u16Address = 0;
1313 MS_U8 cData = 0;
1314 MS_U8 cBitMask = 0;
1315
1316 switch( eStatus )
1317 {
1318 case E_DMD_COFDM_FEC_LOCK:
1319 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1320
1321 if (cData == 0x0B)
1322 {
1323 return TRUE;
1324 }
1325 else
1326 {
1327 return FALSE; // continuously un-lock
1328 }
1329 break;
1330
1331 case E_DMD_COFDM_PSYNC_LOCK:
1332 u16Address = 0x232C; //FEC: P-sync Lock,
1333 cBitMask = BIT(1);
1334 break;
1335
1336 case E_DMD_COFDM_TPS_LOCK:
1337 u16Address = 0x2222; //TPS HW Lock,
1338 cBitMask = BIT(1);
1339 break;
1340
1341 case E_DMD_COFDM_DCR_LOCK:
1342 u16Address = 0x2737; //DCR Lock,
1343 cBitMask = BIT(0);
1344 break;
1345
1346 case E_DMD_COFDM_AGC_LOCK:
1347 u16Address = 0x271D; //AGC Lock,
1348 cBitMask = BIT(0);
1349 break;
1350
1351 case E_DMD_COFDM_MODE_DET:
1352 u16Address = 0x24CF; //Mode CP Detect,
1353 cBitMask = BIT(4);
1354 break;
1355
1356 case E_DMD_COFDM_TPS_EVER_LOCK:
1357 u16Address = 0x20C0; //TPS Ever Lock,
1358 cBitMask = BIT(3);
1359 break;
1360
1361 case E_DMD_COFDM_NO_CHANNEL:
1362 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1363 cBitMask = BIT(7);
1364 break;
1365
1366 default:
1367 return FALSE;
1368 }
1369
1370 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1371 return FALSE;
1372
1373 if ((cData & cBitMask) == cBitMask)
1374 {
1375 return TRUE;
1376 }
1377
1378 return FALSE;
1379
1380 }
1381
1382 /****************************************************************************
1383 Subject: To get the Post viterbi BER
1384 Function: INTERN_DVBT_GetPostViterbiBer
1385 Parmeter: Quility
1386 Return: E_RESULT_SUCCESS
1387 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1388 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1389 We will not read the Period, and have the "/256/8"
1390 *****************************************************************************/
INTERN_DVBT_GetPostViterbiBer(float * ber)1391 MS_BOOL INTERN_DVBT_GetPostViterbiBer(float *ber)
1392 {
1393 MS_BOOL status = true;
1394 MS_U8 reg=0, reg_frz=0;
1395 MS_U16 BitErrPeriod;
1396 MS_U32 BitErr;
1397 MS_U16 PktErr;
1398
1399 /////////// Post-Viterbi BER /////////////
1400
1401 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1402 {
1403 *ber = (float)-1.0;
1404 return false;
1405 }
1406 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1407 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1408 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1409
1410 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1411 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1413 BitErrPeriod = reg;
1414
1415 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1416 BitErrPeriod = (BitErrPeriod << 8)|reg;
1417
1418 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1419 // 0x6b [15:8] reg_bit_err_num_15_8
1420 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1421 // 0x6d [15:8] reg_bit_err_num_31_24
1422 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1423 BitErr = reg;
1424
1425 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1426 BitErr = (BitErr << 8)|reg;
1427
1428 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1429 BitErr = (BitErr << 8)|reg;
1430
1431 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1432 BitErr = (BitErr << 8)|reg;
1433
1434 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1435 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1436 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1437 PktErr = reg;
1438
1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1440 PktErr = (PktErr << 8)|reg;
1441
1442 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1443 reg_frz=reg_frz&(~0x03);
1444 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1445
1446 if (BitErrPeriod == 0 ) //protect 0
1447 BitErrPeriod = 1;
1448
1449 if (BitErr <=0 )
1450 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1451 else
1452 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1453
1454
1455 DBG_GET_SIGNAL(printf("INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1456 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1457
1458 return status;
1459 }
1460
1461 /****************************************************************************
1462 Subject: To get the Pre viterbi BER
1463 Function: INTERN_DVBT_GetPreViterbiBer
1464 Parmeter: ber
1465 Return: E_RESULT_SUCCESS
1466 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1467 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1468 We will not read the Period, and have the "/256/8"
1469 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1470 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1471 {
1472 MS_U8 status = true;
1473 MS_U8 reg=0, reg_frz=0;
1474 MS_U16 BitErrPeriod;
1475 MS_U32 BitErr;
1476 MS_BOOL BEROver;
1477
1478 // bank 7 0x10 [3] reg_rd_freezeber
1479 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1480 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1481
1482 // bank 7 0x16 [7:0] reg_ber_timerl
1483 // [15:8] reg_ber_timerm
1484 // bank 7 0x18 [5:0] reg_ber_timerh
1485 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1486 BitErrPeriod = reg&0x3f;
1487
1488 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1489 BitErrPeriod = (BitErrPeriod << 8)|reg;
1490
1491 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1492 BitErrPeriod = (BitErrPeriod << 8)|reg;
1493
1494 // bank 7 0x1e [7:0] reg_ber_7_0
1495 // [15:8] reg_ber_15_8
1496 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1497 BitErr = reg;
1498
1499 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1500 BitErr = (BitErr << 8)|reg;
1501
1502 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1503 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1504 if (reg & 0x10)
1505 BEROver = true;
1506 else
1507 BEROver = false;
1508
1509 if (BitErrPeriod ==0 )//protect 0
1510 BitErrPeriod=1;
1511
1512 if (BEROver)
1513 {
1514 *ber = 1;
1515 printf("BER is over\n");
1516 }
1517 else
1518 {
1519 if (BitErr <=0 )
1520 *ber=0.5 / (float)(BitErrPeriod * 256);
1521 else
1522 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1523 }
1524
1525 // bank 7 0x10 [3] reg_rd_freezeber
1526 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1527
1528 return status;
1529 }
1530
1531 /****************************************************************************
1532 Subject: To get the Packet error
1533 Function: INTERN_DVBT_GetPacketErr
1534 Parmeter: pktErr
1535 Return: E_RESULT_SUCCESS
1536 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1537 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1538 We will not read the Period, and have the "/256/8"
1539 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1540 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1541 {
1542 MS_BOOL status = true;
1543 MS_U8 reg = 0, reg_frz = 0;
1544 MS_U16 PktErr;
1545
1546 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1548 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1549
1550 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1551 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1552 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1553 PktErr = reg;
1554
1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1556 PktErr = (PktErr << 8)|reg;
1557
1558 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1559 reg_frz=reg_frz&(~0x03);
1560 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1561
1562 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1563
1564 *u16PktErr = PktErr;
1565
1566 return status;
1567 }
1568
1569 /****************************************************************************
1570 Subject: To get the DVBT parameter
1571 Function: INTERN_DVBT_Get_TPS_Info
1572 Parmeter: point to return parameter
1573 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1574 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1575 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1576 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1577 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1578 FFT ( b14) : 0~1 => 2K, 8K
1579 Priority(bit 15) : 0~1=> HP,LP
1580 Return: TRUE
1581 FALSE
1582 Remark: The TPS parameters will be available after TPS lock
1583 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1584 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1585 {
1586 MS_U8 u8Temp;
1587
1588 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1589 return FALSE;
1590
1591 if ((u8Temp& 0x02) != 0x02)
1592 {
1593 return FALSE; //TPS unlock
1594 }
1595 else
1596 {
1597 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1598 return FALSE;
1599
1600 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1601 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1602
1603 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1604 return FALSE;
1605
1606 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1607 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1608
1609 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1610 return FALSE;
1611
1612 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
1613 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
1614
1615 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
1616 return FALSE;
1617
1618 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
1619
1620 }
1621 return TRUE;
1622 }
1623
1624
1625 /****************************************************************************
1626 Subject: Read the signal to noise ratio (SNR)
1627 Function: INTERN_DVBT_GetSNR
1628 Parmeter: None
1629 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1630 Remark:
1631 *****************************************************************************/
INTERN_DVBT_GetSNR(void)1632 float INTERN_DVBT_GetSNR (void)
1633 {
1634 MS_U8 status = true;
1635 MS_U8 reg=0, reg_frz=0;
1636 MS_U32 noise_power;
1637 float snr;
1638
1639 // bank 6 0xfe [0] reg_fdp_freeze
1640 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
1641 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
1642
1643 // bank 6 0xff [0] reg_fdp_load
1644 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1645
1646 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
1647 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
1648 noise_power = reg & 0x07;
1649
1650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
1651 noise_power = (noise_power << 8)|reg;
1652
1653 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
1654 noise_power = (noise_power << 8)|reg;
1655
1656 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
1657 noise_power = (noise_power << 8)|reg;
1658
1659 // bank 6 0x26 [5:4] reg_transmission_mode
1660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
1661
1662 // bank 6 0xfe [0] reg_fdp_freeze
1663 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
1664
1665 // bank 6 0xff [0] reg_fdp_load
1666 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1667
1668 #if 1
1669 noise_power = noise_power/2;
1670 noise_power /=1280;
1671 // noisepower = (rand()%256)*256;
1672 if (noise_power==0)//protect value 0
1673 noise_power=1;
1674
1675
1676 #ifdef MSOS_TYPE_LINUX
1677 snr = 10*log10f((float)noise_power);
1678 #else
1679 snr = 10*Log10Approx((float)noise_power);
1680 #endif
1681
1682
1683 #else
1684 noise_power = noise_power/2;
1685
1686 if ((reg&0x30)==0x00) //2K
1687 {
1688 if (noise_power<1512)
1689 snr = 0;
1690 else
1691 #ifdef MSOS_TYPE_LINUX
1692 snr = 10*log10f((float)noise_power/1512);
1693 #else
1694 snr = 10*Log10Approx((float)noise_power/1512);
1695 #endif
1696 }
1697 //else if ((reg&0x30)==0x10)//8K
1698 else
1699 {
1700 if (noise_power<6048)
1701 snr = 0;
1702 else
1703 #ifdef MSOS_TYPE_LINUX
1704 snr = 10*log10f((float)noise_power/6048);
1705 #else
1706 snr = 10*Log10Approx((float)noise_power/6048);
1707 #endif
1708 }
1709 /* ignore 4K
1710 else //4K
1711 {
1712 if (noise_power<3024)
1713 snr = 0;
1714 else
1715 snr = 10*Log10Approx(noise_power/3024);
1716 }
1717 */
1718 #endif
1719
1720 if (status == true)
1721 return snr;
1722 else
1723 return -1;
1724
1725 }
1726
1727 /****************************************************************************
1728 Subject: To check if Hierarchy on
1729 Function: INTERN_DVBT_Is_HierarchyOn
1730 Parmeter:
1731 Return: BOOLEAN
1732 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)1733 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
1734 {
1735 MS_U16 u16_tmp;
1736
1737 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
1738 return FALSE;
1739 //printf("u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
1740 if(u16_tmp&0x38)
1741 {
1742 return TRUE;
1743 }
1744 return FALSE;
1745 }
1746
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1747 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1748 {
1749 MS_U8 status = true;
1750 float ch_power_db = 0.0f;
1751 float ch_power_ref = 11.0f;
1752 float ch_power_rel = 0.0f;
1753 MS_U8 u8_index = 0;
1754 MS_U16 tps_info_qam,tps_info_cr;
1755
1756 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1757 {
1758 *strength = 0;
1759 return TRUE;
1760 }
1761 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
1762
1763 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
1764 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
1765 /* Actually, it's more reasonable, that signal level depended on cable input power level
1766 * thougth the signal isn't dvb-t signal.
1767 */
1768
1769 // use pointer of IFAGC table to identify
1770 // case 1: RFAGC from SAR, IFAGC controlled by demod
1771 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1772 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1773 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
1774 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1775 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1776 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
1777 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
1778
1779
1780 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
1781 printf("[dvbt]TPS qam parameter retrieve failure\n");
1782
1783 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
1784 printf("[dvbt]TPS cr parameter retrieve failure\n");
1785
1786
1787 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
1788 {
1789 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
1790 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
1791 {
1792 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
1793 break;
1794 }
1795 else
1796 {
1797 u8_index++;
1798 }
1799 }
1800
1801 if (ch_power_ref > 10.0f)
1802 *strength = 0;
1803 else
1804 {
1805 ch_power_rel = ch_power_db - ch_power_ref;
1806
1807 if ( ch_power_rel < -15.0f )
1808 {
1809 *strength = 0;
1810 }
1811 else if ( ch_power_rel < 0.0f )
1812 {
1813 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
1814 }
1815 else if ( ch_power_rel < 20 )
1816 {
1817 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
1818 }
1819 else if ( ch_power_rel < 35.0f )
1820 {
1821 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
1822 }
1823 else
1824 {
1825 *strength = 100;
1826 }
1827 }
1828
1829 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1830 {
1831 *strength = 0;
1832 return TRUE;
1833 }
1834
1835 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
1836 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
1837
1838 return status;
1839 }
1840
1841 /****************************************************************************
1842 Subject: To get the DVT Signal quility
1843 Function: INTERN_DVBT_GetSignalQuality
1844 Parmeter: Quility
1845 Return: E_RESULT_SUCCESS
1846 E_RESULT_FAILURE
1847 Remark: Here we have 4 level range
1848 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1849 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1850 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1851 <4>.4th Range => Quality <10
1852 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1853 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1854 {
1855 float ber_sqi;
1856 float fber;
1857 float cn_rec = 0;
1858 float cn_nordig_p1 = 0;
1859 float cn_rel = 0;
1860
1861 MS_U8 status = true;
1862 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
1863 MS_U16 u16_tmp;
1864
1865 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
1866
1867 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
1868 {
1869
1870 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1871 {
1872 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
1873 }
1874 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
1875 if(fViterbiBerFiltered<= 0.0)
1876 {
1877 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
1878 {
1879 DBG_INTERN_DVBT(printf("GetPostViterbiBer Fail!\n"));
1880 return FALSE;
1881 }
1882 fViterbiBerFiltered = fber;
1883 }
1884 else
1885 {
1886 fber = fViterbiBerFiltered;
1887 }
1888
1889 if (fber > 1.0E-3)
1890 ber_sqi = 0.0;
1891 else if (fber > 8.5E-7)
1892 #ifdef MSOS_TYPE_LINUX
1893 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
1894 #else
1895 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
1896 #endif
1897 else
1898 ber_sqi = 100.0;
1899
1900 cn_rec = INTERN_DVBT_GetSNR();
1901
1902 if (cn_rec == -1) //get SNR return fail
1903 status = false;
1904
1905 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
1906 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
1907 tps_cnstl = 0xff;
1908 tps_cr = 0xff;
1909 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
1910 tps_cnstl = (MS_U8)u16_tmp&0x07;
1911 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
1912 tps_cr = (MS_U8)u16_tmp&0x07;
1913
1914 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
1915 {
1916 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
1917 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
1918 {
1919 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
1920 break;
1921 }
1922 }
1923
1924 // 0,5, snr offset
1925 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
1926
1927 // patch....
1928 // Noridg SQI,
1929 // 64QAM, CR34, GI14, SNR 22dB.
1930 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
1931 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
1932 {
1933 cn_rel += 1.5f;
1934 }
1935
1936 if (cn_rel < -7.0f)
1937 {
1938 *quality = 0;
1939 }
1940 else if (cn_rel < 3.0)
1941 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
1942 else
1943 *quality = (MS_U16)ber_sqi;
1944 }
1945 else
1946 {
1947 *quality = 0;
1948 }
1949
1950 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
1951 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
1952 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
1953 return status;
1954 }
1955
1956 /****************************************************************************
1957 Subject: To get the Cell ID
1958 Function: INTERN_DVBT_Get_CELL_ID
1959 Parmeter: point to return parameter cell_id
1960
1961 Return: TRUE
1962 FALSE
1963 Remark:
1964 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)1965 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
1966 {
1967 MS_U8 status = true;
1968 MS_U8 value1=0;
1969 MS_U8 value2=0;
1970
1971 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
1972 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
1973
1974 *cell_id = ((MS_U16)value1<<8)|value2;
1975 return status;
1976 }
1977 /*
1978 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
1979 {
1980 #define SQI_LOOP_NUM 50
1981 U8 inn = 0;
1982 WORD sqi = 0;
1983 WORD ave_sqi = 0;
1984 WORD ave_num = 0;
1985 while(inn++<SQI_LOOP_NUM)
1986 {
1987 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
1988 {
1989 printf("[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
1990 ave_sqi+=sqi;
1991 ave_num++;
1992 }
1993 MsOS_DelayTask(50);
1994 }
1995
1996 if(ave_num != 0 )
1997 *quality = ave_sqi/ave_num;
1998
1999 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2000 }
2001 */
2002 /****************************************************************************
2003 Subject: To get the DVBT Carrier Freq Offset
2004 Function: INTERN_DVBT_Get_FreqOffset
2005 Parmeter: Frequency offset (in KHz), bandwidth
2006 Return: E_RESULT_SUCCESS
2007 E_RESULT_FAILURE
2008 Remark:
2009 *****************************************************************************/
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2010 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2011 {
2012 float N, FreqB;
2013 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2014 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2015 MS_U8 reg_frz=0, reg=0;
2016 MS_U8 status;
2017
2018 FreqB = (float)u8BW * 8 / 7;
2019
2020 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2021
2022 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2023
2024 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2025 RegCfoTd = reg;
2026
2027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2028 RegCfoTd = (RegCfoTd << 8)|reg;
2029
2030 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2031 RegCfoTd = (RegCfoTd << 8)|reg;
2032
2033 FreqCfoTd = (float)RegCfoTd;
2034
2035 if (RegCfoTd & 0x800000)
2036 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2037
2038 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2039
2040 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2041
2042 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2043 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2044
2045 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2046
2047 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2048 RegCfoFd = reg;
2049
2050 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2051 RegCfoFd = (RegCfoFd << 8)|reg;
2052
2053 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2054 RegCfoFd = (RegCfoFd << 8)|reg;
2055
2056 FreqCfoFd = (float)RegCfoFd;
2057
2058 if (RegCfoFd & 0x800000)
2059 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2060
2061 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2062
2063 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2064 RegIcfo = reg & 0x07;
2065
2066 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2067 RegIcfo = (RegIcfo << 8)|reg;
2068
2069 FreqIcfo = (float)RegIcfo;
2070
2071 if (RegIcfo & 0x400)
2072 FreqIcfo = FreqIcfo - (float)0x800;
2073
2074 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2075 reg = reg & 0x30;
2076
2077 switch (reg)
2078 {
2079 case 0x00: N = 2048; break;
2080 case 0x20: N = 4096; break;
2081 case 0x10:
2082 default: N = 8192; break;
2083 }
2084
2085 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2086 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2087 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2088 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2089 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2090 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2091 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2092 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2093 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2094 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2095
2096 if (status == TRUE)
2097 return TRUE;
2098 else
2099 return FALSE;
2100 }
2101
2102
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2103 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2104 {
2105
2106 bPowerOn = bPowerOn;
2107 }
2108
INTERN_DVBT_Power_Save(void)2109 MS_BOOL INTERN_DVBT_Power_Save(void)
2110 {
2111
2112 return TRUE;
2113 }
2114
2115 /****************************************************************************
2116 Subject: To get the DVBT constellation parameter
2117 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2118 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2119 Return: TRUE
2120 FALSE
2121 Remark: The TPS parameters will be available after TPS lock
2122 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2123 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2124 {
2125 MS_U8 tps_param;
2126
2127 //@@++ Arki 20100125
2128 if (eSignalType == TS_MODUL_MODE)
2129 {
2130 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2131 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2132 }
2133
2134 if (eSignalType == TS_CODE_RATE)
2135 {
2136 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2137 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2138 }
2139
2140 if (eSignalType == TS_GUARD_INTERVAL)
2141 {
2142 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2143 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2144 }
2145
2146 if (eSignalType == TS_FFX_VALUE)
2147 {
2148 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2149 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2150 }
2151 //@@-- Arki 20100125
2152 return TRUE;
2153 }
2154
INTERN_DVBT_Version(MS_U16 * ver)2155 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2156 {
2157
2158 MS_U8 status = true;
2159 MS_U8 tmp = 0;
2160 MS_U16 u16_INTERN_DVBT_Version;
2161
2162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2163 u16_INTERN_DVBT_Version = tmp;
2164 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2165 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2166 *ver = u16_INTERN_DVBT_Version;
2167
2168 return status;
2169 }
2170
INTERN_DVBT_Version_minor(MS_U8 * ver2)2171 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2172 {
2173
2174 MS_U8 status = true;
2175
2176 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2177
2178 return status;
2179 }
2180
2181
INTERN_DVBT_Show_Demod_Version(void)2182 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2183 {
2184
2185 MS_BOOL status = true;
2186 MS_U16 u16_INTERN_DVBT_Version;
2187 MS_U8 u8_minor_ver = 0;
2188
2189 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2190 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2191 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2192
2193 return status;
2194 }
2195
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2196 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2197 {
2198 MS_U8 u8_index = 0;
2199 MS_BOOL bRet = false;
2200
2201 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2202 {
2203 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2204 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2205 {
2206 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2207 bRet = true;
2208 break;
2209 }
2210 else
2211 {
2212 u8_index++;
2213 }
2214 }
2215 return bRet;
2216 }
2217
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2218 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2219 {
2220 MS_U8 u8_index = 0;
2221 MS_BOOL bRet = false;
2222
2223 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2224 {
2225 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2226 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2227 {
2228 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2229 bRet = true;
2230 break;
2231 }
2232 else
2233 {
2234 u8_index++;
2235 }
2236 }
2237 return bRet;
2238 }
2239
2240
2241 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2242 void INTERN_DVBT_get_demod_state(MS_U8* state)
2243 {
2244 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2245 return;
2246 }
2247
INTERN_DVBT_Show_ChannelLength(void)2248 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2249 {
2250 MS_U8 status = true;
2251 MS_U8 tmp = 0;
2252 MS_U16 len = 0;
2253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2254 len = tmp;
2255 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2256 len = (len<<8)|tmp;
2257 printf("[dvbt]Hw_channel=%d\n",len);
2258 return status;
2259 }
2260
INTERN_DVBT_Show_SW_ChannelLength(void)2261 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2262 {
2263 MS_U8 status = true;
2264 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2265 MS_U16 sw_len = 0;
2266 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2267 sw_len = tmp;
2268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2269 sw_len = (sw_len<<8)|tmp;
2270 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2271 peak_num = tmp;
2272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2273 insideGI = tmp&0x01;
2274 stoptracking = (tmp&0x02)>>1;
2275 flag_short_echo = (tmp&0x0C)>>2;
2276 fsa_mode = (tmp&0x30)>>4;
2277
2278 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2279 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2280
2281 return status;
2282 }
2283
INTERN_DVBT_Show_ACI_CI(void)2284 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2285 {
2286
2287 #define BIT4 0x10
2288 MS_U8 status = true;
2289 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2290
2291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2292 digACI = (tmp&BIT4)>>4;
2293
2294 // get flag_CI
2295 // 0: No interference
2296 // 1: CCI
2297 // 2: in-band ACI
2298 // 3: N+1 ACI
2299 // flag_ci = (tmp&0xc0)>>6;
2300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2301 flag_CI = (tmp&0xC0)>>6;
2302 td_coef = (tmp&0x0C)>>2;
2303
2304 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2305
2306 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2307
2308 return status;
2309 }
2310
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2311 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2312 {
2313 MS_U8 status = true;
2314 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2315 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2316 fd = tmp;
2317 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2318 ch_len = tmp;
2319 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2320 snr_sel = (tmp>>4)&0x03;
2321 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2322 pertone_num = tmp;
2323
2324 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2325
2326 return status;
2327 }
2328
INTERN_DVBT_Get_CFO(void)2329 MS_BOOL INTERN_DVBT_Get_CFO(void)
2330 {
2331
2332 float N = 0, FreqB = 0;
2333 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2334 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2335 MS_U8 reg_frz = 0, reg = 0;
2336 MS_U8 status = 0;
2337 MS_U8 u8BW = 8;
2338
2339 FreqB = (float)u8BW * 8 / 7;
2340
2341 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2342
2343 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2344
2345 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2346 RegCfoTd = reg;
2347
2348 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2349 RegCfoTd = (RegCfoTd << 8)|reg;
2350
2351 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2352 RegCfoTd = (RegCfoTd << 8)|reg;
2353
2354 FreqCfoTd = (float)RegCfoTd;
2355
2356 if (RegCfoTd & 0x800000)
2357 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2358
2359 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2360
2361 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2362
2363 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2364 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2365
2366 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2367
2368 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2369 RegCfoFd = reg;
2370
2371 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2372 RegCfoFd = (RegCfoFd << 8)|reg;
2373
2374 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2375 RegCfoFd = (RegCfoFd << 8)|reg;
2376
2377 FreqCfoFd = (float)RegCfoFd;
2378
2379 if (RegCfoFd & 0x800000)
2380 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2381
2382 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2383
2384 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2385 RegIcfo = reg & 0x07;
2386
2387 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2388 RegIcfo = (RegIcfo << 8)|reg;
2389
2390 FreqIcfo = (float)RegIcfo;
2391
2392 if (RegIcfo & 0x400)
2393 FreqIcfo = FreqIcfo - (float)0x800;
2394
2395 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2396 reg = reg & 0x30;
2397
2398 switch (reg)
2399 {
2400 case 0x00: N = 2048; break;
2401 case 0x20: N = 4096; break;
2402 case 0x10:
2403 default: N = 8192; break;
2404 }
2405
2406 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2407 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2408 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2409 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2410 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2411
2412 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2413
2414 return status;
2415
2416 }
INTERN_DVBT_Get_SFO(void)2417 MS_BOOL INTERN_DVBT_Get_SFO(void)
2418 {
2419 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2420 MS_BOOL status = true;
2421 MS_U8 reg = 0;
2422 float FreqB = 9.143, FreqS = 45.473; //20.48
2423 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2424 float sfo_value = 0;
2425
2426 // get Reg_TDP_SFO,
2427 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2428 Reg_TDP_SFO = reg;
2429 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2430 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2431 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2432 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2433
2434 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2435
2436 // get Reg_FDP_SFO,
2437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2438 Reg_FDP_SFO = reg;
2439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2440 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2442 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2443
2444 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2445
2446 // get Reg_FSA_SFO,
2447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2448 Reg_FSA_SFO = reg;
2449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2450 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2451 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2452 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2453
2454 // get Reg_FSA_IN,
2455 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2456 Reg_FSA_IN = reg;
2457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2458 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2459 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2460
2461 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2462 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2463
2464 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2465 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2466 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2467
2468
2469 return status;
2470 }
2471
INTERN_DVBT_Get_SYA_status(void)2472 void INTERN_DVBT_Get_SYA_status(void)
2473 {
2474 MS_U8 status = true;
2475 MS_U8 sya_k = 0,reg = 0;
2476 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2477
2478 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2479 sya_k = reg;
2480
2481 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2482 sya_th = reg;
2483 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2484 sya_th = (sya_th<<8)|reg;
2485
2486 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2487 sya_offset = reg;
2488 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2489 sya_offset = (sya_offset<<8)|reg;
2490
2491 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2492 len_m = reg;
2493 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2494 len_m = (len_m<<8)|reg;
2495
2496 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2497 len_b = reg;
2498 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2499 len_b = (len_b<<8)|reg;
2500
2501
2502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2503 len_a = reg;
2504 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2505 len_a = (len_a<<8)|reg;
2506
2507
2508 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2509 tracking_reg = reg;
2510
2511
2512 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2513 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2514
2515 return;
2516 }
2517
INTERN_DVBT_Get_cci_status(void)2518 void INTERN_DVBT_Get_cci_status(void)
2519 {
2520 MS_U8 status = true;
2521 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2522
2523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2524 cci_fsweep = reg;
2525
2526 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2527 cci_kp = reg;
2528
2529 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2530
2531 return;
2532 }
2533
INTERN_DVBT_Show_PRESFO_Info(void)2534 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2535 {
2536 MS_U8 tmp = 0;
2537 MS_BOOL status = TRUE;
2538 printf("\n[SFO]");
2539 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2540 printf("[%x]",tmp);
2541 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2542 printf("[%x]",tmp);
2543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2544 printf("[%x]",tmp);
2545 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2546 printf("[%x]",tmp);
2547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2548 printf("[%x]",tmp);
2549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2550 printf("[%x]",tmp);
2551 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2552 printf("[%x]",tmp);
2553 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2554 printf("[%x][End]",tmp);
2555
2556 return status;
2557 }
2558
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2559 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2560 {
2561 MS_BOOL status = true;
2562
2563 *locktime = 0xffff;
2564 printf("[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2565
2566 status = false;
2567 return status;
2568 }
2569
2570
INTERN_DVBT_Show_Lock_Time_Info(void)2571 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2572 {
2573 MS_U16 locktime = 0;
2574 MS_BOOL status = TRUE;
2575 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2576 printf("[DVBT]lock_time = %d ms\n",locktime);
2577 return status;
2578 }
2579
INTERN_DVBT_Show_BER_Info(void)2580 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2581 {
2582 MS_U8 tmp = 0;
2583 MS_BOOL status = TRUE;
2584 printf("\n[BER]");
2585 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2586 printf("[%x,",tmp);
2587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2588 printf("%x]",tmp);
2589 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2590 printf("[%x,",tmp);
2591 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2592 printf("%x]",tmp);
2593 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2594 printf("[%x,",tmp);
2595 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2596 printf("%x][End]",tmp);
2597
2598 return status;
2599
2600 }
2601
2602
INTERN_DVBT_Show_AGC_Info(void)2603 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2604 {
2605 MS_U8 tmp = 0;
2606 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2607 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2608 MS_U16 if_agc_err = 0;
2609 MS_BOOL status = TRUE;
2610 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2611
2612 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2614 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2615 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2616 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2617 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2618
2619
2620 // select IF gain to read
2621 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2622 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2623
2624 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2625 if_agc_gain = tmp;
2626 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2627 if_agc_gain = (if_agc_gain<<8)|tmp;
2628
2629
2630 // select d1 gain to read.
2631 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
2632 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
2633
2634 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
2635 d1_gain = tmp;
2636 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
2637 d1_gain = (d1_gain<<8)|tmp;
2638
2639 // select d2 gain to read.
2640 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
2641 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
2642
2643 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
2644 d2_gain = tmp;
2645 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
2646 d2_gain = (d2_gain<<8)|tmp;
2647
2648 // select IF gain err to read
2649 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2650 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
2651
2652 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2653 if_agc_err = tmp;
2654 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2655 if_agc_err = (if_agc_err<<8)|tmp;
2656
2657 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
2658 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
2659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
2660
2661
2662
2663 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2664 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2665
2666 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2667 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
2668
2669 return status;
2670
2671 }
2672
INTERN_DVBT_Show_WIN_Info(void)2673 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
2674 {
2675 MS_U8 tmp = 0;
2676 MS_U8 trigger = 0;
2677 MS_U16 win_len = 0;
2678
2679 MS_BOOL status = TRUE;
2680
2681 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
2682 win_len = tmp;
2683 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
2684 win_len = (win_len<<8)|tmp;
2685
2686 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
2687
2688 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
2689
2690 return status;
2691 }
2692
INTERN_DVBT_Show_td_coeff(void)2693 void INTERN_DVBT_Show_td_coeff(void)
2694 {
2695 MS_U8 status = true;
2696 MS_U8 w1 = 0,w2 = 0,reg = 0;
2697
2698 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
2699 w1 = reg;
2700
2701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
2702 w2 = reg;
2703
2704 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
2705
2706 return;
2707 }
2708
2709 /********************************************************
2710 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
2711 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
2712 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2713 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2714 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
2715 * FFT ( b14) : 0~1 => 2K, 8K
2716 ********************************/
INTERN_DVBT_Show_Modulation_info(void)2717 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
2718 {
2719 MS_U16 tps_info;
2720
2721 // printf("[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
2722
2723 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
2724 {
2725 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
2726 MS_U8 constel = tps_info&0x0007;
2727 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
2728 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
2729 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
2730 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
2731
2732 printf("tps=0x%x ",tps_info);
2733
2734 switch(fft)
2735 {
2736 case 0:
2737 printf("mode = 2K,");
2738 break;
2739 case 1:
2740 printf("mode = 8K,");
2741 break;
2742 default:
2743 printf("mode = unknow,");
2744 break;
2745 }
2746 switch(constel)
2747 {
2748 case 0:
2749 printf(" QPSK, ");
2750 break;
2751 case 1:
2752 printf("16QAM, ");
2753 break;
2754 case 2:
2755 printf("64QAM, ");
2756 break;
2757 default:
2758 printf("unknow QAM, ");
2759 break;
2760 }
2761 switch(gi)
2762 {
2763 case 0:
2764 printf("GI=1/32, ");
2765 break;
2766 case 1:
2767 printf("GI=1/16, ");
2768 break;
2769 case 2:
2770 printf("GI= 1/8, ");
2771 break;
2772 case 3:
2773 printf("GI= 1/4, ");
2774 break;
2775 default:
2776 printf("unknow GI, ");
2777 break;
2778 }
2779
2780 switch(hp_cr)
2781 {
2782 case 0:
2783 printf("HP_CR=1/2, ");
2784 break;
2785 case 1:
2786 printf("HP_CR=2/3, ");
2787 break;
2788 case 2:
2789 printf("HP_CR=3/4, ");
2790 break;
2791 case 3:
2792 printf("HP_CR=5/6, ");
2793 break;
2794 case 4:
2795 printf("HP_CR=7/8, ");
2796 break;
2797 default:
2798 printf("unknow hp_cr, ");
2799 break;
2800 }
2801
2802 switch(lp_cr)
2803 {
2804 case 0:
2805 printf("LP_CR=1/2, ");
2806 break;
2807 case 1:
2808 printf("LP_CR=2/3, ");
2809 break;
2810 case 2:
2811 printf("LP_CR=3/4, ");
2812 break;
2813 case 3:
2814 printf("LP_CR=5/6, ");
2815 break;
2816 case 4:
2817 printf("LP_CR=7/8, ");
2818 break;
2819 default:
2820 printf("unknow lp_cr, ");
2821 break;
2822 }
2823
2824 printf(" Hiearchy=0x%x\n",hiearchy);
2825
2826 // printf("\n");
2827 return TRUE;
2828 }
2829 else
2830 {
2831 printf("INVALID\n");
2832 return FALSE;
2833 }
2834 }
2835
2836
2837
2838
INTERN_DVBT_Show_BER_PacketErr(void)2839 void INTERN_DVBT_Show_BER_PacketErr(void)
2840 {
2841 float f_ber = 0;
2842 MS_U16 packetErr = 0;
2843 INTERN_DVBT_GetPostViterbiBer(&f_ber);
2844 INTERN_DVBT_GetPacketErr(&packetErr);
2845
2846 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
2847 return;
2848 }
2849
INTERN_DVBT_Show_Lock_Info(void)2850 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
2851 {
2852
2853 printf("[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
2854 return false;
2855 }
2856
2857
INTERN_DVBT_Show_Demod_Info(void)2858 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
2859 {
2860 MS_U8 demod_state = 0;
2861 MS_BOOL status = true;
2862 static MS_U8 counter = 0;
2863
2864 INTERN_DVBT_get_demod_state(&demod_state);
2865
2866 printf("==========[dvbt]state=%d\n",demod_state);
2867 if (demod_state < 5)
2868 {
2869 INTERN_DVBT_Show_Demod_Version();
2870 INTERN_DVBT_Show_AGC_Info();
2871 INTERN_DVBT_Show_ACI_CI();
2872 }
2873 else if(demod_state < 8)
2874 {
2875 INTERN_DVBT_Show_Demod_Version();
2876 INTERN_DVBT_Show_AGC_Info();
2877 INTERN_DVBT_Show_ACI_CI();
2878 INTERN_DVBT_Show_ChannelLength();
2879 INTERN_DVBT_Get_CFO();
2880 INTERN_DVBT_Get_SFO();
2881 INTERN_DVBT_Show_td_coeff();
2882 }
2883 else if(demod_state < 11)
2884 {
2885 INTERN_DVBT_Show_Demod_Version();
2886 INTERN_DVBT_Show_AGC_Info();
2887 INTERN_DVBT_Show_ACI_CI();
2888 INTERN_DVBT_Show_ChannelLength();
2889 INTERN_DVBT_Get_CFO();
2890 INTERN_DVBT_Get_SFO();
2891 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
2892 INTERN_DVBT_Get_SYA_status();
2893 INTERN_DVBT_Show_td_coeff();
2894 }
2895 else if((demod_state == 11) && ((counter%4) == 0))
2896 {
2897 INTERN_DVBT_Show_Demod_Version();
2898 INTERN_DVBT_Show_AGC_Info();
2899 INTERN_DVBT_Show_ACI_CI();
2900 INTERN_DVBT_Show_ChannelLength();
2901 INTERN_DVBT_Get_CFO();
2902 INTERN_DVBT_Get_SFO();
2903 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
2904 INTERN_DVBT_Get_SYA_status();
2905 INTERN_DVBT_Show_td_coeff();
2906 INTERN_DVBT_Show_Modulation_info();
2907 INTERN_DVBT_Show_BER_PacketErr();
2908 }
2909 else
2910 status = false;
2911
2912 printf("===========================\n");
2913 counter++;
2914
2915 return status;
2916 }
2917 #endif
2918
2919