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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT2.c
98 /// @brief INTERN_DVBT2 DVBT2
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT2_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 //#include "BinInfo.h"
114 #include "drvDMD_VD_MBX.h"
115 #include "drvDMD_INTERN_DVBT2.h"
116 #include "halDMD_INTERN_DVBT2.h"
117 #include "halDMD_INTERN_common.h"
118
119 extern void *memcpy(void *destination, const void *source, size_t num);
120
121 #define TEST_EMBEDED_DEMOD 0
122 //U8 load_data_variable=1;
123 //-----------------------------------------------------------------------
124 #define BIN_ID_INTERN_DVBT2_DEMOD BIN_ID_INTERN_DVBT
125
126 #define TDE_REG_BASE 0x2400
127 #define DIV_REG_BASE 0x2500
128 #define TR_REG_BASE 0x2600
129 #define FTN_REG_BASE 0x2700
130 #define FTNEXT_REG_BASE 0x2800
131
132
133 #define INTERNAL_DVBT2_DRAM_OFFSET 0x5000
134 #define INTERNAL_DVBT2_FW_LEN (0x10000 - INTERNAL_DVBT2_DRAM_OFFSET)
135 #define INTERNAL_DVBT2_PS2XDATA_LEN 15
136
137
138 #if 0//ENABLE_SCAN_ONELINE_MSG
139 #define DBG_INTERN_DVBT2_ONELINE(x) x
140 #else
141 #define DBG_INTERN_DVBT2_ONELINE(x) // x
142 #endif
143
144 #ifdef MS_DEBUG
145 #define DBG_INTERN_DVBT2(x) x
146 #define DBG_GET_SIGNAL(x) x
147 #define DBG_INTERN_DVBT2_TIME(x) x
148 #define DBG_INTERN_DVBT2_LOCK(x) x
149 #else
150 #define DBG_INTERN_DVBT2(x) //x
151 #define DBG_GET_SIGNAL(x) //x
152 #define DBG_INTERN_DVBT2_TIME(x) // x
153 #define DBG_INTERN_DVBT2_LOCK(x) //x
154 #endif
155 #define DBG_DUMP_LOAD_DSP_TIME 0
156
157 #define INTERN_DVBT2_TS_SERIAL_INVERSION 0
158 #define INTERN_DVBT2_TS_PARALLEL_INVERSION 1
159 #define INTERN_DVBT2_DTV_DRIVING_LEVEL 1
160 #define INTERN_DVBT2_INTERNAL_DEBUG 1
161
162 #define SIGNAL_LEVEL_OFFSET 0.00
163 #define TAKEOVERPOINT -59.0
164 #define TAKEOVERRANGE 0.5
165 #define LOG10_OFFSET -0.21
166 #define INTERN_DVBT2_USE_SAR_3_ENABLE 0
167 #define INTERN_DVBT2_GET_TIME msAPI_Timer_GetTime0()
168 #define AUTO_TS_DATA_RATE 1
169
170 #if(AUTO_TS_DATA_RATE)
171 #define DBG_AUTO_TS_DATA_RATE(x)
172 #endif
173
174 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
175 #define TUNER_VPP 2
176 #define IF_AGC_VPP 2
177 #else
178 #define TUNER_VPP 1
179 #define IF_AGC_VPP 2
180 #endif
181
182 #if (TUNER_VPP == 1)
183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
184 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
186 #endif
187
188 /*BEG INTERN_DVBT2_DSPREG_TABLE*/
189 #define DVBT2_FS 24000
190
191 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
192 #define T2_BW_VAL 0x04
193 // FC: FC = FS = 5000 = 0x1388 (5.0MHz IF)
194 #define T2_FC_L_VAL 0x88 // 5.0M
195 #define T2_FC_H_VAL 0x13
196 #define T2_TS_SERIAL_VAL 0x00
197 #define T2_TS_CLK_RATE_VAL 0x06
198 #define T2_TS_OUT_INV_VAL 0x00
199 #define T2_TS_DATA_SWAP_VAL 0x00
200 #define T2_IF_AGC_INV_PWM_EN_VAL 0x00
201 #define T2_LITE_VAL 0x00
202 #define T2_AGC_REF_VAL 0x40
203
204 //#define DVBT2_BER_TH_HY 0.1
205
206 /*END INTERN_DVBT2_DSPREG_TABLE*/
207 //-----------------------------------------------------------------------
208 /****************************************************************
209 *Local Variables *
210 ****************************************************************/
211 static MS_BOOL bFECLock=0;
212 static MS_BOOL bP1Lock = 0;
213 static MS_U32 u32ChkScanTimeStart = 0;
214 static MS_U32 u32FecFirstLockTime=0;
215 static MS_U32 u32FecLastLockTime=0;
216 //static float fLDPCBerFiltered=-1;
217 //static float fBerFilteredDVBT2 = -1.0;
218
219 //Global Variables
220 //S_CMDPKTREG gsCmdPacket;
221 //U8 gCalIdacCh0, gCalIdacCh1;
222 extern MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
223 extern MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
224 extern MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
225 extern MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
226 extern MS_U32 u32DMD_DVBT2_FW_START_ADDR;
227
228 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
229 MS_U8 INTERN_DVBT2_table[] = {
230 #include "fwDMD_INTERN_DVBT2.dat"
231 };
232
233 #endif
234 /*
235 static DMD_T2_SSI_DBM_NORDIGP1 dvbt2_ssi_dbm_nordigp1[] =
236 {
237 {_T2_QPSK, _T2_CR1Y2, -95.7},
238 {_T2_QPSK, _T2_CR3Y5, -94.4},
239 {_T2_QPSK, _T2_CR2Y3, -93.6},
240 {_T2_QPSK, _T2_CR3Y4, -92.6},
241 {_T2_QPSK, _T2_CR4Y5, -92.0},
242 {_T2_QPSK, _T2_CR5Y6, -91.5},
243
244 {_T2_16QAM, _T2_CR1Y2, -90.8},
245 {_T2_16QAM, _T2_CR3Y5, -89.1},
246 {_T2_16QAM, _T2_CR2Y3, -87.9},
247 {_T2_16QAM, _T2_CR3Y4, -86.7},
248 {_T2_16QAM, _T2_CR4Y5, -85.8},
249 {_T2_16QAM, _T2_CR5Y6, -85.2},
250
251 {_T2_64QAM, _T2_CR1Y2, -86.9},
252 {_T2_64QAM, _T2_CR3Y5, -84.6},
253 {_T2_64QAM, _T2_CR2Y3, -83.2},
254 {_T2_64QAM, _T2_CR3Y4, -81.4},
255 {_T2_64QAM, _T2_CR4Y5, -80.3},
256 {_T2_64QAM, _T2_CR5Y6, -79.7},
257
258 {_T2_256QAM, _T2_CR1Y2, -83.5},
259 {_T2_256QAM, _T2_CR3Y5, -80.4},
260 {_T2_256QAM, _T2_CR2Y3, -78.6},
261 {_T2_256QAM, _T2_CR3Y4, -76.0},
262 {_T2_256QAM, _T2_CR4Y5, -74.4},
263 {_T2_256QAM, _T2_CR5Y6, -73.3},
264 {_T2_QAM_UNKNOWN, _T2_CR_UNKNOWN, 0.0}
265 };
266 */
267
268 /*
269 static float dvbt2_ssi_dbm_nordigp1[][6] =
270 {
271 { -95.7, -94.4, -93.6, -92.6, -92.0, -91.5},
272 { -90.8, -89.1, -87.9, -86.7, -85.8, -85.2},
273 { -86.9, -84.6, -83.2, -81.4, -80.3, -79.7},
274 { -83.5, -80.4, -78.6, -76.0, -74.4, -73.3},
275 };
276
277 // cr, 3/5(1), 2/3(2), 3/4 (3)
278 float fT2_SSI_formula[][12]=
279 {
280 {1.0/5, 97.0, 3.0/2, 82.0, 16.0/5, 50.0, 29.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/5
281 {2.0/3, 95.0, 9.0/5, 77.0, 17.0/5, 43.0, 14.0/5.0, 15.0, 13.0/15, 2.0, 2.0/5, 0.0}, // CR2/3
282 {1.0/2, 93.0, 19.0/10, 74.0, 31.0/10, 43.0, 22.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/4
283 };
284 */
285
286 //static void INTERN_DVBT2_SignalQualityReset(void);
287 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void);
288
289 #if (AUTO_TS_DATA_RATE)
290 MS_BOOL INTERN_DVBT2_GetTsDivNum(MS_U8* u8TSDivNum);
291 MS_BOOL INTERN_DVBT2_ConfigAdaptiveTsDivNum(void);
292 #endif
293
294 #if 0
295 static void INTERN_DVBT2_SignalQualityReset(void)
296 {
297 u32FecFirstLockTime=0;
298 fLDPCBerFiltered=-1;
299 }
300 #endif
301
INTERN_DVBT2_DSPReg_Init(const MS_U8 * u8DVBT2_DSPReg,MS_U8 u8Size)302 MS_BOOL INTERN_DVBT2_DSPReg_Init(const MS_U8 *u8DVBT2_DSPReg, MS_U8 u8Size)
303 {
304 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
305 MS_BOOL status = TRUE;
306 MS_U16 u16DspAddr = 0;
307
308 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_DSPReg_Init\n"));
309
310 //for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
311 // status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
312 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_BW, T2_BW_VAL) != TRUE)
313 {
314 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
315 }
316 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_L, T2_FC_L_VAL) != TRUE)
317 {
318 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
319 }
320 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_H, T2_FC_H_VAL) != TRUE)
321 {
322 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
323 }
324 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_SERIAL, T2_TS_SERIAL_VAL) != TRUE)
325 {
326 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
327 }
328 //if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_CLK_RATE, T2_TS_CLK_RATE_VAL) != TRUE)
329 //{
330 // printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
331 //}
332 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_OUT_INV, T2_TS_OUT_INV_VAL) != TRUE)
333 {
334 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
335 }
336 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_SWAP, T2_TS_DATA_SWAP_VAL) != TRUE)
337 {
338 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
339 }
340 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_IF_AGC_INV_PWM_EN, T2_IF_AGC_INV_PWM_EN_VAL) != TRUE)
341 {
342 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
343 }
344 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_LITE, T2_LITE_VAL) != TRUE)
345 {
346 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
347 }
348
349 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_AGC_REF, T2_AGC_REF_VAL) != TRUE) //brown:0x40->agc_ref
350 {
351 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
352 }
353
354 if (u8DVBT2_DSPReg != NULL)
355 {
356 /*temp solution until new dsp table applied.*/
357 // if (INTERN_DVBT2_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
358 if (u8DVBT2_DSPReg[0] >= 1)
359 {
360 u8DVBT2_DSPReg+=2;
361 for (idx = 0; idx<u8Size; idx++)
362 {
363 u16DspAddr = *u8DVBT2_DSPReg;
364 u8DVBT2_DSPReg++;
365 u16DspAddr = (u16DspAddr) + ((*u8DVBT2_DSPReg)<<8);
366 u8DVBT2_DSPReg++;
367 u8Mask = *u8DVBT2_DSPReg;
368 u8DVBT2_DSPReg++;
369 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
370 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT2_DSPReg) & (u8Mask));
371 u8DVBT2_DSPReg++;
372 DBG_INTERN_DVBT2(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
373 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
374 }
375 }
376 else
377 {
378 printf("FATAL: parameter version incorrect\n");
379 }
380 }
381
382 return status;
383 }
384
385 /***********************************************************************************
386 Subject: SoftStop
387 Function: INTERN_DVBT2_SoftStop
388 Parmeter:
389 Return: MS_BOOL
390 Remark:
391 ************************************************************************************/
392
INTERN_DVBT2_SoftStop(void)393 MS_BOOL INTERN_DVBT2_SoftStop ( void )
394 {
395 MS_U16 u8WaitCnt=0;
396 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
397 {
398 printf(">> MB Busy!\n");
399 return FALSE;
400 }
401
402 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
403
404 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
405 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
406
407 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
408 {
409 if (u8WaitCnt++ >= 0xFFF)
410 {
411 printf(">> DVBT2 SoftStop Fail!\n");
412 return FALSE;
413 }
414 }
415
416 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
417 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
418 return TRUE;
419 }
420
INTERN_DVBT2_SoftReset(void)421 MS_BOOL INTERN_DVBT2_SoftReset ( void )
422 {
423 MS_BOOL bRet=TRUE;
424 //MS_U8 u8Data, fdp_fifo_done, djb_fifo_done, tdi_fifo_done;
425 MS_U8 u8Data = 0, fdp_fifo_done = 0, tdi_fifo_done = 0;
426 MS_U8 u8_timeout = 0;
427
428 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_SoftReset\n"));
429
430 //stop FSM_EN
431 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN
432
433 MsOS_DelayTask(5);
434
435 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
436 DBG_INTERN_DVBT2(printf("@@@TOP_RESET:0x%x\n", u8Data));
437 // MIU hold function
438 if((u8Data & 0x20) == 0x00)
439 {
440 // mask miu service with fdp, djb, tdi
441 //fdp 0x17 [12] reg_fdp_fifo_stop=1'b1
442 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
443 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10));
444 // [8] reg_fdp_load, fdp register dynamic change protection, 1->load register
445 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10);
446 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
447 //printf("@@@@@@ DVBT2 [reg_fdp_fifo_stop]=0x%x\n", u8Data);
448 //djb 0x65 [0] reg_stop_mu_request
449 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
450 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01));
451 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
452 //printf("@@@@@@ DVBT2 [reg_stop_mu_request]=0x%x\n", u8Data);
453 //snr 0x23 [8] reg_tdi_miu_off
454 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
455 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01));
456 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
457 //printf("@@@@@@ DVBT2 [reg_tdi_miu_off]=0x%x\n", u8Data);
458 // ---------------------------------------------
459 // Wait MIU mask or timeout!
460 // DVBT2_TIMER_INT[ 7:0] : indicator of the selected Timer's max count(15:8) (r)
461 // DVBT2_TIMER_INT[11:8] : timer3~timer0 interrupt (r)
462 // ---------------------------------------------
463 //fdp 0x18 [2] reg_fdp_fifo_req_done
464 //djb 0x65 [8] reg_miu_req_terminate_done
465 //tdi 0x23 [9] reg_tdi_miu_off_done
466 do
467 {
468 // Wait MIU mask done or timeout!
469 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data);
470 fdp_fifo_done = u8Data & 0x04;
471 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2)+1, &u8Data);
472 //djb_fifo_done = u8Data & 0x01;
473 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
474 tdi_fifo_done = u8Data & 0x02;
475
476 u8_timeout++;
477 }
478 //while(((fdp_fifo_done != 0x04)||(djb_fifo_done != 0x01)||(tdi_fifo_done != 0x02))
479 while(((fdp_fifo_done != 0x04)||(tdi_fifo_done != 0x02))
480 && u8_timeout != 0x7f);
481
482 //printf(">> DVBT2 fdp_fifo_done=%d, djb_fifo_done=%d, tdi_fifo_done=%d \n", fdp_fifo_done, djb_fifo_done, tdi_fifo_done);
483 printf(">> DVBT2 [fdp_fifo_done]=%d, [tdi_fifo_done]=%d \n", fdp_fifo_done, tdi_fifo_done);
484
485 MsOS_DelayTask(2);
486
487 if(u8_timeout == 0x7f)
488 {
489 printf(">> DVBT2 MIU hold function Fail!\n");
490 //return FALSE;
491 }
492 else
493 {
494 printf(">> DVBT2 MIU hold function done!!\n");
495 }
496 }
497 else
498 printf(">> No need DVBT2 MIU hold function!!\n");
499
500 // demod_top reset
501 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
502 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data|0x20));
503
504 MsOS_DelayTask(1);
505
506 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data&(~0x20)));
507
508 DBG_INTERN_DVBT2(printf("@INTERN_DVBT2_SoftReset done!!\n"));
509
510 return bRet;
511 }
512
513
514 /***********************************************************************************
515 Subject: Reset
516 Function: INTERN_DVBT2_Reset
517 Parmeter:
518 Return: MS_BOOL
519 Remark:
520 ************************************************************************************/
521 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT2_Reset(void)522 MS_BOOL INTERN_DVBT2_Reset ( void )
523 {
524 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_reset\n"));
525
526 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Reset, t = %ld\n",MsOS_GetSystemTime()));
527
528 //INTERN_DVBT2_SoftStop();
529
530
531 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
532 MsOS_DelayTask(5);
533 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
534
535 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
536 MsOS_DelayTask(5);
537
538 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
539 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
540
541 bFECLock = FALSE;
542 bP1Lock = FALSE;
543 u32ChkScanTimeStart = MsOS_GetSystemTime();
544 return TRUE;
545 }
546
547 /***********************************************************************************
548 Subject: Exit
549 Function: INTERN_DVBT2_Exit
550 Parmeter:
551 Return: MS_BOOL
552 Remark:
553 ************************************************************************************/
INTERN_DVBT2_Exit(void)554 MS_BOOL INTERN_DVBT2_Exit ( void )
555 {
556 MS_U8 status = true;
557
558 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_Exit\n"));
559
560 status &= INTERN_DVBT2_SoftStop();
561
562 // SRAM End Address
563 HAL_DMD_RIU_WriteByte(0x111707,0xff);
564 HAL_DMD_RIU_WriteByte(0x111706,0xff);
565
566 // DRAM Disable
567 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
568
569
570 //diable clk gen
571 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
572 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
573 /*
574 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
575 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
576
577 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
578 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
579
580 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
581 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
582
583 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
584 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
585
586 HAL_DMD_RIU_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
587 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
588
589 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
590 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
591
592 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
593 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
594
595 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
596 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
597
598 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
599 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
600
601 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
602 */
603 return status;
604 }
605 /*
606 MS_BOOL INTERN_DVBT2_Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length)
607 {
608
609 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Load2Sdram, len=0x%x, \n",data_length));
610 MS_U8 addrhi, addrlo;
611 int i, j, k, old_i=0;
612 int sdram_start_addr = 0;//1024 >> 2; //StrToInt(ed_sdram_start->Text)>>2; // 4KB alignment
613
614 //I2C_CH_Exit(); // exit CH4
615 //I2C_CH5_Reset(); // switch to CH5
616 //MDrv_DMD_I2C_Channel_Change(5);
617 //--------------------------------------------------------------------------
618 // Set xData map for DRAM
619 //--------------------------------------------------------------------------
620
621 //banknum = 0x1d; //dmdmcu51_xdmiu
622
623 //set xData map upper and low bound for 64k DRAM window
624 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x2020);
625 if(SLAVE_I2CWrite16(banknum,0x63,0x2020)==false)
626 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
627
628 //set xData map offset for 64k DRAM window
629 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x64, 0x0000);
630 if(SLAVE_I2CWrite16(banknum,0x64,0x0000)==false)
631 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
632
633 //set xData map upper and low bound for 4k DRAM window
634 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x65, 0x2420);
635 if(SLAVE_I2CWrite16(banknum,0x65,0x2420)==false)
636 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
637
638 //set xData map offset for 4k DRAM window
639 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, sdram_start_addr);
640 if(SLAVE_I2CWrite16(banknum,0x66,sdram_start_addr)==false)
641 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
642
643 //I2C_CH_Exit(); // exit CH5
644 //EnterDebugMode(1); // switch to CH1
645
646 //enable xData map for DRAM
647 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x0007);
648 if(SLAVE_I2CWrite16(banknum,0x62,0x0007)==false)
649 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
650
651
652 for ( i = 0, j = SDRAM_BASE, k = sdram_start_addr + 0x01; i < size;)
653 {
654 if (j == SDRAM_BASE + 0x1000)
655 {
656 //I2C_CH_Exit(); // exit CH1
657 //I2C_CH5_Reset(); // switch to CH5
658 //set xData map offset for 4k DRAM window
659 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, k++);
660 if(SLAVE_I2CWrite16(banknum,0x66,k++)==false)
661 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
662 j = SDRAM_BASE;
663
664 //I2C_CH_Exit(); // exit CH5
665 //EnterDebugMode(1); // switch to CH1
666
667 }
668
669 addrhi = (j >> 8) & 0xff;
670 addrlo = j & 0xff;
671
672 if (i+EZUSB_Write_Buffer<size)
673 {
674 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,EZUSB_Write_Buffer)==FALSE)
675 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
676
677 j=j+EZUSB_Write_Buffer;
678 i=i+EZUSB_Write_Buffer;
679 }
680 else
681 {
682 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,size-i)==FALSE)
683 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
684
685 i=size;
686 }
687
688 if ((i-old_i)>=2048)
689 {
690 ShowMCUDL_Progress(0,3*i,size);
691 old_i=i;
692 }
693 }//end for
694
695
696 FWDLRichEdit->Lines->Add(">SDRAM Down Load OK!");
697
698 I2C_CH_Exit(); // exit CH1
699 I2C_CH5_Reset(); // switch to CH5
700
701 //--------------------------------------------------------------------------
702 // Release xData map for SDRAM
703 //--------------------------------------------------------------------------
704
705 if(SLAVE_I2CWrite16(banknum,0x62,0x0000)==false)
706 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
707
708 }
709 */
710 /***********************************************************************************
711 Subject: Load DSP code to chip
712 Function: INTERN_DVBT2_LoadDSPCode
713 Parmeter:
714 Return: MS_BOOL
715 Remark:
716 ************************************************************************************/
INTERN_DVBT2_LoadDSPCode(void)717 static MS_BOOL INTERN_DVBT2_LoadDSPCode(void)
718 {
719 MS_U8 u8data = 0x00;
720 MS_U16 i;
721 MS_U16 fail_cnt=0;
722 //MS_U16 u16AddressOffset;
723 MS_U32 u32VA_DramCodeAddr;
724
725 #if (DBG_DUMP_LOAD_DSP_TIME==1)
726 MS_U32 u32Time;
727 #endif
728
729
730 #ifndef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
731 BININFO BinInfo;
732 MS_BOOL bResult;
733 MS_U32 u32GEAddr;
734 MS_U8 Data;
735 MS_S8 op;
736 MS_U32 srcaddr;
737 MS_U32 len;
738 MS_U32 SizeBy4K;
739 MS_U16 u16Counter=0;
740 MS_U8 *pU8Data;
741 #endif
742
743 #if 0
744 if(HAL_DMD_RIU_ReadByte(0x101E3E))
745 {
746 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
747 return FALSE;
748 }
749 #endif
750
751 // MDrv_Sys_DisableWatchDog();
752
753
754 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
755 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
756 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
757 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
758 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
759 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
760
761 //// Load code thru VDMCU_IF ////
762 DBG_INTERN_DVBT2(printf(">Load Code...\n"));
763 //#ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
764 //for ( i = 0; i < sizeof(INTERN_DVBT2_table); i++)
765 //{
766 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
767 //}
768 if (sizeof(INTERN_DVBT2_table) < 0x8000)
769 {
770 printf("----->Bin file Size is not match...\n");
771 }
772 else
773 {
774 // load half code to SRAM
775 for ( i = 0; i < 0x8000; i++)
776 {
777 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
778 }
779 DBG_INTERN_DVBT2(printf(">Load SRAM code done...\n"));
780
781
782 if((u32DMD_DVBT2_FW_START_ADDR & 0x5000) != 0x5000)
783 {
784 for(i=0; i<50; i++)
785 {
786 printf(">DVB-T2 DRAM Start address is not correct!!\n");
787 }
788
789 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%x \n", u32DMD_DVBT2_EQ_START_ADDR);
790 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%x \n", u32DMD_DVBT2_TDI_START_ADDR);
791 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%x \n", u32DMD_DVBT2_DJB_START_ADDR);
792 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%x \n", u32DMD_DVBT2_FW_START_ADDR);
793 }
794 else
795 {
796 // load another half code to SDRAM
797 // VA = MsOS_PA2KSEG1(PA); //NonCache
798 DBG_INTERN_DVBT2(printf(">>> DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
799 u32VA_DramCodeAddr = MsOS_PA2KSEG1(u32DMD_DVBT2_FW_START_ADDR);
800 memcpy((void*)(MS_VIRT)u32VA_DramCodeAddr, &INTERN_DVBT2_table[0x8000], sizeof(INTERN_DVBT2_table) - 0x8000);
801
802 DBG_INTERN_DVBT2(printf(">Load DRAM code done...\n"));
803 }
804 }
805
806 //#endif
807
808 //// Content verification ////
809 DBG_INTERN_DVBT2(printf(">Verify Code...\n"));
810
811 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
812 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
813
814 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
815 for ( i = 0; i < 0x8000; i++)
816 {
817 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
818 if (u8data != INTERN_DVBT2_table[i])
819 {
820 printf(">fail add = 0x%x\n", i);
821 printf(">code = 0x%x\n", INTERN_DVBT2_table[i]);
822 printf(">data = 0x%x\n", u8data);
823
824 if (fail_cnt++ > 10)
825 {
826 printf(">DVB-T2 DSP SRAM Loadcode fail!\n");
827 return false;
828 }
829 }
830 }
831 #else
832 for (i=0;i<=SizeBy4K;i++)
833 {
834 if(i==SizeBy4K)
835 len=BinInfo.B_Len%0x1000;
836 else
837 len=0x1000;
838
839 srcaddr = u32GEAddr+(0x1000*i);
840 //printf("\t i = %08LX\n", i);
841 //printf("\t len = %08LX\n", len);
842 op = 1;
843 u16Counter = 0 ;
844 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
845 while(len--)
846 {
847 u16Counter ++ ;
848 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
849 //pU8Data = (U8 *)(srcaddr|0x80000000);
850 #if OBA2
851 pU8Data = (U8 *)(srcaddr);
852 #else
853 pU8Data = (U8 *)(srcaddr|0x80000000);
854 #endif
855 Data = *pU8Data;
856
857 #if 0
858 if(u16Counter < 0x100)
859 printf("0x%bx,", Data);
860 #endif
861 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
862 if (u8data != Data)
863 {
864 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
865 printf(">code = 0x%x\n", Data);
866 printf(">data = 0x%x\n", u8data);
867
868 if (fail_cnt++ > 10)
869 {
870 printf(">DVB-T DSP Loadcode fail!");
871 return false;
872 }
873 }
874
875 srcaddr += op;
876 }
877 // printf("\n\n\n");
878 }
879 #endif
880
881 // add T2 DRAM bufer start address into fixed location
882 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
883 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
884
885 // write Start address to VD MCU 51 code sram
886 // //0x30~0x33
887 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR);
888 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 8));
889 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 16));
890 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 24));
891 //0x30~0x33
892 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_EQ_START_ADDR);
893 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 8));
894 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 16));
895 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 24));
896 //0x34~0x37
897 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_TDI_START_ADDR);
898 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 8));
899 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 16));
900 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 24));
901 //0x38~0x3b
902 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_DJB_START_ADDR);
903 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 8));
904 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 16));
905 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 24));
906 //0x3c~0x3f
907 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_FW_START_ADDR);
908 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 8));
909 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 16));
910 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 24));
911
912 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR));
913 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR));
914 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR));
915 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
916
917 #if 0
918 // DEBUG
919 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
920 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
921
922 // for ( i = 0; i < 16; i++)
923 // {
924 // u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
925 // printf(">add = 0x%x\t", i);
926 // printf(">data = 0x%x\n", u8data);
927 // }
928
929 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR);
930 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR);
931 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR);
932 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR);
933 #endif
934
935 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
936 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
937 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
938 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
939
940 DBG_INTERN_DVBT2(printf(">DSP Loadcode done."));
941 //while(load_data_variable);
942
943 return TRUE;
944 }
945
946 /***********************************************************************************
947 Subject: DVB-T CLKGEN initialized function
948 Function: INTERN_DVBT2_Power_On_Initialization
949 Parmeter:
950 Return: MS_BOOL
951 Remark:
952 ************************************************************************************/
INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)953 void INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)
954 {
955 MS_U8 temp_val;
956 MS_U16 u16_temp_val;
957
958 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_InitClkgen\n"));
959
960 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
961 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
962 // ----------------------------------------------
963 // start demod CLKGEN setting
964 // ----------------------------------------------
965 // *** Set register at CLKGEN1
966 // enable DMD MCU clock "bit[0] set 0"
967 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
968 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
969 // CLK_DMDMCU clock setting
970 // [0] disable clock
971 // [1] invert clock
972 // [4:2]
973 // 000:170 MHz(MPLL_DIV_BUf)
974 // 001:160MHz
975 // 010:144MHz
976 // 011:123MHz
977 // 100:108MHz
978 // 101:mem_clcok
979 // 110:mem_clock div 2
980 // 111:select XTAL
981 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
982 // HAL_DMD_RIU_WriteByte(0x10331e,0x1c); // 24MHz
983 HAL_DMD_RIU_WriteByte(0x10331e,0x10); // 108MHz
984
985 // set parallet ts clock
986 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
987 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
988 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0615
989 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
990 temp_val|=0x05;
991 // temp_val|=0x07;
992 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
993
994 HAL_DMD_RIU_WriteByte(0x103300,0x10);
995
996 // enable DVBTC ts clock
997 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
998 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
999 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1000 HAL_DMD_RIU_WriteByte(0x103308,0x00);
1001
1002 // enable dvbc adc clock
1003 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1004 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1005 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1006 HAL_DMD_RIU_WriteByte(0x103314,0x00);
1007
1008 // [Maxim] enable ADCI clock & ADCQ clock
1009 // h0010 h0010 3 0 reg_ckg_dvbtc_adc_i 3 0 4 h1
1010 // h0010 h0010 11 8 reg_ckg_dvbtc_adc_q 3 0 4 h1
1011 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
1012 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
1013 HAL_DMD_RIU_WriteByte(0x103321,0x00);
1014 HAL_DMD_RIU_WriteByte(0x103320,0x00);
1015
1016 // ----------------------------------------------
1017 // start demod_0 CLKGEN setting
1018 // ----------------------------------------------
1019
1020 // enable clk_atsc_adcd_sync
1021 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1022 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1023 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1024 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1025
1026 //reg_ckg_dvbt_inner
1027 HAL_DMD_RIU_WriteByte(0x111f21,0x11);
1028 HAL_DMD_RIU_WriteByte(0x111f20,0x10);
1029
1030 //reg_ckg_dvbt_outer
1031 HAL_DMD_RIU_WriteByte(0x111f23,0x01);
1032 HAL_DMD_RIU_WriteByte(0x111f22,0x11);
1033
1034 //reg_ckg_acifir
1035 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
1036
1037 //reg_ckg_dvbtm_sram_t1o2x_t22x
1038 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
1039 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
1040
1041 //reg_ckg_dvbtm_sram_adc_t22x
1042 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
1043 HAL_DMD_RIU_WriteByte(0x111f2c,0x01);
1044
1045 //reg_ckg_dvbtm_sram_t12x_t24x
1046 HAL_DMD_RIU_WriteByte(0x111f2f,0x00);
1047 HAL_DMD_RIU_WriteByte(0x111f2e,0x00);
1048
1049 //reg_ckg_dvbtm_ts_in
1050 HAL_DMD_RIU_WriteByte(0x111f31,0x04);
1051 HAL_DMD_RIU_WriteByte(0x111f30,0x00);
1052
1053 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
1054 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
1055
1056 HAL_DMD_RIU_WriteByte(0x111f35,0x00);
1057 HAL_DMD_RIU_WriteByte(0x111f34,0x00);
1058
1059 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
1060 HAL_DMD_RIU_WriteByte(0x111f36,0x00);
1061
1062 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
1063 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
1064
1065 HAL_DMD_RIU_WriteByte(0x111f3d,0x00);
1066 HAL_DMD_RIU_WriteByte(0x111f3c,0x00);
1067
1068 HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1069 HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1070
1071 HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1072 HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1073
1074 HAL_DMD_RIU_WriteByte(0x111fe1,0x00);
1075 HAL_DMD_RIU_WriteByte(0x111fe0,0x00);
1076
1077 HAL_DMD_RIU_WriteByte(0x111fe3,0x00);
1078 HAL_DMD_RIU_WriteByte(0x111fe2,0x00);
1079
1080 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1081 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1082
1083 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1084 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1085
1086 HAL_DMD_RIU_WriteByte(0x111fe9,0x00);
1087 HAL_DMD_RIU_WriteByte(0x111fe8,0x00);
1088
1089 HAL_DMD_RIU_WriteByte(0x111feb,0xc8);
1090 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1091
1092 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1093 HAL_DMD_RIU_WriteByte(0x111fec,0x0c);
1094
1095 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1096 HAL_DMD_RIU_WriteByte(0x111fee,0x00);
1097
1098 // Maserati special
1099 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1100 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1101
1102 HAL_DMD_RIU_WriteByte(0x111ff0,0x00);
1103
1104 // Mulan special
1105 // TEQ CLK for DVBT2
1106 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1107
1108 // SRAM share
1109 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
1110 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
1111
1112 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1113 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1114
1115 HAL_DMD_RIU_WriteByte(0x111f79,0x00);
1116 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
1117
1118 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
1119 HAL_DMD_RIU_WriteByte(0x111f7a,0x00);
1120
1121 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
1122 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
1123
1124 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
1125 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
1126
1127 // 32+4K xdata sram
1128 HAL_DMD_RIU_WriteByte(0x1117e0,(0x21+INTERNAL_DVBT2_PS2XDATA_LEN-1));
1129 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
1130 HAL_DMD_RIU_WriteByte(0x1117e4,(INTERNAL_DVBT2_PS2XDATA_LEN-2));
1131 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
1132
1133 // SRAM allocation
1134 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1135 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1136
1137 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1138 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1139
1140 HAL_DMD_RIU_WriteByte(0x111703,0x00);
1141 HAL_DMD_RIU_WriteByte(0x111702,0x00);
1142
1143 HAL_DMD_RIU_WriteByte(0x111707,(INTERNAL_DVBT2_DRAM_OFFSET-1)>>8);
1144 HAL_DMD_RIU_WriteByte(0x111706,(INTERNAL_DVBT2_DRAM_OFFSET-1)&0xff);
1145
1146 // SDRAM address offset
1147 u16_temp_val = (MS_U16)(u32DMD_DVBT2_FW_START_ADDR>>16);
1148 HAL_DMD_RIU_WriteByte(0x11171b,(MS_U8)(u16_temp_val>>8));
1149 HAL_DMD_RIU_WriteByte(0x11171a,(MS_U8)u16_temp_val);
1150
1151 // DRAM allocation
1152 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1153 HAL_DMD_RIU_WriteByte(0x111708,0x00);
1154
1155 HAL_DMD_RIU_WriteByte(0x11170d,INTERNAL_DVBT2_DRAM_OFFSET>>8);
1156 HAL_DMD_RIU_WriteByte(0x11170c,INTERNAL_DVBT2_DRAM_OFFSET&0xff);
1157
1158 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1159 HAL_DMD_RIU_WriteByte(0x11170a,0x00);
1160
1161 HAL_DMD_RIU_WriteByte(0x11170f,0xff);
1162 HAL_DMD_RIU_WriteByte(0x11170e,0xff);
1163
1164 // DRAM EN
1165 HAL_DMD_RIU_WriteByte(0x111718,0x04);
1166
1167 // [0]switch dram address mode:
1168 // 0: address from dmdmcu51 bank (old mode)
1169 // 1: address from dmdmcu51_top bank (new mode)
1170 HAL_DMD_RIU_WriteByte(0x11171c,0x01);
1171
1172 // ----------------------------------------------
1173 // start demod CLKGEN setting
1174 // ----------------------------------------------
1175 // select DMD MCU
1176 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1177 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1178 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1179
1180 // stream2miu_en, activate rst_wadr
1181 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1182 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1183 // stream2miu_en, turn off rst_wadr
1184 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1185
1186 }
1187
1188 /***********************************************************************************
1189 Subject: Power on initialized function
1190 Function: INTERN_DVBT2_Power_On_Initialization
1191 Parmeter:
1192 Return: MS_BOOL
1193 Remark:
1194 ************************************************************************************/
1195
INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT2_DSPRegInitExt,MS_U8 u8DMD_DVBT2_DSPRegInitSize)1196 MS_BOOL INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT2_DSPRegInitExt, MS_U8 u8DMD_DVBT2_DSPRegInitSize)
1197 {
1198 MS_U16 status = true;
1199
1200 // MS_U8 temp_val;
1201 //MS_U8 cData = 0;
1202 //U8 cal_done;
1203 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Power_On_Initialization\n"));
1204
1205 #if defined(PWS_ENABLE)
1206 Mapi_PWS_Stop_VDMCU();
1207 #endif
1208 // No definition for Mulan
1209 #if 0
1210 // Global demod reset. To fix DVBS -> DVBT2 or DVBS blind scan -> DVBT2 unlock issue.
1211 temp_val=HAL_DMD_RIU_ReadByte(0x101e3a);
1212 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val|0x02);
1213
1214 MsOS_DelayTask(1);
1215
1216 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val&(~0x02));
1217 #endif
1218
1219 INTERN_DVBT2_InitClkgen(bRFAGCTristateEnable);
1220 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1221 //// Firmware download //////////
1222 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Load DSP...\n"));
1223 //MsOS_DelayTask(100);
1224
1225 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1226 {
1227 if (INTERN_DVBT2_LoadDSPCode() == FALSE)
1228 {
1229 printf("DVB-T2 Load DSP Code Fail\n");
1230 return FALSE;
1231 }
1232 else
1233 {
1234 DBG_INTERN_DVBT2(printf("DVB-T2 Load DSP Code OK\n"));
1235 }
1236 }
1237
1238
1239 //// MCU Reset //////////
1240 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Reset...\n"));
1241 if (INTERN_DVBT2_Reset() == FALSE)
1242 {
1243 DBG_INTERN_DVBT2(printf("Fail\n"));
1244 return FALSE;
1245 }
1246 else
1247 {
1248 DBG_INTERN_DVBT2(printf("OK\n"));
1249 }
1250
1251 // SRAM setting, DVB-T use it.
1252 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1253 //MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1254 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1255
1256 status &= INTERN_DVBT2_DSPReg_Init(u8DMD_DVBT2_DSPRegInitExt, u8DMD_DVBT2_DSPRegInitSize);
1257 return status;
1258 }
1259
1260 /************************************************************************************************
1261 Subject: Driving control
1262 Function: INTERN_DVBT2_Driving_Control
1263 Parmeter: bInversionEnable : TRUE For High
1264 Return: void
1265 Remark:
1266 *************************************************************************************************/
INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)1267 void INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)
1268 {
1269 MS_U8 u8Temp;
1270
1271 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1272
1273 if (bEnable)
1274 {
1275 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1276 }
1277 else
1278 {
1279 u8Temp = u8Temp & (~0x01);
1280 }
1281
1282 DBG_INTERN_DVBT2(printf("---> INTERN_DVBT2_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1283 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1284 }
1285 /************************************************************************************************
1286 Subject: Clk Inversion control
1287 Function: INTERN_DVBT2_Clk_Inversion_Control
1288 Parmeter: bInversionEnable : TRUE For Inversion Action
1289 Return: void
1290 Remark:
1291 *************************************************************************************************/
INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)1292 void INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1293 {
1294 MS_U8 u8Temp;
1295
1296 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1297
1298 if (bInversionEnable)
1299 {
1300 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1301 }
1302 else
1303 {
1304 u8Temp = u8Temp & (~0x02);
1305 }
1306
1307 DBG_INTERN_DVBT2(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1308 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1309 }
1310 /************************************************************************************************
1311 Subject: Transport stream serial/parallel control
1312 Function: INTERN_DVBT2_Serial_Control
1313 Parmeter: bEnable : TRUE For serial
1314 Return: MS_BOOL :
1315 Remark:
1316 *************************************************************************************************/
INTERN_DVBT2_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1317 MS_BOOL INTERN_DVBT2_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1318 {
1319 MS_U8 status = true;
1320 MS_U8 temp_val;
1321 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_ts... u8TSClk=%d\n",u8TSClk));
1322
1323 if (u8TSClk == 0xFF) u8TSClk=0x13;
1324 if (bEnable) //Serial mode for TS pad
1325 {
1326 // serial
1327 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1328 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1329
1330 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1331 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1332 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1333
1334 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1335 temp_val|=0x04;
1336 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1337 #else
1338 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1339 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1340 temp_val|=0x07;
1341 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1342 #endif
1343 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1344 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1345 }
1346 else
1347 {
1348 //parallel
1349 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1350 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1351
1352 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1353 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1354 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1355 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1356 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1357 temp_val|=0x05;
1358 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1359 #else
1360 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1361 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1362 temp_val|=0x07;
1363 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1364 #endif
1365
1366 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1367 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1368 }
1369
1370 //DBG_INTERN_DVBT2(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1371
1372 INTERN_DVBT2_Driving_Control(INTERN_DVBT2_DTV_DRIVING_LEVEL);
1373 return status;
1374 }
1375
1376 /************************************************************************************************
1377 Subject: TS1 output control
1378 Function: INTERN_DVBT2_PAD_TS1_Enable
1379 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1380 Return: void
1381 Remark:
1382 *************************************************************************************************/
INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)1383 void INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)
1384 {
1385 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_TS1_Enable... \n"));
1386
1387 if(flag) // PAD_TS1 Enable TS CLK PAD
1388 {
1389 //printf("=== TS1_Enable ===\n");
1390 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1391 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1392 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1393 }
1394 else // PAD_TS1 Disable TS CLK PAD
1395 {
1396 //printf("=== TS1_Disable ===\n");
1397 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1398 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1399 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1400 }
1401 }
1402
1403 /************************************************************************************************
1404 Subject: channel change config
1405 Function: INTERN_DVBT2_Config
1406 Parmeter: BW: bandwidth
1407 Return: MS_BOOL :
1408 Remark:
1409 *************************************************************************************************/
INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U8 u8PlpID)1410 MS_BOOL INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U8 u8PlpID)
1411 {
1412 MS_U8 bandwidth;
1413 MS_U8 status = true;
1414 //MS_U8 temp_val;
1415 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_config %d %d %d %ld %d\n", BW, bSerialTS, u8TSClk, u32IFFreq, u8PlpID));
1416 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Config, t = %ld\n",MsOS_GetSystemTime()));
1417
1418 if (u8TSClk == 0xFF) u8TSClk=0x13;
1419 switch(BW)
1420 {
1421 case E_DMD_T2_RF_BAND_5MHz:
1422 bandwidth = 1;
1423 break;
1424 case E_DMD_T2_RF_BAND_6MHz:
1425 bandwidth = 2;
1426 break;
1427 case E_DMD_T2_RF_BAND_7MHz:
1428 bandwidth = 3;
1429 break;
1430 case E_DMD_T2_RF_BAND_10MHz:
1431 bandwidth = 5;
1432 break;
1433 case E_DMD_T2_RF_BAND_1p7MHz:
1434 bandwidth = 0;
1435 break;
1436 case E_DMD_T2_RF_BAND_8MHz:
1437 default:
1438 bandwidth = 4;
1439 break;
1440 }
1441
1442 status &= INTERN_DVBT2_Reset();
1443
1444 // BW mode
1445 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_BW, BW);
1446 // TS mode
1447 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_T2_TS_SERIAL, bSerialTS? 0x01:0x00);
1448 // FC
1449 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_L, u32IFFreq&0xff);
1450 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_H, (u32IFFreq>>8)&0xff);
1451 // PLP_ID
1452 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
1453
1454 /*
1455 if(bSerialTS)
1456 {
1457 // serial
1458 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1459 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1460
1461 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1462 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1463 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1464 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1465 temp_val|=0x04;
1466 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1467 #else
1468 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1469 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1470 temp_val|=0x07;
1471 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1472 #endif
1473 }
1474 else
1475 {
1476 //parallel
1477 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1478 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1479
1480 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1481 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1482 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1483 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1484 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1485 temp_val|=0x05;
1486 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1487 #else
1488 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1489 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1490 temp_val|=0x07;
1491 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1492 #endif
1493 }
1494 */
1495 return status;
1496 }
1497 /************************************************************************************************
1498 Subject: enable hw to lock channel
1499 Function: INTERN_DVBT2_Active
1500 Parmeter: bEnable
1501 Return: MS_BOOL
1502 Remark:
1503 *************************************************************************************************/
INTERN_DVBT2_Active(MS_BOOL bEnable)1504 MS_BOOL INTERN_DVBT2_Active(MS_BOOL bEnable)
1505 {
1506 MS_U8 status = true;
1507
1508 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_active\n"));
1509
1510 //// INTERN_DVBT2 Finite State Machine on/off //////////
1511 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1512
1513 // INTERN_DVBT2_SignalQualityReset();
1514 return status;
1515 }
1516 /************************************************************************************************
1517 Subject: Return lock status
1518 Function: INTERN_DVBT2_Lock
1519 Parmeter: eStatus :
1520 Return: MS_BOOL
1521 Remark:
1522 *************************************************************************************************/
INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout,MS_U16 u16DMD_DVBT2_FEC_Timeout)1523 DMD_T2_LOCK_STATUS INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout, MS_U16 u16DMD_DVBT2_FEC_Timeout)
1524 {
1525 // float fBER=0.0f;
1526
1527 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK))
1528 {
1529 #if 0
1530 // copy from msb1240 >>>>>
1531 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1532 {
1533 if ((fBerFilteredDVBT2 <= 0.0) || ((fBerFilteredDVBT2/fBER) > 30.0 || (fBerFilteredDVBT2/fBER) < 0.03))
1534 fBerFilteredDVBT2 = fBER;
1535 else
1536 fBerFilteredDVBT2 = 0.9f*fBerFilteredDVBT2+0.1f*fBER;
1537 }
1538 // <<<<< copy from msb1240
1539 #endif
1540
1541 if (bFECLock == FALSE)
1542 {
1543 u32FecFirstLockTime = MsOS_GetSystemTime();
1544 DBG_INTERN_DVBT2(printf("++++++++[utopia]dvbt2 lock\n"));
1545 }
1546
1547 #if (AUTO_TS_DATA_RATE)
1548 INTERN_DVBT2_ConfigAdaptiveTsDivNum();
1549 #endif
1550
1551 #if 0
1552 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1553 {
1554 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1555 {
1556 if(fLDPCBerFiltered <= 0.0)
1557 fLDPCBerFiltered = fBER;
1558 else
1559 fLDPCBerFiltered = 0.9f*fLDPCBerFiltered+0.1f*fBER;
1560 }
1561 DBG_INTERN_DVBT2(printf("[dvbt2]f_ber=%8.3e, g_ldpc_ber=%8.3e\n",fBER,fLDPCBerFiltered));
1562 }
1563 #endif
1564 u32FecLastLockTime = MsOS_GetSystemTime();
1565 bFECLock = TRUE;
1566 return E_DMD_T2_LOCK;
1567 }
1568 else
1569 {
1570 #if 0
1571 INTERN_DVBT2_SignalQualityReset();
1572 #endif
1573 if (bFECLock == TRUE)
1574 {
1575 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1576 {
1577 return E_DMD_T2_LOCK;
1578 }
1579 }
1580 bFECLock = FALSE;
1581 }
1582 /*
1583 #ifdef CHIP_KRITI
1584 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_NO_CHANNEL))
1585 {
1586 // DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- E_DMD_DVBT2_NO_CHANNEL \n"););
1587 return E_DMD_T2_UNLOCK;
1588 }
1589 #endif
1590 */
1591 if(!bP1Lock)
1592 {
1593 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_EVER_LOCK))
1594 {
1595 DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- P1Lock \n"));
1596 bP1Lock = TRUE;
1597 }
1598 }
1599 if(bP1Lock)
1600 {
1601 DBG_INTERN_DVBT2(printf("P1Lock %ld\n",MsOS_GetSystemTime()));
1602 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_FEC_Timeout)
1603 {
1604 return E_DMD_T2_CHECKING;
1605 }
1606 }
1607 else
1608 {
1609 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_P1_Timeout)
1610 {
1611 return E_DMD_T2_CHECKING;
1612 }
1613 }
1614 return E_DMD_T2_UNLOCK;
1615
1616 }
1617
1618
INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)1619 MS_BOOL INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)
1620 {
1621 MS_U16 u16Address = 0;
1622 MS_U8 cData = 0;
1623 MS_U8 cBitMask = 0;
1624 MS_U8 use_dsp_reg = 0;
1625
1626 switch( eStatus )
1627 {
1628 case E_DMD_DVBT2_FEC_LOCK:
1629 use_dsp_reg = 1;
1630 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //FEC lock,
1631 cBitMask = BIT(7);
1632 break;
1633
1634 case E_DMD_DVBT2_P1_LOCK:
1635 u16Address = 0x3082; //P1 HW Lock,
1636 cBitMask = BIT(3);
1637 break;
1638
1639 case E_DMD_DVBT2_DCR_LOCK:
1640 use_dsp_reg = 1;
1641 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //DCR Lock,
1642 cBitMask = BIT(2);
1643 break;
1644
1645 case E_DMD_DVBT2_AGC_LOCK:
1646 use_dsp_reg = 1;
1647 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //AGC Lock,
1648 cBitMask = BIT(0);
1649 break;
1650
1651 case E_DMD_DVBT2_MODE_DET:
1652 u16Address = 0x3082; //Mode CP Detect,
1653 cBitMask = BIT(1);
1654 break;
1655
1656 case E_DMD_DVBT2_P1_EVER_LOCK:
1657 use_dsp_reg = 1;
1658 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //P1 Ever Lock,
1659 cBitMask = BIT(5);
1660 break;
1661
1662 case E_DMD_DVBT2_L1_CRC_LOCK:
1663 u16Address = 0x2B41; //P1 Ever Lock,
1664 cBitMask = BIT(5)|BIT(6)|BIT(7);
1665 break;
1666
1667 case E_DMD_DVBT2_NO_CHANNEL:
1668 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1669 cBitMask = BIT(7);
1670 break;
1671
1672
1673 default:
1674 return FALSE;
1675 }
1676
1677 if (use_dsp_reg == 1)
1678 {
1679 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16Address, &cData) == FALSE)
1680 {
1681 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
1682 return FALSE;
1683 }
1684 }
1685 else
1686 {
1687 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1688 {
1689 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadReg fail \n"));
1690 return FALSE;
1691 }
1692 }
1693
1694 #ifdef MS_DEBUG
1695 MS_U8 u8tmp;
1696 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20c4, &u8tmp);
1697 DBG_INTERN_DVBT2(printf(">>>>>>>>>> DVBT2 State=%d \n", u8tmp));
1698 #endif
1699
1700 if ((cData & cBitMask) == cBitMask)
1701 {
1702 #if (AUTO_TS_DATA_RATE)
1703 if(eStatus == E_DMD_DVBT2_FEC_LOCK)
1704 INTERN_DVBT2_ConfigAdaptiveTsDivNum();
1705 #endif
1706 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is lock \n", eStatus));
1707 return TRUE;
1708 }
1709 else
1710 {
1711 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is unlock \n", eStatus));
1712 return FALSE;
1713 }
1714
1715 }
1716
1717 /****************************************************************************
1718 Subject: To get the Post LDPC BER
1719 Function: INTERN_DVBT2_GetPostLdpcBer
1720 Parmeter: Quility
1721 Return: E_RESULT_SUCCESS
1722 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1723 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1724 We will not read the Period, and have the "/256/8"
1725 **************************************************************************/
INTERN_DVBT2_GetPostLdpcBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg,MS_U16 * FecType)1726 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType)
1727 {
1728 MS_BOOL status = true;
1729 MS_U8 reg=0;
1730 // MS_U16 BitErrPeriod;
1731 // MS_U32 BitErr;
1732 // MS_U16 FecType = 0;
1733
1734 /////////// Post-Viterbi BER /////////////
1735 /////////// Data BER /////////////
1736 // bank 0x33 0x02 [0] freeze
1737 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1738
1739 // bank 0x33 0x12 Data BER Window[15:0]
1740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1741 *BitErrPeriod_reg = reg;
1742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1743 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg;
1744
1745 // bank 0x33 0x34 Data BER count[15:0]
1746 // bank 0x33 0x35 Data BER count[31:16]
1747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1748 *BitErr_reg = reg;
1749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1750 *BitErr_reg = (*BitErr_reg << 8) | reg;
1751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1752 *BitErr_reg = (*BitErr_reg << 8) | reg;
1753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1754 *BitErr_reg = (*BitErr_reg << 8) | reg;
1755
1756 // bank 0x33 0x02 [0] freeze
1757 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1758
1759 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1760 *FecType = reg;
1761 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1762 *FecType = (*FecType << 8) | reg;
1763
1764 return status;
1765 }
1766
1767 #if 0
1768 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(float *ber)
1769 {
1770 MS_BOOL status = true;
1771 MS_U8 reg=0;
1772 MS_U16 BitErrPeriod;
1773 MS_U32 BitErr;
1774 MS_U16 FecType = 0;
1775
1776 /////////// Post-Viterbi BER /////////////
1777
1778 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1779 {
1780 *ber = (float)-1.0;
1781 return false;
1782 }
1783
1784 /////////// Data BER /////////////
1785 // bank 0x33 0x02 [0] freeze
1786 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1787
1788 // bank 0x33 0x12 Data BER Window[15:0]
1789 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1790 BitErrPeriod = reg;
1791 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1792 BitErrPeriod = (BitErrPeriod << 8) | reg;
1793
1794 // bank 0x33 0x34 Data BER count[15:0]
1795 // bank 0x33 0x35 Data BER count[31:16]
1796 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1797 BitErr = reg;
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1799 BitErr = (BitErr << 8) | reg;
1800 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1801 BitErr = (BitErr << 8) | reg;
1802 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1803 BitErr = (BitErr << 8) | reg;
1804
1805 // bank 0x33 0x02 [0] freeze
1806 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1807
1808 if (BitErrPeriod == 0)
1809 //protect 0
1810 BitErrPeriod = 1;
1811
1812 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1813 FecType = reg;
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1815 FecType = (FecType << 8) | reg;
1816
1817 if (FecType & 0x0180)
1818 {
1819 if (BitErr == 0)
1820 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1821 else
1822 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1823 }
1824 else
1825 {
1826 if (BitErr == 0)
1827 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1828 else
1829 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1830 }
1831
1832 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PostLDPCBER = %8.3e \n ", *ber));
1833
1834 if (status == FALSE)
1835 {
1836 printf("INTERN_DVBT2_GetPostLdpcBer Fail!\n");
1837 return FALSE;
1838 }
1839
1840 return status;
1841 }
1842 #endif
1843
1844 /****************************************************************************
1845 Subject: To get the Pre LDPC BER
1846 Function: INTERN_DVBT2_GetPreLdpcBer
1847 Parmeter: ber
1848 Return: E_RESULT_SUCCESS
1849 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1850 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1851 We will not read the Period, and have the "/256/8"
1852 *****************************************************************************/
INTERN_DVBT2_GetPreLdpcBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg,MS_U16 * FecType)1853 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType)
1854 {
1855 MS_U8 status = true;
1856 MS_U8 reg=0;
1857 // MS_U16 BitErrPeriod;
1858 // MS_U32 BitErr;
1859 // MS_U16 FecType = 0;
1860
1861 /////////// Data BER /////////////
1862 // bank 0x33 0x02 [0] freeze
1863 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1864
1865 // bank 0x33 0x12 Data BER Window[15:0]
1866 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1867 *BitErrPeriod_reg = reg;
1868 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1869 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg;
1870
1871 // bank 0x33 0x34 Data BER count[15:0]
1872 // bank 0x33 0x35 Data BER count[31:16]
1873 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1874 *BitErr_reg = reg;
1875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1876 *BitErr_reg = (*BitErr_reg << 8) | reg;
1877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1878 *BitErr_reg = (*BitErr_reg << 8) | reg;
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1880 *BitErr_reg = (*BitErr_reg << 8) | reg;
1881
1882 // bank 0x33 0x02 [0] freeze
1883 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1884
1885 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1886 *FecType = reg;
1887 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1888 *FecType = (*FecType << 8) | reg;
1889
1890 return status;
1891 }
1892
1893 #if 0
1894 /****************************************************************************
1895 Subject: To get the Pre LDPC BER
1896 Function: INTERN_DVBT2_GetPreLdpcBer
1897 Parmeter: ber
1898 Return: E_RESULT_SUCCESS
1899 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1900 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1901 We will not read the Period, and have the "/256/8"
1902 *****************************************************************************/
1903 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(float *ber)
1904 {
1905 MS_U8 status = true;
1906 MS_U8 reg=0;
1907 MS_U16 BitErrPeriod;
1908 MS_U32 BitErr;
1909 MS_U16 FecType = 0;
1910
1911 /////////// Data BER /////////////
1912 // bank 0x33 0x02 [0] freeze
1913 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1914
1915 // bank 0x33 0x12 Data BER Window[15:0]
1916 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1917 BitErrPeriod = reg;
1918 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1919 BitErrPeriod = (BitErrPeriod << 8) | reg;
1920
1921 // bank 0x33 0x34 Data BER count[15:0]
1922 // bank 0x33 0x35 Data BER count[31:16]
1923 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1924 BitErr = reg;
1925 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1926 BitErr = (BitErr << 8) | reg;
1927 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1928 BitErr = (BitErr << 8) | reg;
1929 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1930 BitErr = (BitErr << 8) | reg;
1931
1932 // bank 0x33 0x02 [0] freeze
1933 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1934
1935 if (BitErrPeriod == 0)
1936 //protect 0
1937 BitErrPeriod = 1;
1938
1939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1940 FecType = reg;
1941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1942 FecType = (FecType << 8) | reg;
1943
1944 if (FecType & 0x0180)
1945 {
1946 if (BitErr == 0)
1947 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1948 else
1949 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1950 }
1951 else
1952 {
1953 if (BitErr == 0)
1954 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1955 else
1956 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1957 }
1958
1959 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PreLDPCBER = %8.3e \n ", *ber));
1960
1961 if (status == FALSE)
1962 {
1963 printf("INTERN_DVBT2_GetPreLdpcBer Fail!\n");
1964 return FALSE;
1965 }
1966
1967 return status;
1968 }
1969 #endif
1970
1971 /****************************************************************************
1972 Subject: To get the Packet error
1973 Function: INTERN_DVBT2_GetPacketErr
1974 Parmeter: pktErr
1975 Return: E_RESULT_SUCCESS
1976 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1977 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1978 We will not read the Period, and have the "/256/8"
1979 *****************************************************************************/
INTERN_DVBT2_GetPacketErr(MS_U16 * u16PktErr)1980 MS_BOOL INTERN_DVBT2_GetPacketErr(MS_U16 *u16PktErr)
1981 {
1982 MS_BOOL status = true;
1983 MS_U8 reg = 0;
1984 MS_U16 PktErr;
1985
1986 //freeze
1987 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01);
1988 //read packet error
1989 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5B, ®);
1990 PktErr = reg;
1991 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5A, ®);
1992 PktErr = (PktErr << 8) | reg;
1993
1994 *u16PktErr = PktErr;
1995 //release
1996 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00);
1997
1998 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PktErr = %d \n ", (int)PktErr));
1999
2000 *u16PktErr = PktErr;
2001
2002 return status;
2003 }
2004
2005 /****************************************************************************
2006 Subject: To get the DVBT2 parameter
2007 Function: INTERN_DVBT2_Get_L1_Info
2008 Parmeter: point to return parameter
2009 Return: TRUE
2010 FALSE
2011 Remark: The TPS parameters will be available after TPS lock
2012 *****************************************************************************/
INTERN_DVBT2_Get_L1_Parameter(MS_U16 * pu16L1_parameter,DMD_DVBT2_SIGNAL_INFO eSignalType)2013 MS_BOOL INTERN_DVBT2_Get_L1_Parameter( MS_U16 * pu16L1_parameter, DMD_DVBT2_SIGNAL_INFO eSignalType)
2014 {
2015 MS_U8 u8Data = 0;
2016 MS_U16 FecType = 0;
2017 MS_U16 u16Data = 0;
2018 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
2019 {
2020 if (eSignalType == T2_MODUL_MODE)
2021 {
2022 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
2023 return FALSE;
2024
2025 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(5) | BIT(4) | BIT(3))) >> 3;
2026 }
2027 else if (eSignalType == T2_FFT_VALUE)
2028 {
2029 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
2030 {
2031 return FALSE;
2032 }
2033 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
2034 }
2035 else if (eSignalType == T2_GUARD_INTERVAL)
2036 {
2037 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
2038 {
2039 return FALSE;
2040 }
2041 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(6) | BIT(5) | BIT(4))) >> 4;
2042 }
2043 else if (eSignalType == T2_CODE_RATE)
2044 {
2045 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
2046 {
2047 return FALSE;
2048 }
2049 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
2050 }
2051 else if (eSignalType == T2_PREAMBLE)
2052 {
2053 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
2054 {
2055 return FALSE;
2056 }
2057 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(4))) >> 4;
2058 }
2059 else if (eSignalType == T2_S1_SIGNALLING)
2060 {
2061 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
2062 {
2063 return FALSE;
2064 }
2065 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(3) | BIT(2) | BIT(1))) >> 1;
2066 }
2067 else if (eSignalType == T2_PILOT_PATTERN)
2068 {
2069 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE)
2070 {
2071 return FALSE;
2072 }
2073 *pu16L1_parameter = (((MS_U16) u8Data) & 0x0F);
2074 }
2075 else if (eSignalType == T2_BW_EXT)
2076 {
2077 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
2078 {
2079 return FALSE;
2080 }
2081 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(0)));
2082 }
2083 else if (eSignalType == T2_PAPR_REDUCTION)
2084 {
2085 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2), &u8Data) == FALSE)
2086 {
2087 return FALSE;
2088 }
2089 *pu16L1_parameter = (((MS_U16) u8Data) & 0xF0) >> 4;
2090 }
2091 else if (eSignalType == T2_OFDM_SYMBOLS_PER_FRAME)
2092 {
2093 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2), &u8Data) == FALSE)
2094 {
2095 return FALSE;
2096 }
2097 *pu16L1_parameter = (MS_U16) u8Data;
2098 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2) + 1, &u8Data) == FALSE)
2099 {
2100 return FALSE;
2101 }
2102 *pu16L1_parameter |= (((MS_U16) u8Data) & 0x0F) << 8;
2103 }
2104 else if (eSignalType == T2_PLP_ROTATION)
2105 {
2106 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
2107 {
2108 return FALSE;
2109 }
2110 *pu16L1_parameter = (((MS_U16) u8Data) & BIT(6)) >> 6;
2111 }
2112 else if (eSignalType == T2_PLP_FEC_TYPE)
2113 {
2114 //FEC Type[8:7]
2115 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8f, &u8Data) == FALSE) return FALSE;
2116 FecType = u8Data;
2117 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8e, &u8Data) == FALSE) return FALSE;
2118 FecType = (FecType << 8) | u8Data;
2119
2120 *pu16L1_parameter = (FecType & 0x0180) >> 7;
2121 }
2122 else if (eSignalType == T2_NUM_PLP)
2123 {
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x42 * 2), &u8Data) == FALSE)
2125 {
2126 return FALSE;
2127 }
2128 *pu16L1_parameter = (MS_U16)u8Data;
2129 }
2130 else if (eSignalType == T2_PLP_TYPE)
2131 {
2132 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x45 * 2) + 1, &u8Data) == FALSE)
2133 {
2134 return FALSE;
2135 }
2136 *pu16L1_parameter = ((MS_U16) u8Data) & 0x07;
2137 }
2138 else if (eSignalType == T2_PLP_TIME_IL_TYPE)
2139 {
2140 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x48 * 2) + 1, &u8Data) == FALSE)
2141 {
2142 return FALSE;
2143 }
2144 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2145 }
2146 else if (eSignalType == T2_PLP_TIME_IL_LENGTH)
2147 {
2148 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x49 * 2) + 1, &u8Data) == FALSE)
2149 {
2150 return FALSE;
2151 }
2152 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2153 }
2154 else if (eSignalType == T2_DAT_ISSY)
2155 {
2156 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2157 {
2158 return FALSE;
2159 }
2160 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2161 }
2162 else if (eSignalType == T2_PLP_MODE)
2163 {
2164 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE)
2165 {
2166 return FALSE;
2167 }
2168 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE)
2169 {
2170 return FALSE;
2171 }
2172 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2173 {
2174 return FALSE;
2175 }
2176 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE)
2177 {
2178 return FALSE;
2179 }
2180 *pu16L1_parameter = ((MS_U16) u8Data) & 0x03;
2181 }
2182 else if (eSignalType == T2_L1_MODULATION)
2183 {
2184 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2) + 1, &u8Data) == FALSE)
2185 {
2186 return FALSE;
2187 }
2188 *pu16L1_parameter = ((MS_U16) u8Data) & 0x0F;
2189 }
2190 else if (eSignalType == T2_NUM_T2_FRAMES)
2191 {
2192 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3b * 2), &u8Data) == FALSE)
2193 {
2194 return FALSE;
2195 }
2196 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2197 }
2198 else if (eSignalType == T2_PLP_NUM_BLOCKS_MAX)
2199 {
2200 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2) + 1, &u8Data) == FALSE) return FALSE;
2201 u16Data = u8Data & 0x03;
2202 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2), &u8Data) == FALSE) return FALSE;
2203 u16Data = (u16Data << 8) | u8Data;
2204
2205 *pu16L1_parameter = u16Data;
2206 }
2207 else if (eSignalType == T2_FEF_ENABLE)
2208 {
2209
2210 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(0x00F1, &u8Data) == FALSE)
2211 {
2212 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2213 return FALSE;
2214 }
2215 *pu16L1_parameter = ((MS_U16) u8Data) & 0x01;
2216 }
2217 else
2218 {
2219 return FALSE;
2220 }
2221
2222 return TRUE;
2223
2224 }
2225
2226 return FALSE;
2227 }
2228
2229
2230 /****************************************************************************
2231 Subject: Read the signal to noise ratio (SNR)
2232 Function: INTERN_DVBT2_GetSNR
2233 Parmeter: None
2234 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2235 Remark:
2236 *****************************************************************************/
INTERN_DVBT2_GetSNR(MS_U16 * u16_snr100,MS_U8 * snr_cali,MS_U8 * u8_gi)2237 MS_BOOL INTERN_DVBT2_GetSNR (MS_U16 *u16_snr100, MS_U8 *snr_cali, MS_U8 *u8_gi)
2238 {
2239 MS_U8 status = true;
2240 MS_U8 reg=0, reg_frz=0;
2241 // MS_U16 u16_snr100 = 0;
2242 // float f_snr;
2243 // MS_U8 u8_win = 0;
2244 // MS_U8 u8_gi = 0;
2245
2246 // freeze
2247 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
2248 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
2249
2250 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
2251 *u16_snr100 = reg;
2252 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
2253 *u16_snr100 = (*u16_snr100<<8)|reg;
2254
2255 // unfreeze
2256 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
2257
2258 // f_snr = (float)u16_snr100/100.0;
2259
2260 // snr cali
2261 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
2262 *snr_cali = (reg>>2)&0x01;
2263
2264 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
2265 *u8_gi = (reg>>1)&0x07;
2266
2267 return status;
2268 #if 0
2269 if (u8_win == 1)
2270 {
2271 float snr_offset = 0.0;
2272 float snr_cali = 0.0;
2273
2274 if (u8_gi == 0) snr_offset = 0.157;
2275 else if(u8_gi == 1) snr_offset = 0.317;
2276 else if(u8_gi == 2) snr_offset = 0.645;
2277 else if(u8_gi == 3) snr_offset = 1.335;
2278 else if(u8_gi == 4) snr_offset = 0.039;
2279 else if(u8_gi == 5) snr_offset = 0.771;
2280 else if(u8_gi == 6) snr_offset = 0.378;
2281
2282 snr_cali = f_snr - snr_offset;
2283 if (snr_cali > 0.0) f_snr = snr_cali;
2284 }
2285 //use Polynomial curve fitting to fix snr
2286 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
2287 //f_snr = f_snr + snr_poly;
2288
2289 if (status == true)
2290 return f_snr;
2291 else
2292 return -1;
2293 #endif
2294
2295 }
2296
2297 #if 0
2298 float INTERN_DVBT2_GetSNR (void)
2299 {
2300 MS_U8 status = true;
2301 MS_U8 reg=0, reg_frz=0;
2302 MS_U16 u16_snr100 = 0;
2303 float f_snr;
2304 MS_U8 u8_win = 0;
2305 MS_U8 u8_gi = 0;
2306
2307 // freeze
2308 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
2309 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
2310
2311 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
2312 u16_snr100 = reg;
2313 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
2314 u16_snr100 = (u16_snr100<<8)|reg;
2315
2316 // unfreeze
2317 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
2318
2319 f_snr = (float)u16_snr100/100.0;
2320
2321 // snr cali
2322 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
2323 u8_win = (reg>>2)&0x01;
2324
2325 if (u8_win == 1)
2326 {
2327 float snr_offset = 0.0;
2328 float snr_cali = 0.0;
2329
2330 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
2331 u8_gi = (reg>>1)&0x07;
2332
2333 if (u8_gi == 0) snr_offset = 0.157;
2334 else if(u8_gi == 1) snr_offset = 0.317;
2335 else if(u8_gi == 2) snr_offset = 0.645;
2336 else if(u8_gi == 3) snr_offset = 1.335;
2337 else if(u8_gi == 4) snr_offset = 0.039;
2338 else if(u8_gi == 5) snr_offset = 0.771;
2339 else if(u8_gi == 6) snr_offset = 0.378;
2340
2341 snr_cali = f_snr - snr_offset;
2342 if (snr_cali > 0.0) f_snr = snr_cali;
2343 }
2344 //use Polynomial curve fitting to fix snr
2345 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
2346 //f_snr = f_snr + snr_poly;
2347
2348 if (status == true)
2349 return f_snr;
2350 else
2351 return -1;
2352
2353 }
2354 #endif
2355
2356 #if 0
2357 MS_BOOL INTERN_DVBT2_GetSignalStrength(MS_U16 *strength,const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2358 {
2359 MS_U8 status = true;
2360 float ch_power_db = 0.0f;
2361 float ch_power_ref = 11.0f;
2362 float ch_power_rel = 0.0f;
2363 //MS_U8 u8_index = 0;
2364 MS_U16 L1_info_qam, L1_info_cr;
2365 // MS_U8 demodState = 0;
2366
2367 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2368 {
2369 *strength = 0;
2370 return TRUE;
2371 }
2372 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2373
2374 // if (INTERN_DVBT2_Lock(COFDM_TPS_LOCK))
2375 //if (INTERN_DVBT2_Lock(COFDM_AGC_LOCK))
2376 /* Actually, it's more reasonable, that signal level depended on cable input power level
2377 * thougth the signal isn't dvb-t signal.
2378 */
2379
2380 #if 0
2381 // use pointer of IFAGC table to identify
2382 // case 1: RFAGC from SAR, IFAGC controlled by demod
2383 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2384 status &= HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2385 sDMD_DVBT2_InitData->pTuner_RfagcSsi, sDMD_DVBT2_InitData->u16Tuner_RfagcSsi_Size,
2386 sDMD_DVBT2_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2387 sDMD_DVBT2_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2388 sDMD_DVBT2_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_HiRef_Size,
2389 sDMD_DVBT2_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_LoRef_Size);
2390 #endif
2391
2392 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2393 printf("[dvbt2] QAM parameter retrieve failure\n");
2394
2395 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2396 printf("[dvbt2]code rate parameter retrieve failure\n");
2397
2398 /*
2399 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2400 {
2401 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)L1_info_qam)
2402 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)L1_info_cr))
2403 {
2404 ch_power_ref = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2405 break;
2406 }
2407 else
2408 {
2409 u8_index++;
2410 }
2411 }
2412 */
2413 ch_power_ref = dvbt2_ssi_dbm_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
2414
2415 // status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + (0x62*2), &demodState);
2416
2417 if (ch_power_ref > 10.0f)
2418 *strength = 0;
2419 else
2420 {
2421 // For Nordig's SSI test items
2422 if ( (L1_info_qam == 3) //256qam
2423 && (L1_info_cr > 0 && L1_info_cr < 4) // CR 3/5,2/3,3/4
2424 )
2425 {
2426 MS_U8 u8_x = L1_info_cr - 1;
2427 float f_ssi = 0.0;
2428
2429 if(ch_power_db >= -45)f_ssi = 100;
2430 else if (ch_power_db >= -50) f_ssi = fT2_SSI_formula[u8_x][0]*(ch_power_db + 50) + fT2_SSI_formula[u8_x][1];
2431 else if (ch_power_db >= -60) f_ssi = fT2_SSI_formula[u8_x][2]*(ch_power_db + 60) + fT2_SSI_formula[u8_x][3];
2432 else if (ch_power_db >= -70) f_ssi = fT2_SSI_formula[u8_x][4]*(ch_power_db + 70) + fT2_SSI_formula[u8_x][5];
2433 else if (ch_power_db >= -80) f_ssi = fT2_SSI_formula[u8_x][6]*(ch_power_db + 80) + fT2_SSI_formula[u8_x][7];
2434 else if (ch_power_db >= -95) f_ssi = fT2_SSI_formula[u8_x][8]*(ch_power_db + 95) + fT2_SSI_formula[u8_x][9];
2435 else if (ch_power_db >= -100) f_ssi = fT2_SSI_formula[u8_x][10]*(ch_power_db + 100) + fT2_SSI_formula[u8_x][11];
2436
2437 if (f_ssi > 100) *strength = 100;
2438 else if (f_ssi < 0) *strength = 0;
2439 else *strength = (MS_U16)(f_ssi+0.5);
2440
2441 DBG_GET_SIGNAL(printf(">>> SSI... RF_level=%d, f_ssi=%d, ssi=%d, cr=%d, mod=%d\n", (MS_S16)ch_power_db, (MS_S16)f_ssi, (MS_S16)(*strength), L1_info_cr, L1_info_qam));
2442 }
2443 else
2444 {
2445 ch_power_rel = ch_power_db - ch_power_ref;
2446 /*
2447 if (demodState != 0x09)
2448 {
2449 ch_power_rel = ch_power_db - (-50.0f);
2450 }
2451 else
2452 {
2453 ch_power_rel = ch_power_db - ch_power_ref;
2454 }
2455 */
2456 if ( ch_power_rel < -15.0f )
2457 {
2458 *strength = 0;
2459 }
2460 else if ( ch_power_rel < 0.0f )
2461 {
2462 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2463 }
2464 else if ( ch_power_rel < 20 )
2465 {
2466 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2467 }
2468 else if ( ch_power_rel < 35.0f )
2469 {
2470 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2471 }
2472 else
2473 {
2474 *strength = 100;
2475 }
2476 }
2477 }
2478
2479 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2480 {
2481 *strength = 0;
2482 return TRUE;
2483 }
2484
2485 DBG_GET_SIGNAL(printf(">>> ch_power_ref(dB) = %d , ch_power_db(dB) = %d, ch_power_rel(dB) = %d<<<\n", (MS_S16)ch_power_ref, (MS_S16)ch_power_db, (MS_S16)ch_power_rel));
2486 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %d , Score = %d<<<\n", (MS_S16)ch_power_db, *strength));
2487 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2488
2489 return status;
2490 }
2491 #endif
2492
2493 #if 0
2494 /****************************************************************************
2495 Subject: To get the DVT Signal quility
2496 Function: INTERN_DVBT2_GetSignalQuality
2497 Parmeter: Quility
2498 Return: E_RESULT_SUCCESS
2499 E_RESULT_FAILURE
2500 Remark: Here we have 4 level range
2501 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_100)
2502 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_60)
2503 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT2_SIGNAL_BASE_10)
2504 <4>.4th Range => Quality <10
2505 *****************************************************************************/
2506 MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2507 {
2508 // float ber_sqi, SQI;
2509 float fber;
2510 float cn_rec = 0;
2511 float cn_ref = 0;
2512 float cn_rel = 0;
2513
2514 #if 0
2515 float fBerTH1[] = {1E-4, 1E-4*(1.0-DVBT2_BER_TH_HY), 1E-4*(1.0+DVBT2_BER_TH_HY), 1E-4};
2516 float fBerTH2[] = {3E-7, 3E-7, 3E-7*(1.0-DVBT2_BER_TH_HY), 3E-7*(1.0+DVBT2_BER_TH_HY)};
2517 float BER_SQI = (float)0.0;
2518 float SQI = (float)0.0;
2519 static MS_U8 u8SQIState = 0;
2520 #endif
2521
2522 MS_U8 status = true;
2523 MS_U16 L1_info_qam = 0, L1_info_cr = 0, i = 0;
2524
2525 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2526
2527 if (TRUE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_LOCK) )
2528 {
2529 #if 1 // copy from msb1240
2530 if (fBerFilteredDVBT2 < 0.0)
2531 {
2532 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2533 {
2534 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2535 return FALSE;
2536 }
2537 fBerFilteredDVBT2 = fber;
2538 }
2539 else
2540 {
2541 fber = fBerFilteredDVBT2;
2542 }
2543
2544 if (fber > fBerTH1[u8SQIState])
2545 {
2546 BER_SQI = 0.0;
2547 u8SQIState = 1;
2548 }
2549 else if (fber >=fBerTH2[u8SQIState])
2550 {
2551 BER_SQI = 100.0/15;
2552 u8SQIState = 2;
2553 }
2554 else
2555 {
2556 BER_SQI = 100.0/6;
2557 u8SQIState = 3;
2558 }
2559
2560 cn_rec = INTERN_DVBT2_GetSNR();
2561 if (cn_rec < 0.0)
2562 return FALSE;
2563
2564 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2565 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2566 L1_info_qam = 0xff;
2567 L1_info_cr = 0xff;
2568
2569 cn_ref = (float)-1.0;
2570 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2571 printf("[dvbt2] QAM parameter retrieve failure\n");
2572
2573 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2574 printf("[dvbt2]code rate parameter retrieve failure\n");
2575
2576 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2577 {
2578 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2579 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2580 {
2581 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2582 break;
2583 }
2584 }
2585
2586 if (cn_ref < 0.0)
2587 {
2588 SQI = (float)0.0;
2589 printf("SQI is zero, 1\n");
2590 }
2591 else
2592 {
2593 // 0.7, snr offset
2594 cn_rel = cn_rec - cn_ref + 0.7f;
2595 if (cn_rel > 3.0)
2596 SQI = 100;
2597 else if (cn_rel >= -3)
2598 {
2599 SQI = (cn_rel+3)*BER_SQI;
2600 if (SQI > 100.0) SQI = 100.0;
2601 else if (SQI < 0.0) SQI = 0.0;
2602 }
2603 else
2604 {
2605 SQI = (float)0.0;
2606 printf("SQI is zero, 2\n");
2607 }
2608 }
2609
2610 *quality = (MS_U16)SQI;
2611 #else
2612 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2613 {
2614 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2615 }
2616 ///////// Get Pre-BCH (Post-LDPC) BER to determine BER_SQI //////////
2617 if(fLDPCBerFiltered<= 0.0)
2618 {
2619 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2620 {
2621 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2622 return FALSE;
2623 }
2624 fLDPCBerFiltered = fber;
2625 }
2626 else
2627 {
2628 fber = fLDPCBerFiltered;
2629 }
2630 /*
2631 if (fber > 1.0E-3)
2632 ber_sqi = 0.0;
2633 else if (fber > 8.5E-7)
2634 #ifdef MSOS_TYPE_LINUX
2635 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2636 #else
2637 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2638 #endif
2639 else
2640 ber_sqi = 100.0;
2641 */
2642 if (fber > 1E-4)
2643 ber_sqi = 0.0;
2644 else if (fber >= 1E-7)
2645 ber_sqi = 100.0 / 15;
2646 else
2647 ber_sqi = 100.0 / 6;
2648
2649 cn_rec = INTERN_DVBT2_GetSNR();
2650
2651 if (cn_rec == -1) //get SNR return fail
2652 status = false;
2653
2654 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2655 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2656 L1_info_qam = 0xff;
2657 L1_info_cr = 0xff;
2658
2659 cn_ref = (float)-1.0;
2660 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2661 printf("[dvbt2] QAM parameter retrieve failure\n");
2662
2663 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2664 printf("[dvbt2]code rate parameter retrieve failure\n");
2665
2666 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2667 {
2668 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2669 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2670 {
2671 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2672 break;
2673 }
2674 }
2675
2676 if (cn_ref == -1.0)
2677 SQI = (float)0.0;
2678 else
2679 {
2680 cn_rel = cn_rec - cn_ref;
2681 if (cn_rel > 3.0)
2682 SQI = 100;
2683 else if (cn_rel >= -3)
2684 {
2685 SQI = (cn_rel+3)*ber_sqi;
2686 if (SQI > 100.0) SQI = 100.0;
2687 else if (SQI < 0.0) SQI = 0.0;
2688 }
2689 else
2690 SQI = (float)0.0;
2691 }
2692
2693 // SQI patch, 256qam, R3/4 CN=20.8, SQI=0~13
2694 if ((L1_info_qam==_T2_256QAM) && (L1_info_cr==_T2_CR3Y4))
2695 {
2696 if ( (cn_rec > 20.6) && (cn_rec < 20.9))
2697 {
2698 if (SQI > 3) SQI -= 3;
2699 }
2700 else if ( (cn_rec >= 20.9) && (cn_rec < 21.2))
2701 {
2702 if (SQI > 9) SQI -= 9;
2703 }
2704 }
2705
2706 *quality = (MS_U16)SQI;
2707 #endif
2708 }
2709 else
2710 {
2711 *quality = 0;
2712 }
2713
2714 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, L1_info_qam, L1_info_cr));
2715 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2716 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2717 return status;
2718 }
2719 #endif
2720
2721 /****************************************************************************
2722 Subject: To get the DVBT Carrier Freq Offset
2723 Function: INTERN_DVBT2_Get_FreqOffset
2724 Parmeter: Frequency offset (in KHz), bandwidth
2725 Return: E_RESULT_SUCCESS
2726 E_RESULT_FAILURE
2727 Remark:
2728 *****************************************************************************/
INTERN_DVBT2_Get_FreqOffset(MS_U32 * CfoTd_reg,MS_U32 * CfoFd_reg,MS_U32 * Icfo_reg,MS_U8 * fft_reg)2729 MS_BOOL INTERN_DVBT2_Get_FreqOffset(MS_U32 *CfoTd_reg, MS_U32 *CfoFd_reg, MS_U32 *Icfo_reg, MS_U8 *fft_reg)
2730 {
2731 // float N, FreqB;
2732 // float FreqCfoTd, FreqCfoFd, FreqIcfo;
2733 // MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2734 MS_U8 reg_frz=0, reg=0;
2735 MS_U8 status;
2736
2737 #if 0
2738 FreqB = (float)u8BW * 8 / 7;
2739 #endif
2740
2741 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2742
2743 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2744
2745 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2746 *CfoTd_reg = reg;
2747
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2749 *CfoTd_reg = (*CfoTd_reg << 8)|reg;
2750
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2752 *CfoTd_reg = (*CfoTd_reg << 8)|reg;
2753 #if 0
2754 FreqCfoTd = (float)RegCfoTd;
2755
2756 if (RegCfoTd & 0x800000)
2757 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2758
2759 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2760 #endif
2761
2762 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2763
2764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2765 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2766
2767 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2768
2769 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2770 *CfoFd_reg = reg;
2771
2772 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2773 *CfoFd_reg = (*CfoFd_reg << 8)|reg;
2774
2775 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2776 *CfoFd_reg = (*CfoFd_reg << 8)|reg;
2777
2778 #if 0
2779 FreqCfoFd = (float)RegCfoFd;
2780
2781 if (RegCfoFd & 0x800000)
2782 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2783
2784 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2785 #endif
2786
2787 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2788 *Icfo_reg = reg & 0x07;
2789
2790 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2791 *Icfo_reg = (*Icfo_reg << 8)|reg;
2792
2793 #if 0
2794 FreqIcfo = (float)RegIcfo;
2795
2796 if (RegIcfo & 0x400)
2797 FreqIcfo = FreqIcfo - (float)0x800;
2798 #endif
2799
2800 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2801 *fft_reg = reg & 0x30;
2802
2803 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2804 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2805 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2806
2807 #if 0
2808 switch (*fft_reg)
2809 {
2810 case 0x00: N = 2048; break;
2811 case 0x20: N = 4096; break;
2812 case 0x10:
2813 default: N = 8192; break;
2814 }
2815
2816 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2817
2818
2819 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2820 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2821 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2822 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2823 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2824 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2825 #endif
2826
2827 if (status == TRUE)
2828 return TRUE;
2829 else
2830 return FALSE;
2831 }
2832
2833 #if 0
2834 /****************************************************************************
2835 Subject: To get the DVBT Carrier Freq Offset
2836 Function: INTERN_DVBT2_Get_FreqOffset
2837 Parmeter: Frequency offset (in KHz), bandwidth
2838 Return: E_RESULT_SUCCESS
2839 E_RESULT_FAILURE
2840 Remark:
2841 *****************************************************************************/
2842 MS_BOOL INTERN_DVBT2_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2843 {
2844 float N, FreqB;
2845 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2846 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2847 MS_U8 reg_frz=0, reg=0;
2848 MS_U8 status;
2849
2850 FreqB = (float)u8BW * 8 / 7;
2851
2852 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2853
2854 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2855
2856 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2857 RegCfoTd = reg;
2858
2859 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2860 RegCfoTd = (RegCfoTd << 8)|reg;
2861
2862 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2863 RegCfoTd = (RegCfoTd << 8)|reg;
2864
2865 FreqCfoTd = (float)RegCfoTd;
2866
2867 if (RegCfoTd & 0x800000)
2868 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2869
2870 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2871
2872 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2873
2874 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2875 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2876
2877 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2878
2879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2880 RegCfoFd = reg;
2881
2882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2883 RegCfoFd = (RegCfoFd << 8)|reg;
2884
2885 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2886 RegCfoFd = (RegCfoFd << 8)|reg;
2887
2888 FreqCfoFd = (float)RegCfoFd;
2889
2890 if (RegCfoFd & 0x800000)
2891 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2892
2893 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2894
2895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2896 RegIcfo = reg & 0x07;
2897
2898 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2899 RegIcfo = (RegIcfo << 8)|reg;
2900
2901 FreqIcfo = (float)RegIcfo;
2902
2903 if (RegIcfo & 0x400)
2904 FreqIcfo = FreqIcfo - (float)0x800;
2905
2906 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2907 reg = reg & 0x30;
2908
2909 switch (reg)
2910 {
2911 case 0x00: N = 2048; break;
2912 case 0x20: N = 4096; break;
2913 case 0x10:
2914 default: N = 8192; break;
2915 }
2916
2917 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2918 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2919 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2920 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2921 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2922 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2923 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2924 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2925 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2926 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2927
2928 if (status == TRUE)
2929 return TRUE;
2930 else
2931 return FALSE;
2932 }
2933 #endif
2934
INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)2935 void INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)
2936 {
2937
2938 bPowerOn = bPowerOn;
2939 }
2940
INTERN_DVBT2_Power_Save(void)2941 MS_BOOL INTERN_DVBT2_Power_Save(void)
2942 {
2943
2944 return TRUE;
2945 }
2946
INTERN_DVBT2_Version(MS_U16 * ver)2947 MS_BOOL INTERN_DVBT2_Version(MS_U16 *ver)
2948 {
2949
2950 MS_U8 status = true;
2951 MS_U8 tmp = 0;
2952 MS_U16 u16_INTERN_DVBT2_Version;
2953
2954 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2955 u16_INTERN_DVBT2_Version = tmp;
2956 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2957 u16_INTERN_DVBT2_Version = u16_INTERN_DVBT2_Version<<8|tmp;
2958 *ver = u16_INTERN_DVBT2_Version;
2959
2960 return status;
2961 }
2962
INTERN_DVBT2_Version_minor(MS_U8 * ver2)2963 MS_BOOL INTERN_DVBT2_Version_minor(MS_U8 *ver2)
2964 {
2965
2966 MS_U8 status = true;
2967
2968 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2969
2970 return status;
2971 }
2972
2973
INTERN_DVBT2_Show_Demod_Version(void)2974 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void)
2975 {
2976
2977 MS_BOOL status = true;
2978 MS_U16 u16_INTERN_DVBT2_Version = 0;
2979 MS_U8 u8_minor_ver = 0;
2980
2981 status &= INTERN_DVBT2_Version(&u16_INTERN_DVBT2_Version);
2982 status &= INTERN_DVBT2_Version_minor(&u8_minor_ver);
2983 printf("[DVBT2]Version = 0x%x,0x%x\n",u16_INTERN_DVBT2_Version,u8_minor_ver);
2984
2985 return status;
2986 }
2987
2988 #if 0
2989 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
2990 {
2991 dvbt2_ssi_dbm_nordigp1[constel][code_rate] = write_value;
2992 return TRUE;
2993 /*
2994 MS_U8 u8_index = 0;
2995 MS_BOOL bRet = false;
2996
2997 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2998 {
2999 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
3000 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
3001 {
3002 dvbt2_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
3003 bRet = true;
3004 break;
3005 }
3006 else
3007 {
3008 u8_index++;
3009 }
3010 }
3011 return bRet;
3012 */
3013 }
3014
3015 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
3016 {
3017 *read_value = dvbt2_ssi_dbm_nordigp1[constel][code_rate];
3018 return TRUE;
3019 /*
3020 MS_U8 u8_index = 0;
3021 MS_BOOL bRet = false;
3022
3023 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
3024 {
3025 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
3026 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
3027 {
3028 *read_value = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
3029 bRet = true;
3030 break;
3031 }
3032 else
3033 {
3034 u8_index++;
3035 }
3036 }
3037 return bRet;
3038 */
3039 }
3040 #endif
3041
INTERN_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)3042 MS_BOOL INTERN_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
3043 {
3044 MS_BOOL status = TRUE;
3045 MS_U8 u8Data = 0;
3046 MS_U8 indx = 0;
3047
3048 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_GetPlpBitMap\n"));
3049
3050 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
3051 if (u8Data != 0x30)
3052 {
3053 DBG_INTERN_DVBT2(printf("\n[INTERN_DVBT2_GetPlpBitMap] Check L1 NOT Ready !! E_DMD_T2_L1_FLAG = 0x%x\n", u8Data));
3054 return FALSE;
3055 }
3056 while (indx < 32)
3057 {
3058 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_PLP_ID_ARR + indx, &u8Data);
3059 u8PlpBitMap[indx] = u8Data;
3060 indx++;
3061 }
3062
3063 if (status)
3064 {
3065 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap data+++++++++++++++\n"));
3066 for (indx = 0; indx < 32; indx++)
3067 DBG_INTERN_DVBT2(printf("[%d] ", u8PlpBitMap[indx]));
3068 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap end+++++++++++++++\n"));
3069 }
3070 return status;
3071 }
3072
INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)3073 MS_BOOL INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
3074 {
3075 MS_BOOL status = TRUE;
3076 MS_U8 u8Data = 0;
3077 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
3078 if (u8Data != 0x30)
3079 {
3080 printf(">>>dvbt2 L1 not ready yet\n");
3081 return FALSE;
3082 }
3083 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_DVBT2_LOCK_HIS, &u8Data);
3084
3085 if ((u8Data & BIT(7)) == 0x00)
3086 {
3087 printf(">>>dvbt2 is un-lock\n");
3088 return FALSE;
3089 }
3090 // assign PLP-ID value
3091 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x78) * 2, u8PlpID);
3092 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x01); // MEM_EN
3093 MsOS_DelayTask(1);
3094 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x79) * 2, u8GroupID);
3095 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x00); // ~MEM_EN
3096
3097 return status;
3098 }
3099
INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID,MS_U8 u8GroupID)3100 MS_BOOL INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID, MS_U8 u8GroupID)
3101 {
3102 MS_BOOL status = TRUE;
3103
3104 // assign Group-ID and PLP-ID value (must be written in order)
3105 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_GROUP_ID, u8GroupID);
3106 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
3107
3108 return status;
3109 }
3110
3111 #if (AUTO_TS_DATA_RATE)
INTERN_DVBT2_GetTsDivNum(MS_U8 * u8TSDivNum)3112 MS_BOOL INTERN_DVBT2_GetTsDivNum(MS_U8* u8TSDivNum)
3113 {
3114 int TS_DATA_RATE =0;
3115 MS_U8 u8_tmp =0;
3116
3117 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_3, &u8_tmp) == FALSE)
3118 {
3119 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
3120 return FALSE;
3121 }
3122 //printf("[dvbt2] TS_DATA_RATE_3 = 0x%x \n\n", u8_tmp);
3123 TS_DATA_RATE = u8_tmp;
3124
3125 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_2, &u8_tmp) == FALSE)
3126 {
3127 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
3128 return FALSE;
3129 }
3130 //printf("[dvbt2] TS_DATA_RATE_2 = 0x%x \n\n", u8_tmp);
3131 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
3132
3133 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_1, &u8_tmp) == FALSE)
3134 {
3135 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
3136 return FALSE;
3137 }
3138 //printf("[dvbt2] TS_DATA_RATE_1 = 0x%x \n\n", u8_tmp);
3139 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
3140
3141 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_0, &u8_tmp) == FALSE)
3142 {
3143 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
3144 return FALSE;
3145 }
3146 //printf("[dvbt2] TS_DATA_RATE_0 = 0x%x \n\n", u8_tmp);
3147 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
3148
3149 DBG_AUTO_TS_DATA_RATE(printf("[dvbt2] TS_DATA_RATE_total = 0x%x %d \n\n", TS_DATA_RATE, TS_DATA_RATE));
3150
3151
3152 u8_tmp=HAL_DMD_RIU_ReadByte(0x103301);
3153 u8_tmp &= 0x01;
3154
3155 if(u8_tmp == 0x01)
3156 {
3157 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DIV_288, &u8_tmp) == FALSE)
3158 {
3159 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
3160 return FALSE;
3161 }
3162 *u8TSDivNum = u8_tmp;
3163
3164 DBG_AUTO_TS_DATA_RATE(printf(" CLK Source: 288 MHz \n"));
3165 }
3166 else
3167 {
3168 printf("@@@@@@@@@@@@@ DVB-T2 TS clock source error!!!\n");
3169 }
3170
3171
3172 if (*u8TSDivNum > 0x1f)// 36 MHz/8 = 4.5 MHz
3173 *u8TSDivNum = 0x1f;
3174
3175 if (*u8TSDivNum < 0x0f)// 72 MHz/8 = 9 MHz
3176 *u8TSDivNum = 0x0f;
3177
3178 DBG_AUTO_TS_DATA_RATE(printf(">>>INTERN_DVBT2_GetTsDivNum = 0x%x<<<\n", *u8TSDivNum));
3179
3180 return TRUE;
3181 }
3182
INTERN_DVBT2_ConfigAdaptiveTsDivNum(void)3183 MS_BOOL INTERN_DVBT2_ConfigAdaptiveTsDivNum(void)
3184 {
3185 MS_U8 u8TSDivNum =0;
3186 MS_U8 u8_tmp =0;
3187
3188 //check if TS DATA RATE change
3189 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_CHANGE_IND, &u8_tmp) == FALSE)
3190 {
3191 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
3192 return FALSE;
3193 }
3194
3195 if (u8_tmp ==1)
3196 {
3197 INTERN_DVBT2_GetTsDivNum(&u8TSDivNum);
3198 DBG_INTERN_DVBT2(printf(">>>INTERN_DVBT2_GetLock TsClkDivNum = 0x%x<<<\n", u8TSDivNum));
3199 DBG_AUTO_TS_DATA_RATE(printf(">>>TS_DATA_RATE_CHANGE Detected: TsClkDivNum = 0x%x<<<\n", u8TSDivNum));
3200 // ** Caution: for TS parallel mode
3201 HAL_DMD_RIU_WriteByte(0x103300, u8TSDivNum);
3202 MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_RATE_CHANGE_IND,0x00);
3203 }
3204
3205 return TRUE;
3206 }
3207 #endif
3208
3209 #if (INTERN_DVBT2_INTERNAL_DEBUG == 1)
INTERN_DVBT2_get_demod_state(MS_U8 * state)3210 void INTERN_DVBT2_get_demod_state(MS_U8* state)
3211 {
3212 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
3213 return;
3214 }
3215
INTERN_DVBT2_Show_ChannelLength(void)3216 MS_BOOL INTERN_DVBT2_Show_ChannelLength(void)
3217 {
3218 MS_U8 status = true;
3219 MS_U8 tmp = 0;
3220 MS_U16 len = 0;
3221 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
3222 len = tmp;
3223 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
3224 len = (len<<8)|tmp;
3225 printf("[dvbt]Hw_channel=%d\n",len);
3226 return status;
3227 }
3228
INTERN_DVBT2_Show_SW_ChannelLength(void)3229 MS_BOOL INTERN_DVBT2_Show_SW_ChannelLength(void)
3230 {
3231 MS_U8 status = true;
3232 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
3233 MS_U16 sw_len = 0;
3234 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
3235 sw_len = tmp;
3236 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
3237 sw_len = (sw_len<<8)|tmp;
3238 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
3239 peak_num = tmp;
3240 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
3241 insideGI = tmp&0x01;
3242 stoptracking = (tmp&0x02)>>1;
3243 flag_short_echo = (tmp&0x0C)>>2;
3244 fsa_mode = (tmp&0x30)>>4;
3245
3246 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
3247 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
3248
3249 return status;
3250 }
3251
INTERN_DVBT2_Show_ACI_CI(void)3252 MS_BOOL INTERN_DVBT2_Show_ACI_CI(void)
3253 {
3254
3255 #define BIT4 0x10
3256 MS_U8 status = true;
3257 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
3258
3259 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
3260 digACI = (tmp&BIT4)>>4;
3261
3262 // get flag_CI
3263 // 0: No interference
3264 // 1: CCI
3265 // 2: in-band ACI
3266 // 3: N+1 ACI
3267 // flag_ci = (tmp&0xc0)>>6;
3268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
3269 flag_CI = (tmp&0xC0)>>6;
3270 td_coef = (tmp&0x0C)>>2;
3271
3272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
3273
3274 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
3275
3276 return status;
3277 }
3278
INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)3279 MS_BOOL INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)
3280 {
3281 MS_U8 status = true;
3282 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
3283 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
3284 fd = tmp;
3285 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
3286 ch_len = tmp;
3287 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
3288 snr_sel = (tmp>>4)&0x03;
3289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
3290 pertone_num = tmp;
3291
3292 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
3293
3294 return status;
3295 }
3296
INTERN_DVBT2_Get_CFO(void)3297 MS_BOOL INTERN_DVBT2_Get_CFO(void)
3298 {
3299 #if 0
3300 float N = 0, FreqB = 0;
3301 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
3302 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
3303 MS_U8 reg_frz = 0, reg = 0;
3304 MS_U8 status = 0;
3305 MS_U8 u8BW = 8;
3306
3307 FreqB = (float)u8BW * 8 / 7;
3308
3309 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
3310
3311 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
3312
3313 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
3314 RegCfoTd = reg;
3315
3316 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
3317 RegCfoTd = (RegCfoTd << 8)|reg;
3318
3319 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
3320 RegCfoTd = (RegCfoTd << 8)|reg;
3321
3322 FreqCfoTd = (float)RegCfoTd;
3323
3324 if (RegCfoTd & 0x800000)
3325 FreqCfoTd = FreqCfoTd - (float)0x1000000;
3326
3327 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
3328
3329 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
3330
3331 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
3332 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
3333
3334 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3335
3336 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
3337 RegCfoFd = reg;
3338
3339 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
3340 RegCfoFd = (RegCfoFd << 8)|reg;
3341
3342 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
3343 RegCfoFd = (RegCfoFd << 8)|reg;
3344
3345 FreqCfoFd = (float)RegCfoFd;
3346
3347 if (RegCfoFd & 0x800000)
3348 FreqCfoFd = FreqCfoFd - (float)0x1000000;
3349
3350 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
3351
3352 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
3353 RegIcfo = reg & 0x07;
3354
3355 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
3356 RegIcfo = (RegIcfo << 8)|reg;
3357
3358 FreqIcfo = (float)RegIcfo;
3359
3360 if (RegIcfo & 0x400)
3361 FreqIcfo = FreqIcfo - (float)0x800;
3362
3363 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
3364 reg = reg & 0x30;
3365
3366 switch (reg)
3367 {
3368 case 0x00: N = 2048; break;
3369 case 0x20: N = 4096; break;
3370 case 0x10:
3371 default: N = 8192; break;
3372 }
3373
3374 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
3375 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
3376 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
3377 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3378 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
3379
3380 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
3381 return status;
3382 #endif
3383 return true;
3384 }
INTERN_DVBT2_Get_SFO(void)3385 MS_BOOL INTERN_DVBT2_Get_SFO(void)
3386 {
3387 #if 0
3388 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
3389 MS_BOOL status = true;
3390 MS_U8 reg = 0;
3391 float FreqB = 9.143, FreqS = 45.473; //20.48
3392 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
3393 float sfo_value = 0;
3394
3395 // get Reg_TDP_SFO,
3396 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
3397 Reg_TDP_SFO = reg;
3398 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
3399 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3400 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
3401 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3402
3403 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3404
3405 // get Reg_FDP_SFO,
3406 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
3407 Reg_FDP_SFO = reg;
3408 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
3409 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3410 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
3411 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3412
3413 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3414
3415 // get Reg_FSA_SFO,
3416 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
3417 Reg_FSA_SFO = reg;
3418 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
3419 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3420 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
3421 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3422
3423 // get Reg_FSA_IN,
3424 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
3425 Reg_FSA_IN = reg;
3426 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
3427 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
3428 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
3429
3430 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
3431 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
3432
3433 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
3434 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
3435 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
3436
3437
3438 return status;
3439 #endif
3440 return true;
3441 }
3442
INTERN_DVBT2_Get_SYA_status(void)3443 void INTERN_DVBT2_Get_SYA_status(void)
3444 {
3445 MS_U8 status = true;
3446 MS_U8 sya_k = 0,reg = 0;
3447 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
3448
3449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
3450 sya_k = reg;
3451
3452 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
3453 sya_th = reg;
3454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
3455 sya_th = (sya_th<<8)|reg;
3456
3457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
3458 sya_offset = reg;
3459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
3460 sya_offset = (sya_offset<<8)|reg;
3461
3462 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
3463 len_m = reg;
3464 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
3465 len_m = (len_m<<8)|reg;
3466
3467 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
3468 len_b = reg;
3469 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
3470 len_b = (len_b<<8)|reg;
3471
3472
3473 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
3474 len_a = reg;
3475 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
3476 len_a = (len_a<<8)|reg;
3477
3478
3479 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
3480 tracking_reg = reg;
3481
3482
3483 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
3484 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
3485
3486 return;
3487 }
3488
INTERN_DVBT2_Get_cci_status(void)3489 void INTERN_DVBT2_Get_cci_status(void)
3490 {
3491 MS_U8 status = true;
3492 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
3493
3494 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
3495 cci_fsweep = reg;
3496
3497 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
3498 cci_kp = reg;
3499
3500 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
3501
3502 return;
3503 }
3504
INTERN_DVBT2_Show_PRESFO_Info(void)3505 MS_BOOL INTERN_DVBT2_Show_PRESFO_Info(void)
3506 {
3507 MS_U8 tmp = 0;
3508 MS_BOOL status = TRUE;
3509 printf("\n[SFO]");
3510 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
3511 printf("[%x]",tmp);
3512 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
3513 printf("[%x]",tmp);
3514 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
3515 printf("[%x]",tmp);
3516 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
3517 printf("[%x]",tmp);
3518 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
3519 printf("[%x]",tmp);
3520 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
3521 printf("[%x]",tmp);
3522 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
3523 printf("[%x]",tmp);
3524 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
3525 printf("[%x][End]",tmp);
3526
3527 return status;
3528 }
3529
INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 * locktime)3530 MS_BOOL INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 *locktime)
3531 {
3532 MS_BOOL status = true;
3533
3534 *locktime = 0xffff;
3535 printf("[dvbt]INTERN_DVBT2_Get_Lock_Time_Info not implement\n");
3536
3537 status = false;
3538 return status;
3539 }
3540
3541
INTERN_DVBT2_Show_Lock_Time_Info(void)3542 MS_BOOL INTERN_DVBT2_Show_Lock_Time_Info(void)
3543 {
3544 MS_U16 locktime = 0;
3545 MS_BOOL status = TRUE;
3546 status &= INTERN_DVBT2_Get_Lock_Time_Info(&locktime);
3547 printf("[DVBT]lock_time = %d ms\n",locktime);
3548 return status;
3549 }
3550
INTERN_DVBT2_Show_BER_Info(void)3551 MS_BOOL INTERN_DVBT2_Show_BER_Info(void)
3552 {
3553 MS_U8 tmp = 0;
3554 MS_BOOL status = TRUE;
3555 printf("\n[BER]");
3556 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
3557 printf("[%x,",tmp);
3558 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
3559 printf("%x]",tmp);
3560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
3561 printf("[%x,",tmp);
3562 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
3563 printf("%x]",tmp);
3564 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
3565 printf("[%x,",tmp);
3566 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
3567 printf("%x][End]",tmp);
3568
3569 return status;
3570
3571 }
3572
3573
INTERN_DVBT2_Show_AGC_Info(void)3574 MS_BOOL INTERN_DVBT2_Show_AGC_Info(void)
3575 {
3576 MS_U8 tmp = 0;
3577 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
3578 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
3579 MS_U16 if_agc_err = 0;
3580 MS_BOOL status = TRUE;
3581 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
3582
3583 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
3584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
3585 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
3586 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
3587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
3588 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
3589
3590
3591 // select IF gain to read
3592 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3593 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
3594
3595 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3596 if_agc_gain = tmp;
3597 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3598 if_agc_gain = (if_agc_gain<<8)|tmp;
3599
3600
3601 // select d1 gain to read.
3602 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3603 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3604
3605 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3606 d1_gain = tmp;
3607 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3608 d1_gain = (d1_gain<<8)|tmp;
3609
3610 // select d2 gain to read.
3611 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3612 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3613
3614 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3615 d2_gain = tmp;
3616 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3617 d2_gain = (d2_gain<<8)|tmp;
3618
3619 // select IF gain err to read
3620 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3621 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3622
3623 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3624 if_agc_err = tmp;
3625 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3626 if_agc_err = (if_agc_err<<8)|tmp;
3627
3628 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3629 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3630 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3631
3632
3633
3634 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3635 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3636
3637 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3638 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3639
3640 return status;
3641 }
3642
INTERN_DVBT2_Show_WIN_Info(void)3643 MS_BOOL INTERN_DVBT2_Show_WIN_Info(void)
3644 {
3645 MS_U8 tmp = 0;
3646 MS_U8 trigger = 0;
3647 MS_U16 win_len = 0;
3648
3649 MS_BOOL status = TRUE;
3650
3651 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3652 win_len = tmp;
3653 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3654 win_len = (win_len<<8)|tmp;
3655
3656 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3657
3658 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3659
3660 return status;
3661 }
3662
INTERN_DVBT2_Show_td_coeff(void)3663 void INTERN_DVBT2_Show_td_coeff(void)
3664 {
3665 MS_U8 status = true;
3666 MS_U8 w1 = 0,w2 = 0,reg = 0;
3667
3668 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3669 w1 = reg;
3670
3671 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3672 w2 = reg;
3673
3674 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
3675
3676 return;
3677 }
3678
3679 /********************************************************
3680 *Constellation (b2 ~ b0) : 0~3 => QPSK, 16QAM, 64QAM, 256QAM
3681 *Code Rate (b5 ~ b3) : 0~5 => 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
3682 *GI (b8 ~ b6) : 0~6 => 1/32, 1/16, 1/8, 1/4, 1/128, 19/128, 19/256
3683 *FFT (b11 ~ b9) : 0~7 => 2K, 8K, 4K, 1K, 16K, 32K, 8KE, 32KE
3684 *Preamble(b12) : 0~1 => mixed, not_mixed
3685 *S1_Signaling(b14~b13) : 0~3 => t2_siso, t2_miso, "non_t2, reserved
3686 *pilot_pattern(b18~b15) : 0~8 => PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8
3687 *BW_Extend(b19) : 0~1 => normal, extension
3688 *PAPR(b22~b20) : 0~4 => none, ace, tr, tr_and_ace, reserved
3689 ********************************/
INTERN_DVBT2_Show_Modulation_info(void)3690 MS_BOOL INTERN_DVBT2_Show_Modulation_info(void)
3691 {
3692 MS_BOOL bRet = TRUE;
3693 MS_U16 u16Data = 0;
3694
3695 char* cConStr[] = {"qpsk", "16qam", "64qam", "256qam"};
3696 char* cCRStr[] = {"1_2", "3_5", "2_3", "3_4", "4_5", "5_6"};
3697 char* cGIStr[] = {"1_32", "1_16", "1_8", "1_4", "1_128", "19_128", "19_256"};
3698 char* cFFTStr[] = {"2k", "8k", "4k", "1k", "16k", "32k", "8k", "32k"};
3699 char* cPreAStr[] = {"mixed", "not_mixed"};
3700 char* cS1SStr[] = {"t2_siso", "t2_miso", "non_t2", "reserved"};
3701 char* cPPSStr[] = {"PP1", "PP2", "PP3", "PP4", "PP5", "PP6", "PP7", "PP8", "reserved"};
3702 char* cBWStr[] = {"normal", "extension"};
3703 char* cPAPRStr[] = {"none", "ace", "tr", "tr_and_ace", "reserved"};
3704
3705 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
3706 {
3707
3708 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_MODUL_MODE) == FALSE)
3709 {
3710 printf("T2_MODUL_MODE Error!\n");
3711 bRet = FALSE;
3712 }
3713 u16Data &= 0x07;
3714 //*L1_Info = (MS_U64)(u16Data);
3715 printf("T2 Constellation:%s\n", cConStr[u16Data]);
3716
3717 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_CODE_RATE) == FALSE)
3718 {
3719 printf(("T2_CODE_RATE Error!\n"));
3720 bRet = FALSE;
3721 }
3722 u16Data &= 0x07;
3723 //*L1_Info |= (MS_U64)(u16Data << 3);
3724 printf("T2 Code Rate:%s\n", cCRStr[u16Data]);
3725
3726 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_GUARD_INTERVAL) == FALSE)
3727 {
3728 printf("T2_GUARD_INTERVAL Error!\n");
3729 bRet = FALSE;
3730 }
3731 u16Data &= 0x07;
3732 //*L1_Info |= (MS_U64)(u16Data << 6);
3733 printf("T2 GI:%s\n", cGIStr[u16Data]);
3734
3735 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_FFT_VALUE) == FALSE)
3736 {
3737 printf("T2_FFT_VALUE Error!\n");
3738 bRet = FALSE;
3739 }
3740 u16Data &= 0x07;
3741 //*L1_Info |= (MS_U64)(u16Data << 9);
3742 printf("T2 FFT:%s\n", cFFTStr[u16Data]);
3743
3744 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PREAMBLE) == FALSE)
3745 {
3746 printf("T2_PREAMBLE Error!\n");
3747 bRet = FALSE;
3748 }
3749 u16Data &= 0x01;
3750 //*L1_Info |= (MS_U64)(u16Data << 12);
3751 printf("Preamble:%s\n", cPreAStr[u16Data]);
3752
3753 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_S1_SIGNALLING) == FALSE)
3754 {
3755 printf("T2_S1_SIGNALLING Error!\n");
3756 bRet = FALSE;
3757 }
3758 u16Data &= 0x03;
3759 if (u16Data > 2)
3760 u16Data = 3;
3761 //*L1_Info |= (MS_U64)(u16Data << 13);
3762 printf("S1 Signalling:%s\n", cS1SStr[u16Data]);
3763
3764 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PILOT_PATTERN) == FALSE)
3765 {
3766 printf("T2_PILOT_PATTERN Error!\n");
3767 bRet = FALSE;
3768 }
3769 u16Data &= 0x0F;
3770 if (u16Data > 7)
3771 u16Data = 8;
3772 //*L1_Info |= (MS_U64)(u16Data << 15);
3773 printf("PilotPattern:%s\n", cPPSStr[u16Data]);
3774
3775 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_BW_EXT) == FALSE)
3776 {
3777 printf("T2_BW_EXT Error!\n");
3778 bRet = FALSE;
3779 }
3780 u16Data &= 0x01;
3781 //*L1_Info |= (MS_U64)(u16Data << 19);
3782 printf("BW EXT:%s\n", cBWStr[u16Data]);
3783
3784 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PAPR_REDUCTION) == FALSE)
3785 {
3786 printf("T2_PAPR_REDUCTION Error!\n");
3787 bRet = FALSE;
3788 }
3789 u16Data &= 0x07;
3790 if (u16Data > 3)
3791 u16Data = 4;
3792 //*L1_Info |= (MS_U64)(u16Data << 20);
3793 printf("T2 PAPR:%s\n", cPAPRStr[u16Data]);
3794
3795 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_OFDM_SYMBOLS_PER_FRAME) == FALSE)
3796 {
3797 printf("T2_OFDM_SYMBOLS_PER_FRAME Error!\n");
3798 bRet = FALSE;
3799 }
3800 u16Data &= 0xFFF;
3801 //*L1_Info |= (MS_U64)(u16Data << 23);
3802 printf("T2 OFDM Symbols:%u\n", u16Data);
3803 }
3804 else
3805 {
3806 printf("INVALID\n");
3807 return FALSE;
3808 }
3809
3810 return bRet;
3811
3812 }
3813
3814
INTERN_DVBT2_Show_BER_PacketErr(void)3815 void INTERN_DVBT2_Show_BER_PacketErr(void)
3816 {
3817 // float f_ber = 0;
3818 MS_U16 packetErr = 0;
3819 // INTERN_DVBT2_GetPostLdpcBer(&f_ber);
3820 INTERN_DVBT2_GetPacketErr(&packetErr);
3821
3822 // printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3823 return;
3824 }
3825
INTERN_DVBT2_Show_Lock_Info(void)3826 MS_BOOL INTERN_DVBT2_Show_Lock_Info(void)
3827 {
3828
3829 printf("[dvbt]INTERN_DVBT2_Show_Lock_Info not implement!!!\n");
3830 return false;
3831 }
3832
3833
INTERN_DVBT2_Show_Demod_Info(void)3834 MS_BOOL INTERN_DVBT2_Show_Demod_Info(void)
3835 {
3836 MS_U8 demod_state = 0;
3837 MS_BOOL status = true;
3838 static MS_U8 counter = 0;
3839
3840 INTERN_DVBT2_get_demod_state(&demod_state);
3841
3842 printf("==========[dvbt]state=%d\n",demod_state);
3843 if (demod_state < 5)
3844 {
3845 INTERN_DVBT2_Show_Demod_Version();
3846 INTERN_DVBT2_Show_AGC_Info();
3847 INTERN_DVBT2_Show_ACI_CI();
3848 }
3849 else if(demod_state < 8)
3850 {
3851 INTERN_DVBT2_Show_Demod_Version();
3852 INTERN_DVBT2_Show_AGC_Info();
3853 INTERN_DVBT2_Show_ACI_CI();
3854 INTERN_DVBT2_Show_ChannelLength();
3855 INTERN_DVBT2_Get_CFO();
3856 INTERN_DVBT2_Get_SFO();
3857 INTERN_DVBT2_Show_td_coeff();
3858 }
3859 else if(demod_state < 11)
3860 {
3861 INTERN_DVBT2_Show_Demod_Version();
3862 INTERN_DVBT2_Show_AGC_Info();
3863 INTERN_DVBT2_Show_ACI_CI();
3864 INTERN_DVBT2_Show_ChannelLength();
3865 INTERN_DVBT2_Get_CFO();
3866 INTERN_DVBT2_Get_SFO();
3867 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3868 INTERN_DVBT2_Get_SYA_status();
3869 INTERN_DVBT2_Show_td_coeff();
3870 }
3871 else if((demod_state == 11) && ((counter%4) == 0))
3872 {
3873 INTERN_DVBT2_Show_Demod_Version();
3874 INTERN_DVBT2_Show_AGC_Info();
3875 INTERN_DVBT2_Show_ACI_CI();
3876 INTERN_DVBT2_Show_ChannelLength();
3877 INTERN_DVBT2_Get_CFO();
3878 INTERN_DVBT2_Get_SFO();
3879 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3880 INTERN_DVBT2_Get_SYA_status();
3881 INTERN_DVBT2_Show_td_coeff();
3882 INTERN_DVBT2_Show_Modulation_info();
3883 INTERN_DVBT2_Show_BER_PacketErr();
3884 }
3885 else
3886 status = false;
3887
3888 printf("===========================\n");
3889 counter++;
3890
3891 return status;
3892 }
3893 #endif