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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #include "ULog.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
133
134 #define TDE_REG_BASE 0x2400UL
135 #define DIV_REG_BASE 0x2500UL
136 #define TR_REG_BASE 0x2600UL
137 #define FTN_REG_BASE 0x2800UL
138 #define FTNEXT_REG_BASE 0x2900UL
139 #define MBX_REG_BASE 0x2F00UL
140
141
142
143 #if 0//ENABLE_SCAN_ONELINE_MSG
144 #define DBG_INTERN_DVBT_ONELINE(x) x
145 #else
146 #define DBG_INTERN_DVBT_ONELINE(x) // x
147 #endif
148
149 #ifdef MS_DEBUG
150 #define DBG_INTERN_DVBT(x) x
151 #define DBG_GET_SIGNAL(x) x
152 #define DBG_INTERN_DVBT_TIME(x) x
153 #define DBG_INTERN_DVBT_LOCK(x) x
154 #else
155 #define DBG_INTERN_DVBT(x) //x
156 #define DBG_GET_SIGNAL(x) //x
157 #define DBG_INTERN_DVBT_TIME(x) // x
158 #define DBG_INTERN_DVBT_LOCK(x) //x
159 #endif
160 #define DBG_DUMP_LOAD_DSP_TIME 0
161
162 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
163 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
164 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
165 #define INTERN_DVBT_INTERNAL_DEBUG 1
166
167 #define SIGNAL_LEVEL_OFFSET 0.00
168 #define TAKEOVERPOINT -59.0
169 #define TAKEOVERRANGE 0.5
170 #define LOG10_OFFSET -0.21
171 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
172 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
173
174
175 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
176 #define TUNER_VPP 2
177 #define IF_AGC_VPP 2
178 #else
179 #define TUNER_VPP 1
180 #define IF_AGC_VPP 2
181 #endif
182
183 #if (TUNER_VPP == 1)
184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
185 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
186 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
187 #endif
188
189 /*BEG INTERN_DVBT_DSPREG_TABLE*/
190 #define D_DMD_DVBT_PARAM_VERSION 0x01
191 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
192 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
193 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
194 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
195 #define D_DMD_DVBT_OP_DCR_EN 0x01
196 #define D_DMD_DVBT_OP_IIS_EN 0x01
197 #define D_DMD_DVBT_OP_IQB_EN 0x00
198 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
199 #define D_DMD_DVBT_OP_ACI_EN 0x01
200 #define D_DMD_DVBT_OP_CCI_EN 0x01
201 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
202 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
203 #define D_DMD_DVBT_CFG_BW 0x03 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
204 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
205 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
206 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
207 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
208 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
209 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
210 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
211 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
212 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
213 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
214 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
215 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
216 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
217 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
218 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
219 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
220 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
221 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
222 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
223
224 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
225 #define D_DMD_DVBT_CFG_FC_H 0x4E
226 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
227 #define D_DMD_DVBT_CFG_FS_H 0x5D
228 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
229
230 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
231 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
232 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
233 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
234 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
235 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
236 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
237 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
238 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
239 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
240 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
241 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
242
243 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
244 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
245 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
246 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
247 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
248 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
249 #else
250 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
251 #endif
252 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
253 //#define DMD_DVBT_CHECKSUM 0x00
254 /*END INTERN_DVBT_DSPREG_TABLE*/
255 #define DVBT_FS 24000 // 24000
256 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
257 #define FC_L 0x20 // 0323 jason
258 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
259 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
260 #define SET_ZIF 0x00
261 #define IQB_EN 0x00
262
263 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
264 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
265 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
266 #define CSTL 0x02 //0:QPSK 1:16 2: 64
267 #define HIER 0x00
268 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
269 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
270 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
271 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
272 #define LP_SEL 0x00 // LP select
273 #define IQ_SWAP 0x00 //0x01
274 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
275 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
276 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
277 #define TS_SER 0
278 #define TS_INV 0
279 #define FIF_H 0x13
280 #define FIF_L 0x88
281 #define IF_INV_PWM 0x00
282 #define T_LOWIF 1
283
284 MS_U8 INTERN_DVBT_DSPREG[] =
285 {
286 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
287 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
288 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
289 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
290 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
291 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
292 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
293 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
294 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
295 /*
296 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
297 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
298 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
299 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
300 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
301 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
302 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
303 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
304 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
305 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
306 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
307 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
308 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
309 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
310 */
311 };
312 /*END INTERN_DVBT_DSPREG_TABLE*/
313 //-----------------------------------------------------------------------
314 /****************************************************************
315 *Local Variables *
316 ****************************************************************/
317 static MS_BOOL bFECLock=0;
318 static MS_BOOL bTPSLock = 0;
319 static MS_U32 u32ChkScanTimeStart = 0;
320 static MS_U32 u32FecFirstLockTime=0;
321 static MS_U32 u32FecLastLockTime=0;
322 static float fViterbiBerFiltered=-1;
323 //Global Variables
324 S_CMDPKTREG gsCmdPacket;
325 //U8 gCalIdacCh0, gCalIdacCh1;
326
327 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
328 MS_U8 INTERN_DVBT_table[] = {
329 #include "fwDMD_INTERN_DVBT.dat"
330 };
331
332 #endif
333
334 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
335 {
336 { _QPSK , _CR1Y2, -93},
337 { _QPSK , _CR2Y3, -91},
338 { _QPSK , _CR3Y4, -90},
339 { _QPSK , _CR5Y6, -89},
340 { _QPSK , _CR7Y8, -88},
341
342 { _16QAM , _CR1Y2, -87},
343 { _16QAM , _CR2Y3, -85},
344 { _16QAM , _CR3Y4, -84},
345 { _16QAM , _CR5Y6, -83},
346 { _16QAM , _CR7Y8, -82},
347
348 { _64QAM , _CR1Y2, -82},
349 { _64QAM , _CR2Y3, -80},
350 { _64QAM , _CR3Y4, -78},
351 { _64QAM , _CR5Y6, -77},
352 { _64QAM , _CR7Y8, -76},
353 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
354 };
355
356
357
358 static void INTERN_DVBT_SignalQualityReset(void);
359 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
360
INTERN_DVBT_SignalQualityReset(void)361 static void INTERN_DVBT_SignalQualityReset(void)
362 {
363 u32FecFirstLockTime=0;
364 fViterbiBerFiltered=-1;
365 }
366
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)367 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
368 {
369 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
370 MS_BOOL status = TRUE;
371 MS_U16 u16DspAddr = 0;
372
373 ULOGD("DEMOD","INTERN_DVBT_DSPReg_Init\n");
374
375 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
376 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
377
378 if (u8DVBT_DSPReg != NULL)
379 {
380 /*temp solution until new dsp table applied.*/
381 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
382 if (u8DVBT_DSPReg[0] >= 1)
383 {
384 u8DVBT_DSPReg+=2;
385 for (idx = 0; idx<u8Size; idx++)
386 {
387 u16DspAddr = *u8DVBT_DSPReg;
388 u8DVBT_DSPReg++;
389 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
390 u8DVBT_DSPReg++;
391 u8Mask = *u8DVBT_DSPReg;
392 u8DVBT_DSPReg++;
393 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
394 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
395 u8DVBT_DSPReg++;
396 ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite);
397 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
398 }
399 }
400 else
401 {
402 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
403 }
404 }
405
406 return status;
407 }
408
409 /***********************************************************************************
410 Subject: Command Packet Interface
411 Function: INTERN_DVBT_Cmd_Packet_Send
412 Parmeter:
413 Return: MS_BOOL
414 Remark:
415 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)416 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
417 {
418
419 return TRUE;
420
421 }
422
423
424 /***********************************************************************************
425 Subject: Command Packet Interface
426 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
427 Parmeter:
428 Return: MS_BOOL
429 Remark:
430 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)431 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
432 {
433 return TRUE;
434 }
435
436 /***********************************************************************************
437 Subject: SoftStop
438 Function: INTERN_DVBT_SoftStop
439 Parmeter:
440 Return: MS_BOOL
441 Remark:
442 ************************************************************************************/
443
INTERN_DVBT_SoftStop(void)444 MS_BOOL INTERN_DVBT_SoftStop ( void )
445 {
446 #if 1
447 MS_U16 u8WaitCnt=0;
448
449 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
450 {
451 ULOGD("DEMOD",">> MB Busy!\n");
452 return FALSE;
453 }
454
455 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
456
457 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
458 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
459
460 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
461 {
462 #if TEST_EMBEDED_DEMOD
463 MsOS_DelayTask(1); // << Ken 20090629
464 #endif
465 if (u8WaitCnt++ >= 0x7FFF)
466 {
467 ULOGD("DEMOD",">> DVBT SoftStop Fail!\n");
468 return FALSE;
469 }
470 }
471
472 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
473 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
474 #endif
475 return TRUE;
476 }
477
478
479 /***********************************************************************************
480 Subject: Reset
481 Function: INTERN_DVBT_Reset
482 Parmeter:
483 Return: MS_BOOL
484 Remark:
485 ************************************************************************************/
486 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)487 MS_BOOL INTERN_DVBT_Reset ( void )
488 {
489 ULOGD("DEMOD"," @INTERN_DVBT_reset\n");
490
491 //ULOGD("DEMOD","INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime());
492
493 // INTERN_DVBT_SoftStop();
494
495
496 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
497 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
498 MsOS_DelayTask(5);
499 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
500 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
501 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
502 MsOS_DelayTask(5);
503
504 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
505 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
506
507 bFECLock = FALSE;
508 bTPSLock = FALSE;
509 u32ChkScanTimeStart = MsOS_GetSystemTime();
510 return TRUE;
511 }
512
513 /***********************************************************************************
514 Subject: Exit
515 Function: INTERN_DVBT_Exit
516 Parmeter:
517 Return: MS_BOOL
518 Remark:
519 ************************************************************************************/
INTERN_DVBT_Exit(void)520 MS_BOOL INTERN_DVBT_Exit ( void )
521 {
522
523 INTERN_DVBT_SoftStop();
524
525
526
527 return TRUE;
528 }
529
530 /***********************************************************************************
531 Subject: Load DSP code to chip
532 Function: INTERN_DVBT_LoadDSPCode
533 Parmeter:
534 Return: MS_BOOL
535 Remark:
536 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)537 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
538 {
539 MS_U8 udata = 0x00;
540 MS_U16 i;
541 MS_U16 fail_cnt=0;
542
543 #if (DBG_DUMP_LOAD_DSP_TIME==1)
544 MS_U32 u32Time;
545 #endif
546
547
548 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
549 BININFO BinInfo;
550 MS_BOOL bResult;
551 MS_U32 u32GEAddr;
552 MS_U8 Data;
553 MS_S8 op;
554 MS_U32 srcaddr;
555 MS_U32 len;
556 MS_U32 SizeBy4K;
557 MS_U16 u16Counter=0;
558 MS_U8 *pU8Data;
559 #endif
560
561
562
563 // MDrv_Sys_DisableWatchDog();
564
565
566 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
567 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
568 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
569 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
570 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
571 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
572
573 //// Load code thru VDMCU_IF ////
574 ULOGD("DEMOD",">Load Code...\n");
575 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
576 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
577 {
578 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
579 }
580 #else
581 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
582 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
583 if ( bResult != PASS )
584 {
585 return FALSE;
586 }
587 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
588
589 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
590 InfoBlock_Flash_2_Checking_Start(&BinInfo);
591 #endif
592
593 #if OBA2
594 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
595 #else
596 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
597 #endif
598
599 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
600 InfoBlock_Flash_2_Checking_End(&BinInfo);
601 #endif
602
603 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
604 SizeBy4K=BinInfo.B_Len/0x1000;
605 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
606
607 #if (DBG_DUMP_LOAD_DSP_TIME==1)
608 u32Time = msAPI_Timer_GetTime0();
609 #endif
610
611 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
612
613 for (i=0;i<=SizeBy4K;i++)
614 {
615 if(i==SizeBy4K)
616 len=BinInfo.B_Len%0x1000;
617 else
618 len=0x1000;
619
620 srcaddr = u32GEAddr+(0x1000*i);
621 //ULOGD("DEMOD","\t i = %08X\n", i);
622 //ULOGD("DEMOD","\t len = %08X\n", len);
623 op = 1;
624 u16Counter = 0 ;
625 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
626 while(len--)
627 {
628 u16Counter ++ ;
629 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
630 //pU8Data = (U8 *)(srcaddr|0x80000000);
631 #if OBA2
632 pU8Data = (U8 *)(srcaddr);
633 #else
634 pU8Data = (U8 *)(srcaddr|0x80000000);
635 #endif
636 Data = *pU8Data;
637
638 #if 0
639 if(u16Counter < 0x100)
640 ULOGD("DEMOD","0x%bx,", Data);
641 #endif
642 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
643
644 srcaddr += op;
645 }
646 // ULOGD("DEMOD","\n\n\n");
647 }
648
649 #if (DBG_DUMP_LOAD_DSP_TIME==1)
650 ULOGD("DEMOD","------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
651 #endif
652
653 #endif
654
655 //// Content verification ////
656 ULOGD("DEMOD",">Verify Code...\n");
657
658 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
659 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
660
661 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
662 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
663 {
664 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
665 if (udata != INTERN_DVBT_table[i])
666 {
667 ULOGD("DEMOD",">fail add = 0x%x\n", i);
668 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBT_table[i]);
669 ULOGD("DEMOD",">data = 0x%x\n", udata);
670
671 if (fail_cnt++ > 10)
672 {
673 ULOGD("DEMOD",">DVB-T DSP Loadcode fail!");
674 return false;
675 }
676 }
677 }
678 #else
679 for (i=0;i<=SizeBy4K;i++)
680 {
681 if(i==SizeBy4K)
682 len=BinInfo.B_Len%0x1000;
683 else
684 len=0x1000;
685
686 srcaddr = u32GEAddr+(0x1000*i);
687 //ULOGD("DEMOD","\t i = %08LX\n", i);
688 //ULOGD("DEMOD","\t len = %08LX\n", len);
689 op = 1;
690 u16Counter = 0 ;
691 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
692 while(len--)
693 {
694 u16Counter ++ ;
695 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
696 //pU8Data = (U8 *)(srcaddr|0x80000000);
697 #if OBA2
698 pU8Data = (U8 *)(srcaddr);
699 #else
700 pU8Data = (U8 *)(srcaddr|0x80000000);
701 #endif
702 Data = *pU8Data;
703
704 #if 0
705 if(u16Counter < 0x100)
706 ULOGD("DEMOD","0x%bx,", Data);
707 #endif
708 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
709 if (udata != Data)
710 {
711 ULOGD("DEMOD",">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
712 ULOGD("DEMOD",">code = 0x%x\n", Data);
713 ULOGD("DEMOD",">data = 0x%x\n", udata);
714
715 if (fail_cnt++ > 10)
716 {
717 ULOGD("DEMOD",">DVB-T DSP Loadcode fail!");
718 return false;
719 }
720 }
721
722 srcaddr += op;
723 }
724 // ULOGD("DEMOD","\n\n\n");
725 }
726 #endif
727
728 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
729 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
730 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
731 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
732
733 ULOGD("DEMOD",">DSP Loadcode done.");
734 //while(load_data_variable);
735
736
737 return TRUE;
738 }
739
740 /***********************************************************************************
741 Subject: DVB-T CLKGEN initialized function
742 Function: INTERN_DVBT_Power_On_Initialization
743 Parmeter:
744 Return: MS_BOOL
745 Remark:
746 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)747 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
748 {
749 HAL_DMD_RIU_WriteByte(0x103c0e,0x00);
750 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
751 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
752 // ----------------------------------------------
753 // start demod CLKGEN setting
754 // ----------------------------------------------
755 // *** Set register at CLKGEN1
756 // enable DMD MCU clock "bit[0] set 0"
757 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
758 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
759 // CLK_DMDMCU clock setting
760 // [0] disable clock
761 // [1] invert clock
762 // [4:2]
763 // 000:170 MHz(MPLL_DIV_BUf)
764 // 001:160MHz
765 // 010:144MHz
766 // 011:123MHz
767 // 100:108MHz
768 // 101:mem_clcok
769 // 110:mem_clock div 2
770 // 111:select XTAL
771 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
772 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
773
774 // set parallet ts clock
775 HAL_DMD_RIU_WriteByte(0x103301,0x05);
776 HAL_DMD_RIU_WriteByte(0x103300,0x14);
777
778 // enable atsc, DVBTC ts clock
779 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
780 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
781 HAL_DMD_RIU_WriteByte(0x103309,0x00);
782 HAL_DMD_RIU_WriteByte(0x103308,0x00);
783
784 // enable dvbc adc clock
785 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
786 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
787 HAL_DMD_RIU_WriteByte(0x103315,0x00);
788 HAL_DMD_RIU_WriteByte(0x103314,0x00);
789
790 // Reset TS divider
791 HAL_DMD_RIU_WriteByte(0x103302,0x01);
792 HAL_DMD_RIU_WriteByte(0x103302,0x00);
793
794
795 // enable clk_atsc_adcd_sync
796 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
797 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
798 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
799 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
800
801 // enable dvbt inner clock
802 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
803 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
804 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
805 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
806
807
808
809 // enable dvbt inner clock
810 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
811 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
812 HAL_DMD_RIU_WriteByte(0x111f21,0x44);
813 HAL_DMD_RIU_WriteByte(0x111f20,0x40);
814
815 // enable dvbc outer clock
816 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
817 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
818 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
819 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
820
821
822 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
823
824 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
825 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
826
827 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
828 HAL_DMD_RIU_WriteByte(0x111f2c,0x41);
829
830
831 HAL_DMD_RIU_WriteByte(0x111f2f,0x0c);
832 HAL_DMD_RIU_WriteByte(0x111f2e,0x04);
833
834
835 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
836 HAL_DMD_RIU_WriteByte(0x111f30,0x04);
837
838 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
839 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
840
841
842 HAL_DMD_RIU_WriteByte(0x111f35,0x10);
843 HAL_DMD_RIU_WriteByte(0x111f34,0x10);
844
845 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
846 HAL_DMD_RIU_WriteByte(0x111f36,0x11);
847
848 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
849 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
850
851 HAL_DMD_RIU_WriteByte(0x111f3d,0x0c);
852 HAL_DMD_RIU_WriteByte(0x111f3c,0x04);
853
854 HAL_DMD_RIU_WriteByte(0x111f45,0x04);
855 HAL_DMD_RIU_WriteByte(0x111f44,0x44);
856
857 HAL_DMD_RIU_WriteByte(0x111f69,0x00);
858 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
859
860 HAL_DMD_RIU_WriteByte(0x111f6b,0x00);
861 HAL_DMD_RIU_WriteByte(0x111f6a,0x00);
862
863 HAL_DMD_RIU_WriteByte(0x111f6d,0x00);
864 HAL_DMD_RIU_WriteByte(0x111f6c,0x10);
865
866 HAL_DMD_RIU_WriteByte(0x111f6f,0x0c);
867 HAL_DMD_RIU_WriteByte(0x111f6e,0x40);
868
869 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
870 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
871
872 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
873 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
874
875 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
876 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
877
878 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
879 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
880
881 HAL_DMD_RIU_WriteByte(0x111f79,0x40);
882 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
883
884 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
885 HAL_DMD_RIU_WriteByte(0x111f7a,0x04);
886
887 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
888 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
889
890 HAL_DMD_RIU_WriteByte(0x111f7f,0x40);
891 HAL_DMD_RIU_WriteByte(0x111f7e,0x40);
892
893 HAL_DMD_RIU_WriteByte(0x111fe1,0x04);
894 HAL_DMD_RIU_WriteByte(0x111fe0,0x04);
895
896 HAL_DMD_RIU_WriteByte(0x111ff0,0x04);
897
898 HAL_DMD_RIU_WriteByte(0x111fe3,0x04);
899 HAL_DMD_RIU_WriteByte(0x111fe2,0x0c);
900
901 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
902 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
903
904 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
905 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
906
907 HAL_DMD_RIU_WriteByte(0x111fe9,0x04);
908 HAL_DMD_RIU_WriteByte(0x111fe8,0x0c);
909
910 HAL_DMD_RIU_WriteByte(0x111feb,0x88);
911 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
912
913 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
914 HAL_DMD_RIU_WriteByte(0x111fec,0x08);
915
916 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
917 HAL_DMD_RIU_WriteByte(0x111fee,0x88);
918
919 HAL_DMD_RIU_WriteByte(0x15298f,0x00);
920 HAL_DMD_RIU_WriteByte(0x15298e,0x00);
921
922 HAL_DMD_RIU_WriteByte(0x152991,0x00);
923 HAL_DMD_RIU_WriteByte(0x152990,0x00);
924 HAL_DMD_RIU_WriteByte(0x152992,0x00);
925
926 HAL_DMD_RIU_WriteByte(0x1529e5,0x00);
927 HAL_DMD_RIU_WriteByte(0x1529e4,0x00);
928
929
930 HAL_DMD_RIU_WriteByte(0x152971,0x10);
931 HAL_DMD_RIU_WriteByte(0x152970,0x01);
932
933 HAL_DMD_RIU_WriteByte(0x111f42,0x04);
934
935
936 // 32+4K xdata sram
937 //wriu 0x1117e0 0x23
938 //wriu 0x1117e1 0x21
939
940 //wriu 0x1117e4 0x01
941 //wriu 0x1117e6 0x11
942 HAL_DMD_RIU_WriteByte(0x1117e0,0x23);
943 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
944 HAL_DMD_RIU_WriteByte(0x1117e4,0x01);
945 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
946
947
948 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
949 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
950 }
951
952 /***********************************************************************************
953 Subject: Power on initialized function
954 Function: INTERN_DVBT_Power_On_Initialization
955 Parmeter:
956 Return: MS_BOOL
957 Remark:
958 ************************************************************************************/
959
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)960 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
961 {
962 MS_U16 status = true;
963 MS_U8 cData = 0;
964 //U8 cal_done;
965 ULOGD("DEMOD","INTERN_DVBT_Power_On_Initialization\n");
966
967 #if defined(PWS_ENABLE)
968 Mapi_PWS_Stop_VDMCU();
969 #endif
970
971 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
972 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
973 //// Firmware download //////////
974 ULOGD("DEMOD","INTERN_DVBT Load DSP...\n");
975 //MsOS_DelayTask(100);
976
977
978 {
979 if (INTERN_DVBT_LoadDSPCode() == FALSE)
980 {
981 ULOGD("DEMOD","DVB-T Load DSP Code Fail\n");
982 return FALSE;
983 }
984 else
985 {
986 ULOGD("DEMOD","DVB-T Load DSP Code OK\n");
987 }
988 }
989
990
991 //// MCU Reset //////////
992 ULOGD("DEMOD","INTERN_DVBT Reset...\n");
993 if (INTERN_DVBT_Reset() == FALSE)
994 {
995 ULOGD("DEMOD","Fail\n");
996 return FALSE;
997 }
998 else
999 {
1000 ULOGD("DEMOD","OK\n");
1001 }
1002
1003 // reset FDP
1004 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1005 // SRAM setting, DVB-T use it.
1006 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1007 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1008 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1009
1010 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1011 return status;
1012 }
1013
1014 /************************************************************************************************
1015 Subject: Driving control
1016 Function: INTERN_DVBT_Driving_Control
1017 Parmeter: bInversionEnable : TRUE For High
1018 Return: void
1019 Remark:
1020 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1021 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1022 {
1023 MS_U8 u8Temp;
1024
1025 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1026
1027 if (bEnable)
1028 {
1029 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1030 }
1031 else
1032 {
1033 u8Temp = u8Temp & (~0x01);
1034 }
1035
1036 ULOGD("DEMOD","---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp);
1037 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1038 }
1039 /************************************************************************************************
1040 Subject: Clk Inversion control
1041 Function: INTERN_DVBT_Clk_Inversion_Control
1042 Parmeter: bInversionEnable : TRUE For Inversion Action
1043 Return: void
1044 Remark:
1045 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1046 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1047 {
1048 MS_U8 u8Temp;
1049
1050 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1051
1052 if (bInversionEnable)
1053 {
1054 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1055 }
1056 else
1057 {
1058 u8Temp = u8Temp & (~0x02);
1059 }
1060
1061 ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp);
1062 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1063 }
1064 /************************************************************************************************
1065 Subject: Transport stream serial/parallel control
1066 Function: INTERN_DVBT_Serial_Control
1067 Parmeter: bEnable : TRUE For serial
1068 Return: MS_BOOL :
1069 Remark:
1070 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1071 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1072 {
1073 MS_U8 status = true;
1074
1075 return status;
1076
1077 }
1078
1079 /************************************************************************************************
1080 Subject: TS1 output control
1081 Function: INTERN_DVBT_PAD_TS1_Enable
1082 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1083 Return: void
1084 Remark:
1085 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1086 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1087 {
1088 ULOGD("DEMOD"," @INTERN_DVBT_TS1_Enable... \n");
1089
1090 if(flag) // PAD_TS1 Enable TS CLK PAD
1091 {
1092 //ULOGD("DEMOD","=== TS1_Enable ===\n");
1093 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1094 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1095 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1096 }
1097 else // PAD_TS1 Disable TS CLK PAD
1098 {
1099 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1100 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1101 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1102 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1103 }
1104 }
1105
1106 /************************************************************************************************
1107 Subject: channel change config
1108 Function: INTERN_DVBT_Config
1109 Parmeter: BW: bandwidth
1110 Return: MS_BOOL :
1111 Remark:
1112 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1113 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1114 {
1115 MS_U8 bandwidth;
1116 MS_U8 status = true;
1117
1118 ULOGD("DEMOD"," @INTERN_DVBT_config %d %d %d %d %d %d %d %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap);
1119 //ULOGD("DEMOD","INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime());
1120
1121 if (u8TSClk == 0xFF) u8TSClk=0x13;
1122 switch(BW)
1123 {
1124 case E_DMD_RF_CH_BAND_6MHz:
1125 bandwidth = 1;
1126 break;
1127 case E_DMD_RF_CH_BAND_7MHz:
1128 bandwidth = 2;
1129 break;
1130 case E_DMD_RF_CH_BAND_8MHz:
1131 default:
1132 bandwidth = 3;
1133 break;
1134 }
1135
1136 status &= INTERN_DVBT_Reset();
1137
1138 // BW mode
1139 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1140 // TS mode
1141 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1142 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1143 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1144 // Hierarchy mode
1145 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1146 // FC
1147 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1148 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1149 // FS
1150 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1151 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1152 // IQSwap
1153 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1154
1155 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1156 // Fif
1157 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1158 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1159
1160 return status;
1161 }
1162 /************************************************************************************************
1163 Subject: enable hw to lock channel
1164 Function: INTERN_DVBT_Active
1165 Parmeter: bEnable
1166 Return: MS_BOOL
1167 Remark:
1168 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1169 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1170 {
1171 MS_U8 status = true;
1172
1173 ULOGD("DEMOD"," @INTERN_DVBT_active\n");
1174
1175 //// INTERN_DVBT Finite State Machine on/off //////////
1176 #if 0
1177 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1178
1179 gsCmdPacket.param[0] = (MS_U8)bEnable;
1180 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1181 #else
1182 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1183 #endif
1184 INTERN_DVBT_SignalQualityReset();
1185
1186 return status;
1187 }
1188
1189
1190
1191
1192
1193 #ifdef SUPPORT_ADAPTIVE_TS_CLK
INTERN_DVBT_Locked_Task(void)1194 MS_BOOL INTERN_DVBT_Locked_Task(void)
1195 {
1196 INTERN_DVBT_Adaptive_TS_CLK();
1197
1198 //extension task
1199 {
1200 }
1201 return TRUE;
1202 }
1203
1204
1205
1206
INTERN_DVBT_Adaptive_TS_CLK(void)1207 MS_BOOL INTERN_DVBT_Adaptive_TS_CLK(void)
1208 {
1209 MS_U8 u8_ts_clk=0x00;
1210 MS_U8 TS_Clock_Temp;
1211 u8_ts_clk = HAL_DMD_RIU_ReadByte(MBRegBase+0x15);
1212 ULOGD("DEMOD","*************************************************************\n");
1213 ULOGD("DEMOD"," The TS clock: %x\n",u8_ts_clk);
1214
1215 //reg_atsc_dvb_div_reset =1
1216 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1217 TS_Clock_Temp=TS_Clock_Temp|0x01;
1218 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1219
1220 //set TS clock source div 5
1221 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1);
1222 TS_Clock_Temp=(TS_Clock_Temp&(~0x01));
1223 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp);
1224
1225 //set ts clk, REG_BASE[TOP_CKG_DVBTM_TS + 1] = TS_Clock_Set;
1226 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1227 TS_Clock_Temp=(TS_Clock_Temp&0xE0) |u8_ts_clk;
1228 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp);
1229
1230
1231 //reg_atsc_dvb_div_reset =0
1232 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1233 TS_Clock_Temp=(TS_Clock_Temp&0xFE);
1234 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1235
1236 // set ts FIFO
1237 // reg_RS_BACKEND
1238 // 0x16 *2 [15:8] reg_dvbt_ts_packet_storage_num=0x15 (extend FIFO)
1239 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ;
1240
1241 // enable ts
1242 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ;
1243 TS_Clock_Temp=TS_Clock_Temp|0x01;
1244 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ;
1245
1246 //debug: re-check ts clock
1247 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1248 TS_Clock_Temp=(TS_Clock_Temp&0x1F) ;
1249
1250 ULOGD("DEMOD","-------------------------------------------------------\n");
1251 ULOGD("DEMOD"," System report: %x\n",TS_Clock_Temp);
1252 ULOGD("DEMOD","*************************************************************\n");
1253
1254 return TRUE;
1255 }
1256
1257 #endif
1258 /************************************************************************************************
1259 Subject: Return lock status
1260 Function: INTERN_DVBT_Lock
1261 Parmeter: eStatus :
1262 Return: MS_BOOL
1263 Remark:
1264 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1265 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1266 {
1267 float fBER=0.0f;
1268
1269 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1270 {
1271 if (bFECLock == FALSE)
1272 {
1273 u32FecFirstLockTime = MsOS_GetSystemTime();
1274 ULOGD("DEMOD","++++++++[utopia]dvbt lock\n");
1275 }
1276
1277 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1278 {
1279 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1280 {
1281 if(fViterbiBerFiltered <= 0.0)
1282 fViterbiBerFiltered = fBER;
1283 else
1284 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1285 }
1286 ULOGD("DEMOD","[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered);
1287 }
1288 u32FecLastLockTime = MsOS_GetSystemTime();
1289 bFECLock = TRUE;
1290 return E_DMD_LOCK;
1291 }
1292 else
1293 {
1294 INTERN_DVBT_SignalQualityReset();
1295 if (bFECLock == TRUE)
1296 {
1297 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1298 {
1299 return E_DMD_LOCK;
1300 }
1301 }
1302 bFECLock = FALSE;
1303 }
1304
1305 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1306 {
1307 ULOGD("DEMOD","==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1308 return E_DMD_UNLOCK;
1309 }
1310
1311 if(!bTPSLock)
1312 {
1313 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1314 {
1315 ULOGD("DEMOD","==> INTERN_DVBT_Lock -- TPSLock \n");
1316 bTPSLock = TRUE;
1317 }
1318 }
1319 if(bTPSLock)
1320 {
1321 //ULOGD("DEMOD","TPSLock %ld\n",MsOS_GetSystemTime());
1322 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1323 {
1324 return E_DMD_CHECKING;
1325 }
1326 }
1327 else
1328 {
1329 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1330 {
1331 return E_DMD_CHECKING;
1332 }
1333 }
1334 return E_DMD_UNLOCK;
1335
1336 }
1337
1338
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1339 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1340 {
1341 MS_U16 u16Address = 0;
1342 MS_U8 cData = 0;
1343 MS_U8 cBitMask = 0;
1344 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1345 MS_U8 lock_to_unlock_flag=0;
1346 #endif
1347
1348 switch( eStatus )
1349 {
1350 case E_DMD_COFDM_FEC_LOCK:
1351 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1352 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1353 MDrv_SYS_DMD_VD_MBX_ReadReg(MBX_REG_BASE+0x16, &lock_to_unlock_flag);
1354 if (((cData == 0x0B) && (bFECLock == FALSE)) ||((cData == 0x0B) && ((lock_to_unlock_flag & 0x01)==0x01)) )
1355 {
1356 //ULOGD("DEMOD","Support adaptive TS CLK in polling mode! \n");
1357 INTERN_DVBT_Locked_Task();
1358 if((lock_to_unlock_flag & 0x01)==0x01)
1359 {
1360 MDrv_SYS_DMD_VD_MBX_WriteReg(MBX_REG_BASE+0x16,0x00);
1361 }
1362
1363 }
1364
1365 #endif
1366
1367 if (cData == 0x0B)
1368 {
1369 return TRUE;
1370 }
1371 else
1372 {
1373 return FALSE; // continuously un-lock
1374 }
1375 break;
1376
1377 case E_DMD_COFDM_PSYNC_LOCK:
1378 u16Address = 0x232C; //FEC: P-sync Lock,
1379 cBitMask = BIT(1);
1380 break;
1381
1382 case E_DMD_COFDM_TPS_LOCK:
1383 u16Address = 0x2222; //TPS HW Lock,
1384 cBitMask = BIT(1);
1385 break;
1386
1387 case E_DMD_COFDM_DCR_LOCK:
1388 u16Address = 0x2737; //DCR Lock,
1389 cBitMask = BIT(0);
1390 break;
1391
1392 case E_DMD_COFDM_AGC_LOCK:
1393 u16Address = 0x2829; //AGC Lock,
1394 cBitMask = BIT(0);
1395 break;
1396
1397 case E_DMD_COFDM_MODE_DET:
1398 u16Address = 0x24CF; //Mode CP Detect,
1399 cBitMask = BIT(4);
1400 break;
1401
1402 case E_DMD_COFDM_TPS_EVER_LOCK:
1403 u16Address = 0x20C0; //TPS Ever Lock,
1404 cBitMask = BIT(3);
1405 break;
1406
1407 case E_DMD_COFDM_NO_CHANNEL:
1408 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1409 cBitMask = BIT(7);
1410 break;
1411
1412 default:
1413 return FALSE;
1414 }
1415
1416 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1417 return FALSE;
1418
1419 if ((cData & cBitMask) == cBitMask)
1420 {
1421 return TRUE;
1422 }
1423
1424 return FALSE;
1425
1426 }
1427
1428 /****************************************************************************
1429 Subject: To get the Post viterbi BER
1430 Function: INTERN_DVBT_GetPostViterbiBer
1431 Parmeter: Quility
1432 Return: E_RESULT_SUCCESS
1433 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1434 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1435 We will not read the Period, and have the "/256/8"
1436 *****************************************************************************/
INTERN_DVBT_GetPostViterbiBer(float * ber)1437 MS_BOOL INTERN_DVBT_GetPostViterbiBer(float *ber)
1438 {
1439 MS_BOOL status = true;
1440 MS_U8 reg=0, reg_frz=0;
1441 MS_U16 BitErrPeriod;
1442 MS_U32 BitErr;
1443 MS_U16 PktErr;
1444
1445 /////////// Post-Viterbi BER /////////////
1446
1447 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1448 {
1449 *ber = (float)-1.0;
1450 return false;
1451 }
1452 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1453 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1454 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1455
1456 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1457 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1458 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1459 BitErrPeriod = reg;
1460
1461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1462 BitErrPeriod = (BitErrPeriod << 8)|reg;
1463
1464 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1465 // 0x6b [15:8] reg_bit_err_num_15_8
1466 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1467 // 0x6d [15:8] reg_bit_err_num_31_24
1468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1469 BitErr = reg;
1470
1471 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1472 BitErr = (BitErr << 8)|reg;
1473
1474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1475 BitErr = (BitErr << 8)|reg;
1476
1477 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1478 BitErr = (BitErr << 8)|reg;
1479
1480 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1481 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1482 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1483 PktErr = reg;
1484
1485 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1486 PktErr = (PktErr << 8)|reg;
1487
1488 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1489 reg_frz=reg_frz&(~0x03);
1490 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1491
1492 if (BitErrPeriod == 0 ) //protect 0
1493 BitErrPeriod = 1;
1494
1495 if (BitErr <=0 )
1496 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1497 else
1498 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1499
1500
1501 ULOGD("DEMOD","INTERN_DVBT PostVitBER = %8.3e \n ", *ber);
1502 ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr);
1503
1504 return status;
1505 }
1506
1507 /****************************************************************************
1508 Subject: To get the Pre viterbi BER
1509 Function: INTERN_DVBT_GetPreViterbiBer
1510 Parmeter: ber
1511 Return: E_RESULT_SUCCESS
1512 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1513 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1514 We will not read the Period, and have the "/256/8"
1515 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1516 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1517 {
1518 MS_U8 status = true;
1519 MS_U8 reg=0, reg_frz=0;
1520 MS_U16 BitErrPeriod;
1521 MS_U32 BitErr;
1522 MS_BOOL BEROver;
1523
1524 // bank 7 0x10 [3] reg_rd_freezeber
1525 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1526 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1527
1528 // bank 7 0x16 [7:0] reg_ber_timerl
1529 // [15:8] reg_ber_timerm
1530 // bank 7 0x18 [5:0] reg_ber_timerh
1531 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1532 BitErrPeriod = reg&0x3f;
1533
1534 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1535 BitErrPeriod = (BitErrPeriod << 8)|reg;
1536
1537 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1538 BitErrPeriod = (BitErrPeriod << 8)|reg;
1539
1540 // bank 7 0x1e [7:0] reg_ber_7_0
1541 // [15:8] reg_ber_15_8
1542 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1543 BitErr = reg;
1544
1545 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1546 BitErr = (BitErr << 8)|reg;
1547
1548 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1550 if (reg & 0x10)
1551 BEROver = true;
1552 else
1553 BEROver = false;
1554
1555 if (BitErrPeriod ==0 )//protect 0
1556 BitErrPeriod=1;
1557
1558 if (BEROver)
1559 {
1560 *ber = 1;
1561 ULOGD("DEMOD","BER is over\n");
1562 }
1563 else
1564 {
1565 if (BitErr <=0 )
1566 *ber=0.5 / (float)(BitErrPeriod * 256);
1567 else
1568 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1569 }
1570
1571 // bank 7 0x10 [3] reg_rd_freezeber
1572 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1573
1574 return status;
1575 }
1576
1577 /****************************************************************************
1578 Subject: To get the Packet error
1579 Function: INTERN_DVBT_GetPacketErr
1580 Parmeter: pktErr
1581 Return: E_RESULT_SUCCESS
1582 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1583 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1584 We will not read the Period, and have the "/256/8"
1585 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1586 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1587 {
1588 MS_BOOL status = true;
1589 MS_U8 reg = 0, reg_frz = 0;
1590 MS_U16 PktErr;
1591
1592 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1593 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1594 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1595
1596 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1597 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1598 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1599 PktErr = reg;
1600
1601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1602 PktErr = (PktErr << 8)|reg;
1603
1604 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1605 reg_frz=reg_frz&(~0x03);
1606 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1607
1608 ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr);
1609
1610 *u16PktErr = PktErr;
1611
1612 return status;
1613 }
1614
1615 /****************************************************************************
1616 Subject: To get the DVBT parameter
1617 Function: INTERN_DVBT_Get_TPS_Info
1618 Parmeter: point to return parameter
1619 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1620 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1621 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1622 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1623 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1624 FFT ( b14) : 0~1 => 2K, 8K
1625 Priority(bit 15) : 0~1=> HP,LP
1626 Return: TRUE
1627 FALSE
1628 Remark: The TPS parameters will be available after TPS lock
1629 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1630 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1631 {
1632 MS_U8 u8Temp;
1633
1634 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1635 return FALSE;
1636
1637 if ((u8Temp& 0x02) != 0x02)
1638 {
1639 return FALSE; //TPS unlock
1640 }
1641 else
1642 {
1643 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1644 return FALSE;
1645
1646 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1647 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1648
1649 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1650 return FALSE;
1651
1652 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1653 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1654
1655 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1656 return FALSE;
1657
1658 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
1659 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
1660
1661 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
1662 return FALSE;
1663
1664 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
1665
1666 }
1667 return TRUE;
1668 }
1669
1670
1671 /****************************************************************************
1672 Subject: Read the signal to noise ratio (SNR)
1673 Function: INTERN_DVBT_GetSNR
1674 Parmeter: None
1675 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1676 Remark:
1677 *****************************************************************************/
INTERN_DVBT_GetSNR(void)1678 float INTERN_DVBT_GetSNR (void)
1679 {
1680 MS_U8 status = true;
1681 MS_U8 reg=0, reg_frz=0;
1682 MS_U32 noise_power;
1683 float snr;
1684
1685 // bank 6 0xfe [0] reg_fdp_freeze
1686 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
1687 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
1688
1689 // bank 6 0xff [0] reg_fdp_load
1690 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1691
1692 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
1693 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
1694 noise_power = reg & 0x07;
1695
1696 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
1697 noise_power = (noise_power << 8)|reg;
1698
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
1700 noise_power = (noise_power << 8)|reg;
1701
1702 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
1703 noise_power = (noise_power << 8)|reg;
1704
1705 // bank 6 0x26 [5:4] reg_transmission_mode
1706 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
1707
1708 // bank 6 0xfe [0] reg_fdp_freeze
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
1710
1711 // bank 6 0xff [0] reg_fdp_load
1712 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1713
1714 #if 1 // copy from utopia2\mxlib\hal\miami\demod\halDMD_INTERN_DVBT.c
1715 noise_power = noise_power/2;
1716 noise_power /=1280;
1717 // noisepower = (rand()%256)*256;
1718 if (noise_power==0)//protect value 0
1719 noise_power=1;
1720
1721 #ifdef MSOS_TYPE_LINUX
1722 snr = 10*log10f((float)noise_power);
1723 #else
1724 snr = 10*Log10Approx((float)noise_power);
1725 #endif
1726
1727
1728 #else
1729 noise_power = noise_power/2;
1730
1731 if ((reg&0x30)==0x00) //2K
1732 {
1733 if (noise_power<1512)
1734 snr = 0;
1735 else
1736 #ifdef MSOS_TYPE_LINUX
1737 snr = 10*log10f((float)noise_power/1512);
1738 #else
1739 snr = 10*Log10Approx((float)noise_power/1512);
1740 #endif
1741 }
1742 //else if ((reg&0x30)==0x10)//8K
1743 else
1744 {
1745 if (noise_power<6048)
1746 snr = 0;
1747 else
1748 #ifdef MSOS_TYPE_LINUX
1749 snr = 10*log10f((float)noise_power/6048);
1750 #else
1751 snr = 10*Log10Approx((float)noise_power/6048);
1752 #endif
1753 }
1754 /* ignore 4K
1755 else //4K
1756 {
1757 if (noise_power<3024)
1758 snr = 0;
1759 else
1760 snr = 10*Log10Approx(noise_power/3024);
1761 }
1762 */
1763 #endif
1764
1765 if (status == true)
1766 return snr;
1767 else
1768 return -1;
1769
1770 }
1771
1772 /****************************************************************************
1773 Subject: To check if Hierarchy on
1774 Function: INTERN_DVBT_Is_HierarchyOn
1775 Parmeter:
1776 Return: BOOLEAN
1777 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)1778 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
1779 {
1780 MS_U16 u16_tmp;
1781
1782 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
1783 return FALSE;
1784 //ULOGD("DEMOD","u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
1785 if(u16_tmp&0x38)
1786 {
1787 return TRUE;
1788 }
1789 return FALSE;
1790 }
1791
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1792 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1793 {
1794 MS_U8 status = true;
1795 float ch_power_db = 0.0f;
1796 float ch_power_ref = 11.0f;
1797 float ch_power_rel = 0.0f;
1798 MS_U8 u8_index = 0;
1799 MS_U16 tps_info_qam,tps_info_cr;
1800
1801 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1802 {
1803 *strength = 0;
1804 return TRUE;
1805 }
1806 //ULOGD("DEMOD","INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime());
1807
1808 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
1809 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
1810 /* Actually, it's more reasonable, that signal level depended on cable input power level
1811 * thougth the signal isn't dvb-t signal.
1812 */
1813
1814 // use pointer of IFAGC table to identify
1815 // case 1: RFAGC from SAR, IFAGC controlled by demod
1816 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1817 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1818 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
1819 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1820 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1821 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
1822 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
1823
1824
1825 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
1826 ULOGD("DEMOD","[dvbt]TPS qam parameter retrieve failure\n");
1827
1828 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
1829 ULOGD("DEMOD","[dvbt]TPS cr parameter retrieve failure\n");
1830
1831
1832 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
1833 {
1834 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
1835 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
1836 {
1837 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
1838 break;
1839 }
1840 else
1841 {
1842 u8_index++;
1843 }
1844 }
1845
1846 if (ch_power_ref > 10.0f)
1847 *strength = 0;
1848 else
1849 {
1850 ch_power_rel = ch_power_db - ch_power_ref;
1851
1852 if ( ch_power_rel < -15.0f )
1853 {
1854 *strength = 0;
1855 }
1856 else if ( ch_power_rel < 0.0f )
1857 {
1858 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
1859 }
1860 else if ( ch_power_rel < 20 )
1861 {
1862 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
1863 }
1864 else if ( ch_power_rel < 35.0f )
1865 {
1866 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
1867 }
1868 else
1869 {
1870 *strength = 100;
1871 }
1872 }
1873
1874 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1875 {
1876 *strength = 0;
1877 return TRUE;
1878 }
1879
1880 ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength);
1881 ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength);
1882
1883 return status;
1884 }
1885
1886 /****************************************************************************
1887 Subject: To get the DVT Signal quility
1888 Function: INTERN_DVBT_GetSignalQuality
1889 Parmeter: Quility
1890 Return: E_RESULT_SUCCESS
1891 E_RESULT_FAILURE
1892 Remark: Here we have 4 level range
1893 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1894 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1895 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1896 <4>.4th Range => Quality <10
1897 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1898 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1899 {
1900 float ber_sqi;
1901 float fber;
1902 float cn_rec = 0;
1903 float cn_nordig_p1 = 0;
1904 float cn_rel = 0;
1905
1906 MS_U8 status = true;
1907 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
1908 MS_U16 u16_tmp;
1909
1910 //ULOGD("DEMOD","INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime());
1911
1912 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
1913 {
1914
1915 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1916 {
1917 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
1918 }
1919 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
1920 if(fViterbiBerFiltered<= 0.0)
1921 {
1922 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
1923 {
1924 ULOGD("DEMOD","GetPostViterbiBer Fail!\n");
1925 return FALSE;
1926 }
1927 fViterbiBerFiltered = fber;
1928 }
1929 else
1930 {
1931 fber = fViterbiBerFiltered;
1932 }
1933
1934 if (fber > 1.0E-3)
1935 ber_sqi = 0.0;
1936 else if (fber > 8.5E-7)
1937 #ifdef MSOS_TYPE_LINUX
1938 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
1939 #else
1940 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
1941 #endif
1942 else
1943 ber_sqi = 100.0;
1944
1945 cn_rec = INTERN_DVBT_GetSNR();
1946
1947 if (cn_rec == -1) //get SNR return fail
1948 status = false;
1949
1950 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
1951 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
1952 tps_cnstl = 0xff;
1953 tps_cr = 0xff;
1954 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
1955 tps_cnstl = (MS_U8)u16_tmp&0x07;
1956 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
1957 tps_cr = (MS_U8)u16_tmp&0x07;
1958
1959 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
1960 {
1961 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
1962 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
1963 {
1964 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
1965 break;
1966 }
1967 }
1968
1969 // 0,5, snr offset
1970 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
1971
1972 // patch....
1973 // Noridg SQI,
1974 // 64QAM, CR34, GI14, SNR 22dB.
1975 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
1976 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
1977 {
1978 cn_rel += 1.5f;
1979 }
1980
1981 if (cn_rel < -7.0f)
1982 {
1983 *quality = 0;
1984 }
1985 else if (cn_rel < 3.0)
1986 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
1987 else
1988 *quality = (MS_U16)ber_sqi;
1989 }
1990 else
1991 {
1992 *quality = 0;
1993 }
1994
1995 ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr);
1996 ULOGD("DEMOD","BER = %8.3e\n", fber);
1997 ULOGD("DEMOD","Signal Quility = %d\n", *quality);
1998 return status;
1999 }
2000
2001 /****************************************************************************
2002 Subject: To get the Cell ID
2003 Function: INTERN_DVBT_Get_CELL_ID
2004 Parmeter: point to return parameter cell_id
2005
2006 Return: TRUE
2007 FALSE
2008 Remark:
2009 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2010 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2011 {
2012 MS_U8 status = true;
2013 MS_U8 value1=0;
2014 MS_U8 value2=0;
2015
2016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2017 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2018
2019 *cell_id = ((MS_U16)value1<<8)|value2;
2020 return status;
2021 }
2022 /*
2023 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2024 {
2025 #define SQI_LOOP_NUM 50
2026 U8 inn = 0;
2027 WORD sqi = 0;
2028 WORD ave_sqi = 0;
2029 WORD ave_num = 0;
2030 while(inn++<SQI_LOOP_NUM)
2031 {
2032 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2033 {
2034 ULOGD("DEMOD","[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2035 ave_sqi+=sqi;
2036 ave_num++;
2037 }
2038 MsOS_DelayTask(50);
2039 }
2040
2041 if(ave_num != 0 )
2042 *quality = ave_sqi/ave_num;
2043
2044 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2045 }
2046 */
2047 /****************************************************************************
2048 Subject: To get the DVBT Carrier Freq Offset
2049 Function: INTERN_DVBT_Get_FreqOffset
2050 Parmeter: Frequency offset (in KHz), bandwidth
2051 Return: E_RESULT_SUCCESS
2052 E_RESULT_FAILURE
2053 Remark:
2054 *****************************************************************************/
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2055 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2056 {
2057 float N, FreqB;
2058 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2059 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2060 MS_U8 reg_frz=0, reg=0;
2061 MS_U8 status;
2062
2063 FreqB = (float)u8BW * 8 / 7;
2064
2065 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2066
2067 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2068
2069 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2070 RegCfoTd = reg;
2071
2072 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2073 RegCfoTd = (RegCfoTd << 8)|reg;
2074
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2076 RegCfoTd = (RegCfoTd << 8)|reg;
2077
2078 FreqCfoTd = (float)RegCfoTd;
2079
2080 if (RegCfoTd & 0x800000)
2081 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2082
2083 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2084
2085 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2086
2087 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2088 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2089
2090 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2091
2092 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2093 RegCfoFd = reg;
2094
2095 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2096 RegCfoFd = (RegCfoFd << 8)|reg;
2097
2098 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2099 RegCfoFd = (RegCfoFd << 8)|reg;
2100
2101 FreqCfoFd = (float)RegCfoFd;
2102
2103 if (RegCfoFd & 0x800000)
2104 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2105
2106 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2107
2108 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2109 RegIcfo = reg & 0x07;
2110
2111 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2112 RegIcfo = (RegIcfo << 8)|reg;
2113
2114 FreqIcfo = (float)RegIcfo;
2115
2116 if (RegIcfo & 0x400)
2117 FreqIcfo = FreqIcfo - (float)0x800;
2118
2119 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2120 reg = reg & 0x30;
2121
2122 switch (reg)
2123 {
2124 case 0x00: N = 2048; break;
2125 case 0x20: N = 4096; break;
2126 case 0x10:
2127 default: N = 8192; break;
2128 }
2129
2130 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2131 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2132 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2133 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2134 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2135 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2136 // DBG_GET_SIGNAL(ULOGD("DEMOD","FCFO = %f\n", FreqCfoFd));
2137 // DBG_GET_SIGNAL(ULOGD("DEMOD","TCFO = %f\n", FreqCfoTd));
2138 // DBG_GET_SIGNAL(ULOGD("DEMOD","ICFO = %f\n", FreqIcfo));
2139 ULOGD("DEMOD","CFOE = %f\n", *pFreqOff);
2140
2141 if (status == TRUE)
2142 return TRUE;
2143 else
2144 return FALSE;
2145 }
2146
2147
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2148 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2149 {
2150
2151 bPowerOn = bPowerOn;
2152 }
2153
INTERN_DVBT_Power_Save(void)2154 MS_BOOL INTERN_DVBT_Power_Save(void)
2155 {
2156
2157 return TRUE;
2158 }
2159
2160 /****************************************************************************
2161 Subject: To get the DVBT constellation parameter
2162 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2163 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2164 Return: TRUE
2165 FALSE
2166 Remark: The TPS parameters will be available after TPS lock
2167 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2168 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2169 {
2170 MS_U8 tps_param;
2171
2172 //@@++ Arki 20100125
2173 if (eSignalType == TS_MODUL_MODE)
2174 {
2175 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2176 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2177 }
2178
2179 if (eSignalType == TS_CODE_RATE)
2180 {
2181 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2182 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2183 }
2184
2185 if (eSignalType == TS_GUARD_INTERVAL)
2186 {
2187 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2188 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2189 }
2190
2191 if (eSignalType == TS_FFX_VALUE)
2192 {
2193 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2194 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2195 }
2196 //@@-- Arki 20100125
2197 return TRUE;
2198 }
2199
INTERN_DVBT_Version(MS_U16 * ver)2200 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2201 {
2202
2203 MS_U8 status = true;
2204 MS_U8 tmp = 0;
2205 MS_U16 u16_INTERN_DVBT_Version;
2206
2207 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2208 u16_INTERN_DVBT_Version = tmp;
2209 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2210 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2211 *ver = u16_INTERN_DVBT_Version;
2212
2213 return status;
2214 }
2215
INTERN_DVBT_Version_minor(MS_U8 * ver2)2216 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2217 {
2218
2219 MS_U8 status = true;
2220
2221 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2222
2223 return status;
2224 }
2225
2226
INTERN_DVBT_Show_Demod_Version(void)2227 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2228 {
2229
2230 MS_BOOL status = true;
2231 MS_U16 u16_INTERN_DVBT_Version;
2232 MS_U8 u8_minor_ver = 0;
2233
2234 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2235 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2236 ULOGD("DEMOD","[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2237
2238 return status;
2239 }
2240
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2241 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2242 {
2243 MS_U8 u8_index = 0;
2244 MS_BOOL bRet = false;
2245
2246 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2247 {
2248 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2249 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2250 {
2251 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2252 bRet = true;
2253 break;
2254 }
2255 else
2256 {
2257 u8_index++;
2258 }
2259 }
2260 return bRet;
2261 }
2262
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2263 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2264 {
2265 MS_U8 u8_index = 0;
2266 MS_BOOL bRet = false;
2267
2268 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2269 {
2270 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2271 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2272 {
2273 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2274 bRet = true;
2275 break;
2276 }
2277 else
2278 {
2279 u8_index++;
2280 }
2281 }
2282 return bRet;
2283 }
2284
2285
2286 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2287 void INTERN_DVBT_get_demod_state(MS_U8* state)
2288 {
2289 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2290 return;
2291 }
2292
INTERN_DVBT_Show_ChannelLength(void)2293 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2294 {
2295 MS_U8 status = true;
2296 MS_U8 tmp = 0;
2297 MS_U16 len = 0;
2298 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2299 len = tmp;
2300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2301 len = (len<<8)|tmp;
2302 ULOGD("DEMOD","[dvbt]Hw_channel=%d\n",len);
2303 return status;
2304 }
2305
INTERN_DVBT_Show_SW_ChannelLength(void)2306 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2307 {
2308 MS_U8 status = true;
2309 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2310 MS_U16 sw_len = 0;
2311 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2312 sw_len = tmp;
2313 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2314 sw_len = (sw_len<<8)|tmp;
2315 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2316 peak_num = tmp;
2317 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2318 insideGI = tmp&0x01;
2319 stoptracking = (tmp&0x02)>>1;
2320 flag_short_echo = (tmp&0x0C)>>2;
2321 fsa_mode = (tmp&0x30)>>4;
2322
2323 ULOGD("DEMOD","[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2324 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2325
2326 return status;
2327 }
2328
INTERN_DVBT_Show_ACI_CI(void)2329 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2330 {
2331
2332 #define BIT4 0x10
2333 MS_U8 status = true;
2334 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2335
2336 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2337 digACI = (tmp&BIT4)>>4;
2338
2339 // get flag_CI
2340 // 0: No interference
2341 // 1: CCI
2342 // 2: in-band ACI
2343 // 3: N+1 ACI
2344 // flag_ci = (tmp&0xc0)>>6;
2345 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2346 flag_CI = (tmp&0xC0)>>6;
2347 td_coef = (tmp&0x0C)>>2;
2348
2349 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2350
2351 ULOGD("DEMOD","[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2352
2353 return status;
2354 }
2355
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2356 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2357 {
2358 MS_U8 status = true;
2359 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2360 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2361 fd = tmp;
2362 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2363 ch_len = tmp;
2364 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2365 snr_sel = (tmp>>4)&0x03;
2366 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2367 pertone_num = tmp;
2368
2369 ULOGD("DEMOD","[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2370
2371 return status;
2372 }
2373
INTERN_DVBT_Get_CFO(void)2374 MS_BOOL INTERN_DVBT_Get_CFO(void)
2375 {
2376
2377 float N = 0, FreqB = 0;
2378 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2379 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2380 MS_U8 reg_frz = 0, reg = 0;
2381 MS_U8 status = 0;
2382 MS_U8 u8BW = 8;
2383
2384 FreqB = (float)u8BW * 8 / 7;
2385
2386 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2387
2388 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2389
2390 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2391 RegCfoTd = reg;
2392
2393 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2394 RegCfoTd = (RegCfoTd << 8)|reg;
2395
2396 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2397 RegCfoTd = (RegCfoTd << 8)|reg;
2398
2399 FreqCfoTd = (float)RegCfoTd;
2400
2401 if (RegCfoTd & 0x800000)
2402 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2403
2404 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2405
2406 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2407
2408 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2409 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2410
2411 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2412
2413 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2414 RegCfoFd = reg;
2415
2416 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2417 RegCfoFd = (RegCfoFd << 8)|reg;
2418
2419 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2420 RegCfoFd = (RegCfoFd << 8)|reg;
2421
2422 FreqCfoFd = (float)RegCfoFd;
2423
2424 if (RegCfoFd & 0x800000)
2425 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2426
2427 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2428
2429 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2430 RegIcfo = reg & 0x07;
2431
2432 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2433 RegIcfo = (RegIcfo << 8)|reg;
2434
2435 FreqIcfo = (float)RegIcfo;
2436
2437 if (RegIcfo & 0x400)
2438 FreqIcfo = FreqIcfo - (float)0x800;
2439
2440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2441 reg = reg & 0x30;
2442
2443 switch (reg)
2444 {
2445 case 0x00: N = 2048; break;
2446 case 0x20: N = 4096; break;
2447 case 0x10:
2448 default: N = 8192; break;
2449 }
2450
2451 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2452 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2453 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2454 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2455 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2456
2457 ULOGD("DEMOD","[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2458
2459 return status;
2460
2461 }
INTERN_DVBT_Get_SFO(void)2462 MS_BOOL INTERN_DVBT_Get_SFO(void)
2463 {
2464 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2465 MS_BOOL status = true;
2466 MS_U8 reg = 0;
2467 float FreqB = 9.143, FreqS = 45.473; //20.48
2468 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2469 float sfo_value = 0;
2470
2471 // get Reg_TDP_SFO,
2472 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2473 Reg_TDP_SFO = reg;
2474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2475 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2476 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2477 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2478
2479 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2480
2481 // get Reg_FDP_SFO,
2482 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2483 Reg_FDP_SFO = reg;
2484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2485 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2486 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2487 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2488
2489 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2490
2491 // get Reg_FSA_SFO,
2492 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2493 Reg_FSA_SFO = reg;
2494 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2495 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2496 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2497 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2498
2499 // get Reg_FSA_IN,
2500 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2501 Reg_FSA_IN = reg;
2502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2503 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2504 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2505
2506 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2507 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2508
2509 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2510 // ULOGD("DEMOD","\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2511 ULOGD("DEMOD","[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2512
2513
2514 return status;
2515 }
2516
INTERN_DVBT_Get_SYA_status(void)2517 void INTERN_DVBT_Get_SYA_status(void)
2518 {
2519 MS_U8 status = true;
2520 MS_U8 sya_k = 0,reg = 0;
2521 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2522
2523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2524 sya_k = reg;
2525
2526 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2527 sya_th = reg;
2528 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2529 sya_th = (sya_th<<8)|reg;
2530
2531 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2532 sya_offset = reg;
2533 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2534 sya_offset = (sya_offset<<8)|reg;
2535
2536 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2537 len_m = reg;
2538 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2539 len_m = (len_m<<8)|reg;
2540
2541 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2542 len_b = reg;
2543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2544 len_b = (len_b<<8)|reg;
2545
2546
2547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2548 len_a = reg;
2549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2550 len_a = (len_a<<8)|reg;
2551
2552
2553 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2554 tracking_reg = reg;
2555
2556
2557 ULOGD("DEMOD","[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2558 ULOGD("DEMOD","[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2559
2560 return;
2561 }
2562
INTERN_DVBT_Get_cci_status(void)2563 void INTERN_DVBT_Get_cci_status(void)
2564 {
2565 MS_U8 status = true;
2566 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2567
2568 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2569 cci_fsweep = reg;
2570
2571 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2572 cci_kp = reg;
2573
2574 ULOGD("DEMOD","[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2575
2576 return;
2577 }
2578
INTERN_DVBT_Show_PRESFO_Info(void)2579 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2580 {
2581 MS_U8 tmp = 0;
2582 MS_BOOL status = TRUE;
2583 ULOGD("DEMOD","\n[SFO]");
2584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2585 ULOGD("DEMOD","[%x]",tmp);
2586 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2587 ULOGD("DEMOD","[%x]",tmp);
2588 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2589 ULOGD("DEMOD","[%x]",tmp);
2590 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2591 ULOGD("DEMOD","[%x]",tmp);
2592 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2593 ULOGD("DEMOD","[%x]",tmp);
2594 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2595 ULOGD("DEMOD","[%x]",tmp);
2596 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2597 ULOGD("DEMOD","[%x]",tmp);
2598 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2599 ULOGD("DEMOD","[%x][End]",tmp);
2600
2601 return status;
2602 }
2603
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2604 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2605 {
2606 MS_BOOL status = true;
2607
2608 *locktime = 0xffff;
2609 ULOGD("DEMOD","[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2610
2611 status = false;
2612 return status;
2613 }
2614
2615
INTERN_DVBT_Show_Lock_Time_Info(void)2616 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2617 {
2618 MS_U16 locktime = 0;
2619 MS_BOOL status = TRUE;
2620 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2621 ULOGD("DEMOD","[DVBT]lock_time = %d ms\n",locktime);
2622 return status;
2623 }
2624
INTERN_DVBT_Show_BER_Info(void)2625 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2626 {
2627 MS_U8 tmp = 0;
2628 MS_BOOL status = TRUE;
2629 ULOGD("DEMOD","\n[BER]");
2630 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2631 ULOGD("DEMOD","[%x,",tmp);
2632 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2633 ULOGD("DEMOD","%x]",tmp);
2634 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2635 ULOGD("DEMOD","[%x,",tmp);
2636 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2637 ULOGD("DEMOD","%x]",tmp);
2638 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2639 ULOGD("DEMOD","[%x,",tmp);
2640 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2641 ULOGD("DEMOD","%x][End]",tmp);
2642
2643 return status;
2644
2645 }
2646
2647
INTERN_DVBT_Show_AGC_Info(void)2648 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2649 {
2650 MS_U8 tmp = 0;
2651 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2652 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2653 MS_U16 if_agc_err = 0;
2654 MS_BOOL status = TRUE;
2655 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2656
2657 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2658 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2661 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2663
2664
2665 // select IF gain to read
2666 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2667 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2668
2669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2670 if_agc_gain = tmp;
2671 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2672 if_agc_gain = (if_agc_gain<<8)|tmp;
2673
2674
2675 // select d1 gain to read.
2676 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
2677 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
2678
2679 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
2680 d1_gain = tmp;
2681 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
2682 d1_gain = (d1_gain<<8)|tmp;
2683
2684 // select d2 gain to read.
2685 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
2686 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
2687
2688 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
2689 d2_gain = tmp;
2690 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
2691 d2_gain = (d2_gain<<8)|tmp;
2692
2693 // select IF gain err to read
2694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2695 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
2696
2697 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2698 if_agc_err = tmp;
2699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2700 if_agc_err = (if_agc_err<<8)|tmp;
2701
2702 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
2703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
2704 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
2705
2706
2707
2708 ULOGD("DEMOD","[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2709 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2710
2711 ULOGD("DEMOD","[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2712 ULOGD("DEMOD","[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
2713
2714 return status;
2715
2716 }
2717
INTERN_DVBT_Show_WIN_Info(void)2718 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
2719 {
2720 MS_U8 tmp = 0;
2721 MS_U8 trigger = 0;
2722 MS_U16 win_len = 0;
2723
2724 MS_BOOL status = TRUE;
2725
2726 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
2727 win_len = tmp;
2728 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
2729 win_len = (win_len<<8)|tmp;
2730
2731 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
2732
2733 ULOGD("DEMOD","[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
2734
2735 return status;
2736 }
2737
INTERN_DVBT_Show_td_coeff(void)2738 void INTERN_DVBT_Show_td_coeff(void)
2739 {
2740 MS_U8 status = true;
2741 MS_U8 w1 = 0,w2 = 0,reg = 0;
2742
2743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
2744 w1 = reg;
2745
2746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
2747 w2 = reg;
2748
2749 ULOGD("DEMOD","[td]w1=0x%x, w2=0x%x\n",w1,w2);
2750
2751 return;
2752 }
2753
2754 /********************************************************
2755 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
2756 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
2757 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2758 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2759 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
2760 * FFT ( b14) : 0~1 => 2K, 8K
2761 ********************************/
INTERN_DVBT_Show_Modulation_info(void)2762 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
2763 {
2764 MS_U16 tps_info;
2765
2766 // ULOGD("DEMOD","[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
2767
2768 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
2769 {
2770 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
2771 MS_U8 constel = tps_info&0x0007;
2772 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
2773 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
2774 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
2775 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
2776
2777 ULOGD("DEMOD","tps=0x%x ",tps_info);
2778
2779 switch(fft)
2780 {
2781 case 0:
2782 ULOGD("DEMOD","mode = 2K,");
2783 break;
2784 case 1:
2785 ULOGD("DEMOD","mode = 8K,");
2786 break;
2787 default:
2788 ULOGD("DEMOD","mode = unknow,");
2789 break;
2790 }
2791 switch(constel)
2792 {
2793 case 0:
2794 ULOGD("DEMOD"," QPSK, ");
2795 break;
2796 case 1:
2797 ULOGD("DEMOD","16QAM, ");
2798 break;
2799 case 2:
2800 ULOGD("DEMOD","64QAM, ");
2801 break;
2802 default:
2803 ULOGD("DEMOD","unknow QAM, ");
2804 break;
2805 }
2806 switch(gi)
2807 {
2808 case 0:
2809 ULOGD("DEMOD","GI=1/32, ");
2810 break;
2811 case 1:
2812 ULOGD("DEMOD","GI=1/16, ");
2813 break;
2814 case 2:
2815 ULOGD("DEMOD","GI= 1/8, ");
2816 break;
2817 case 3:
2818 ULOGD("DEMOD","GI= 1/4, ");
2819 break;
2820 default:
2821 ULOGD("DEMOD","unknow GI, ");
2822 break;
2823 }
2824
2825 switch(hp_cr)
2826 {
2827 case 0:
2828 ULOGD("DEMOD","HP_CR=1/2, ");
2829 break;
2830 case 1:
2831 ULOGD("DEMOD","HP_CR=2/3, ");
2832 break;
2833 case 2:
2834 ULOGD("DEMOD","HP_CR=3/4, ");
2835 break;
2836 case 3:
2837 ULOGD("DEMOD","HP_CR=5/6, ");
2838 break;
2839 case 4:
2840 ULOGD("DEMOD","HP_CR=7/8, ");
2841 break;
2842 default:
2843 ULOGD("DEMOD","unknow hp_cr, ");
2844 break;
2845 }
2846
2847 switch(lp_cr)
2848 {
2849 case 0:
2850 ULOGD("DEMOD","LP_CR=1/2, ");
2851 break;
2852 case 1:
2853 ULOGD("DEMOD","LP_CR=2/3, ");
2854 break;
2855 case 2:
2856 ULOGD("DEMOD","LP_CR=3/4, ");
2857 break;
2858 case 3:
2859 ULOGD("DEMOD","LP_CR=5/6, ");
2860 break;
2861 case 4:
2862 ULOGD("DEMOD","LP_CR=7/8, ");
2863 break;
2864 default:
2865 ULOGD("DEMOD","unknow lp_cr, ");
2866 break;
2867 }
2868
2869 ULOGD("DEMOD"," Hiearchy=0x%x\n",hiearchy);
2870
2871 // ULOGD("DEMOD","\n");
2872 return TRUE;
2873 }
2874 else
2875 {
2876 ULOGD("DEMOD","INVALID\n");
2877 return FALSE;
2878 }
2879 }
2880
2881
2882
2883
INTERN_DVBT_Show_BER_PacketErr(void)2884 void INTERN_DVBT_Show_BER_PacketErr(void)
2885 {
2886 float f_ber = 0;
2887 MS_U16 packetErr = 0;
2888 INTERN_DVBT_GetPostViterbiBer(&f_ber);
2889 INTERN_DVBT_GetPacketErr(&packetErr);
2890
2891 ULOGD("DEMOD","[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
2892 return;
2893 }
2894
INTERN_DVBT_Show_Lock_Info(void)2895 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
2896 {
2897
2898 ULOGD("DEMOD","[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
2899 return false;
2900 }
2901
2902
INTERN_DVBT_Show_Demod_Info(void)2903 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
2904 {
2905 MS_U8 demod_state = 0;
2906 MS_BOOL status = true;
2907 static MS_U8 counter = 0;
2908
2909 INTERN_DVBT_get_demod_state(&demod_state);
2910
2911 ULOGD("DEMOD","==========[dvbt]state=%d\n",demod_state);
2912 if (demod_state < 5)
2913 {
2914 INTERN_DVBT_Show_Demod_Version();
2915 INTERN_DVBT_Show_AGC_Info();
2916 INTERN_DVBT_Show_ACI_CI();
2917 }
2918 else if(demod_state < 8)
2919 {
2920 INTERN_DVBT_Show_Demod_Version();
2921 INTERN_DVBT_Show_AGC_Info();
2922 INTERN_DVBT_Show_ACI_CI();
2923 INTERN_DVBT_Show_ChannelLength();
2924 INTERN_DVBT_Get_CFO();
2925 INTERN_DVBT_Get_SFO();
2926 INTERN_DVBT_Show_td_coeff();
2927 }
2928 else if(demod_state < 11)
2929 {
2930 INTERN_DVBT_Show_Demod_Version();
2931 INTERN_DVBT_Show_AGC_Info();
2932 INTERN_DVBT_Show_ACI_CI();
2933 INTERN_DVBT_Show_ChannelLength();
2934 INTERN_DVBT_Get_CFO();
2935 INTERN_DVBT_Get_SFO();
2936 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
2937 INTERN_DVBT_Get_SYA_status();
2938 INTERN_DVBT_Show_td_coeff();
2939 }
2940 else if((demod_state == 11) && ((counter%4) == 0))
2941 {
2942 INTERN_DVBT_Show_Demod_Version();
2943 INTERN_DVBT_Show_AGC_Info();
2944 INTERN_DVBT_Show_ACI_CI();
2945 INTERN_DVBT_Show_ChannelLength();
2946 INTERN_DVBT_Get_CFO();
2947 INTERN_DVBT_Get_SFO();
2948 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
2949 INTERN_DVBT_Get_SYA_status();
2950 INTERN_DVBT_Show_td_coeff();
2951 INTERN_DVBT_Show_Modulation_info();
2952 INTERN_DVBT_Show_BER_PacketErr();
2953 }
2954 else
2955 status = false;
2956
2957 ULOGD("DEMOD","===========================\n");
2958 counter++;
2959
2960 return status;
2961 }
2962 #endif
2963
2964