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Searched refs:EQE_REG_BASE (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBC.c134 #define EQE_REG_BASE 0x3900UL macro
1934 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x20); in INTERN_DVBC_GetSNR()
1937 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45, &u8Data); in INTERN_DVBC_GetSNR()
1939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44, &u8Data); in INTERN_DVBC_GetSNR()
1943 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x00); in INTERN_DVBC_GetSNR()
1947 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1948 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1958 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
2265 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x20); in INTERN_DVBC_Get_FreqOffset()
2268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &reg); in INTERN_DVBC_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBC.c134 #define EQE_REG_BASE 0x2B00 macro
1927 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x20); in INTERN_DVBC_GetSNR()
1930 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45, &u8Data); in INTERN_DVBC_GetSNR()
1932 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44, &u8Data); in INTERN_DVBC_GetSNR()
1936 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x00); in INTERN_DVBC_GetSNR()
2244 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x20); in INTERN_DVBC_Get_FreqOffset()
2247 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &reg); in INTERN_DVBC_Get_FreqOffset()
2249 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &reg); in INTERN_DVBC_Get_FreqOffset()
2251 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &reg); in INTERN_DVBC_Get_FreqOffset()
2253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &reg); in INTERN_DVBC_Get_FreqOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBC.c134 #define EQE_REG_BASE 0x2B00 macro
1953 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x20); in INTERN_DVBC_GetSNR()
1956 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45, &u8Data); in INTERN_DVBC_GetSNR()
1958 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44, &u8Data); in INTERN_DVBC_GetSNR()
1962 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x00); in INTERN_DVBC_GetSNR()
2269 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x20); in INTERN_DVBC_Get_FreqOffset()
2272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &reg); in INTERN_DVBC_Get_FreqOffset()
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &reg); in INTERN_DVBC_Get_FreqOffset()
2276 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &reg); in INTERN_DVBC_Get_FreqOffset()
2278 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &reg); in INTERN_DVBC_Get_FreqOffset()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00 macro
1543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1880 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1893 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2236 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2238 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2240 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00 macro
1543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1880 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1893 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2236 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2238 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2240 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00 macro
1593 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1594 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1606 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1929 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1930 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1943 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2286 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2288 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2290 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00 macro
1543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1880 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1893 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2236 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2238 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2240 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00 macro
1593 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1594 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1606 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1929 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1930 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1943 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2286 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2288 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2290 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00 macro
1543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1880 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1893 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2236 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2238 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2240 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00 macro
1543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1880 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1893 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2236 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2238 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2240 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBC.c134 #define EQE_REG_BASE 0x2c00UL // P2= 1; 0x11c00 -> 0x1c00 macro
1489 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1490 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1500 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1807 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1808 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1821 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2152 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2154 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2156 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBC.c136 #define EQE_REG_BASE 0x2c00UL macro
1949 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1950 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1962 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
2286 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
2287 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
2300 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2633 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2635 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2637 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBC.c133 #define EQE_REG_BASE 0x2c00 macro
1687 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1688 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1698 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
2005 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
2006 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
2019 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2346 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2348 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2350 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBC.c133 #define EQE_REG_BASE 0x2c00UL // P2= 1; 0x11c00 -> 0x1c00 macro
1493 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_GetSNR()
1494 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_GetSNR()
1504 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_GetSNR()
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, &reg_frz); in INTERN_DVBC_Get_FreqOffset()
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01); in INTERN_DVBC_Get_FreqOffset()
1825 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz); in INTERN_DVBC_Get_FreqOffset()
2156 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp); in INTERN_DVBC_info()
2158 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp); in INTERN_DVBC_info()
2160 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBC.c139 #define EQE_REG_BASE 0x2700UL // P2 = 1, 0x11a00 -> 0x1a00 macro
2961 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a+BANK_BASE_OFFSET*hal_demod_swtich_status… in INTERN_DVBC_GetSNR()
2964 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45+BANK_BASE_OFFSET*hal_demod_swtich_status… in INTERN_DVBC_GetSNR()
2966 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44+BANK_BASE_OFFSET*hal_demod_swtich_status… in INTERN_DVBC_GetSNR()
2969 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a+BANK_BASE_OFFSET*hal_demod_swtich_status… in INTERN_DVBC_GetSNR()
3338 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d+BANK_BASE_OFFSET*hal_demod_swtich_status, … in INTERN_DVBC_Get_FreqOffset()
3339 …status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d+BANK_BASE_OFFSET*hal_demod_swtich_status,… in INTERN_DVBC_Get_FreqOffset()
3352 …status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d+BANK_BASE_OFFSET*hal_demod_swtich_status,… in INTERN_DVBC_Get_FreqOffset()
3737 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp); in INTERN_DVBC_info()
3739 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp); in INTERN_DVBC_info()
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/utopia/UTPA2-700.0.x/modules/demodulator/drv/dvb_extdemod/
H A DdrvDMD_EXTERN_MSB201X.c163 #define EQE_REG_BASE 0x2A00 macro
2707 status &= _MDrv_DMD_MSB201X_SetReg(devID, EQE_REG_BASE + 0x3a, 0x20); in _MDrv_DMD_MSB201X_GetSNR()
2710 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x45, &u8Data); in _MDrv_DMD_MSB201X_GetSNR()
2712 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x44, &u8Data); in _MDrv_DMD_MSB201X_GetSNR()
2716 status &= _MDrv_DMD_MSB201X_SetReg(devID, EQE_REG_BASE + 0x3a, 0x00); in _MDrv_DMD_MSB201X_GetSNR()
4083 _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x02, &u8Data); in _MDrv_DMD_MSB201X_GetCurrentModulationType()
4158 status &= _MDrv_DMD_MSB201X_SetReg(devID, EQE_REG_BASE + 0x3A, 0x20); in _MDrv_DMD_MSB201X_Get_FreqOffset()
4161 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x43, &reg); in _MDrv_DMD_MSB201X_Get_FreqOffset()
4163 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x42, &reg); in _MDrv_DMD_MSB201X_Get_FreqOffset()
4165 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x41, &reg); in _MDrv_DMD_MSB201X_Get_FreqOffset()
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