1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (��MStar Confidential Information��) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #include <math.h>
105 #include "MsCommon.h"
106 #include "MsIRQ.h"
107 #include "MsOS.h"
108 //#include "apiPWS.h"
109
110 #include "MsTypes.h"
111 #include "drvBDMA.h"
112 //#include "drvIIC.h"
113 //#include "msAPI_Tuner.h"
114 //#include "msAPI_MIU.h"
115 //#include "BinInfo.h"
116 //#include "halVif.h"
117 #include "drvDMD_INTERN_DVBC.h"
118 #include "halDMD_INTERN_DVBC.h"
119 #include "halDMD_INTERN_common.h"
120 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
121 #include "InfoBlock.h"
122 #endif
123 #include "drvMMIO.h"
124 //#include "TDAG4D01A_SSI_DVBT.c"
125 #include "drvDMD_VD_MBX.h"
126 #define TEST_EMBEDED_DEMOD 0
127 //U8 load_data_variable=1;
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
130
131 #define TDE_REG_BASE 0x2400
132 #define INNC_REG_BASE 0x2600
133 #define EQE_REG_BASE 0x2c00
134 #define EQE2_REG_BASE 0x2d00
135
136 #ifdef MS_DEBUG
137 #define DBG_INTERN_DVBC(x) x
138 #define DBG_GET_SIGNAL_DVBC(x) x
139 #define DBG_INTERN_DVBC_TIME(x) x
140 #define DBG_INTERN_DVBC_LOCK(x) x
141 #define INTERN_DVBC_INTERNAL_DEBUG 0
142 #else
143 #define DBG_INTERN_DVBC(x) //x
144 #define DBG_GET_SIGNAL_DVBC(x) //x
145 #define DBG_INTERN_DVBC_TIME(x) //x
146 #define DBG_INTERN_DVBC_LOCK(x) //x
147 #define INTERN_DVBC_INTERNAL_DEBUG 0
148 #endif
149 #define DBG_DUMP_LOAD_DSP_TIME 0
150
151
152 #define SIGNAL_LEVEL_OFFSET 0.00f
153 #define TAKEOVERPOINT -60.0f
154 #define TAKEOVERRANGE 0.5f
155 #define LOG10_OFFSET -0.21f
156 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
157 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
158
159 #define TUNER_IF 5000
160
161 #define TS_SER_C 0x00 //0: parallel 1:serial
162
163 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
164 #define TS_INV_C 0x01
165 #else
166 #define TS_INV_C 0x00
167 #endif
168
169 #define DVBC_FS 48000
170 #define CFG_ZIF 0x00 //For ZIF ,FC=0
171 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
172 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
173 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
174 #define FS_L_C (DVBC_FS&0xFF)
175 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
176 #define IQ_SWAP_C 0x00
177 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
178 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
179 // Symbol Rate: 6875 = 0x1ADB
180 // Symbol Rate: 6900 = 0x1AF4
181 // Symbol Rate: 7000 = 0x1B58
182 // Symbol Rate: 4000 = 0x0FA0
183 // Symbol Rate: 6125 = 0x17ED
184 #define SR0_H 0x1A
185 #define SR0_L 0xF4 //6900
186 #define SR1_H 0x1B
187 #define SR1_L 0x58 //7000
188 #define SR2_H 0x17
189 #define SR2_L 0xED //6125
190 #define SR3_H 0x0F
191 #define SR3_L 0xA0 //4000
192 #define SR4_H 0x1B
193 #define SR4_L 0x26 //6950
194 #define SR5_H 0x1A //0xDB
195 #define SR5_L 0xDB //0x1A //6875
196 #define SR6_H 0x1C
197 #define SR6_L 0x20 //7200
198 #define SR7_H 0x1C
199 #define SR7_L 0x52 //7250
200 #define SR8_H 0x0B
201 #define SR8_L 0xB8 //3000
202 #define SR9_H 0x03
203 #define SR9_L 0xE8 //1000
204 #define SR10_H 0x07
205 #define SR10_L 0xD0 //2000
206 #define SR11_H 0x00
207 #define SR11_L 0x00 //0000
208
209
210 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
211
212 // SAR dependent
213 #define NO_SIGNAL_TH_A 0xA3
214 // Tuner dependent
215 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
216 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
217 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
218 #define NO_SIGNAL_TH_C_H 0xff //0x00
219 #define DAGC1_REF 0x70
220 #define DAGC2_REF 0x30
221 #define AGC_REF_L 0x00
222 #define AGC_REF_H 0x06
223
224 #define INTERN_AUTO_SR_C 1
225 #define INTERN_AUTO_QAM_C 1
226
227 #define ATV_DET_EN 1
228
229
230 MS_U8 INTERN_DVBC_DSPREG[] =
231 {
232 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
233 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
234 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
235 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
236 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
237 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
238 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
239 };
240
241 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
242
243 //-----------------------------------------------------------------------
244 /****************************************************************
245 *Local Variables *
246 ****************************************************************/
247
248 //static MS_BOOL TPSLock = 0;
249 static MS_U32 u32ChkScanTimeStartDVBC = 0;
250 static MS_U8 g_dvbc_lock = 0;
251 static float intern_dvb_c_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
252
253 //Global Variables
254 S_CMDPKTREG gsCmdPacketDVBC;
255 //MS_U8 gCalIdacCh0, gCalIdacCh1;
256 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
257 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
258 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
259 MS_U8 INTERN_DVBC_table[] = {
260 #include "fwDMD_INTERN_DVBC.dat"
261 };
262
263 #endif
264
265 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
266 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
267 // MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
268 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
269 // MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff);
270 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
271 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
272 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
273
274 #if (INTERN_DVBC_INTERNAL_DEBUG)
275 void INTERN_DVBC_info(void);
276 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
277 #endif
278
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)279 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
280 {
281 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
282 MS_U8 status = TRUE;
283 MS_U16 u16DspAddr = 0;
284
285 DBG_INTERN_DVBC(printf("INTERN_DVBC_DSPReg_Init\n"));
286
287 #if 0//def MS_DEBUG
288 {
289 MS_U8 u8buffer[256];
290 printf("INTERN_DVBC_DSPReg_Init Reset\n");
291 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
292 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
293
294 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
295 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
296 printf("INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
297 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
298 printf("%x ", u8buffer[idx]);
299 printf("\n");
300
301 printf("INTERN_DVBC_DSPReg_Init Value\n");
302 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
303 printf("%x ", INTERN_DVBC_DSPREG[idx]);
304 printf("\n");
305 }
306 #endif
307
308 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
309 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
310
311 // readback to confirm.
312 #ifdef MS_DEBUG
313 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
314 {
315 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
316 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
317 {
318 printf("[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
319 }
320 }
321 #endif
322
323 if (u8DVBC_DSPReg != NULL)
324 {
325 if (1 == u8DVBC_DSPReg[0])
326 {
327 u8DVBC_DSPReg+=2;
328 for (idx = 0; idx<u8Size; idx++)
329 {
330 u16DspAddr = *u8DVBC_DSPReg;
331 u8DVBC_DSPReg++;
332 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
333 u8DVBC_DSPReg++;
334 u8Mask = *u8DVBC_DSPReg;
335 u8DVBC_DSPReg++;
336 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
337 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
338 u8DVBC_DSPReg++;
339 DBG_INTERN_DVBC(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
340 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
341 }
342 }
343 else
344 {
345 printf("FATAL: parameter version incorrect\n");
346 }
347 }
348
349 #if 0//def MS_DEBUG
350 {
351 MS_U8 u8buffer[256];
352 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
353 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
354 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
355 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
356 printf("%x ", u8buffer[idx]);
357 printf("\n");
358 }
359 #endif
360
361 #if 0//def MS_DEBUG
362 {
363 MS_U8 u8buffer[256];
364 for (idx = 0; idx<128; idx++)
365 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
366 printf("INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
367 for (idx = 0; idx<128; idx++)
368 {
369 printf("%x ", u8buffer[idx]);
370 if ((idx & 0xF) == 0xF) printf("\n");
371 }
372 printf("\n");
373 }
374 #endif
375 return status;
376 }
377
378 /***********************************************************************************
379 Subject: Command Packet Interface
380 Function: INTERN_DVBC_Cmd_Packet_Send
381 Parmeter:
382 Return: MS_BOOL
383 Remark:
384 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)385 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
386 {
387 return TRUE;
388 }
389
390
391 /***********************************************************************************
392 Subject: Command Packet Interface
393 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
394 Parmeter:
395 Return: MS_BOOL
396 Remark:
397 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)398 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
399 {
400 return TRUE;
401 }
402
403 /***********************************************************************************
404 Subject: SoftStop
405 Function: INTERN_DVBC_SoftStop
406 Parmeter:
407 Return: MS_BOOL
408 Remark:
409 ************************************************************************************/
410
INTERN_DVBC_SoftStop(void)411 MS_BOOL INTERN_DVBC_SoftStop ( void )
412 {
413 #if 1
414 MS_U16 u8WaitCnt=0;
415
416 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
417 {
418 printf(">> MB Busy!\n");
419 return FALSE;
420 }
421
422 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
423
424 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
425 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
426
427 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
428 {
429 #if TEST_EMBEDED_DEMOD
430 MsOS_DelayTask(1); // << Ken 20090629
431 #endif
432 if (u8WaitCnt++ >= 0x7FF)
433 {
434 printf(">> DVBT SoftStop Fail!\n");
435 return FALSE;
436 }
437 }
438
439 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
440 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
441 #endif
442 return TRUE;
443 }
444
445
446 /***********************************************************************************
447 Subject: Reset
448 Function: INTERN_DVBC_Reset
449 Parmeter:
450 Return: MS_BOOL
451 Remark:
452 ************************************************************************************/
453 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)454 MS_BOOL INTERN_DVBC_Reset ( void )
455 {
456 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_reset\n"));
457
458 DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime()));
459
460 INTERN_DVBC_SoftStop();
461
462
463 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
464 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
465 MsOS_DelayTask(5);
466 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
467 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
468 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
469 MsOS_DelayTask(5);
470
471 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
472 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
473
474 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
475 g_dvbc_lock = 0;
476
477 return TRUE;
478 }
479
480 /***********************************************************************************
481 Subject: Exit
482 Function: INTERN_DVBC_Exit
483 Parmeter:
484 Return: MS_BOOL
485 Remark:
486 ************************************************************************************/
INTERN_DVBC_Exit(void)487 MS_BOOL INTERN_DVBC_Exit ( void )
488 {
489
490 INTERN_DVBC_SoftStop();
491
492 return TRUE;
493 }
494
495 /***********************************************************************************
496 Subject: Load DSP code to chip
497 Function: INTERN_DVBC_LoadDSPCode
498 Parmeter:
499 Return: MS_BOOL
500 Remark:
501 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)502 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
503 {
504 MS_U8 udata = 0x00;
505 MS_U16 i;
506 MS_U16 fail_cnt=0;
507
508 #if (DBG_DUMP_LOAD_DSP_TIME==1)
509 MS_U32 u32Time;
510 #endif
511
512
513 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
514 BININFO BinInfo;
515 MS_BOOL bResult;
516 MS_U32 u32GEAddr;
517 MS_U8 Data;
518 MS_S8 op;
519 MS_U32 srcaddr;
520 MS_U32 len;
521 MS_U32 SizeBy4K;
522 MS_U16 u16Counter=0;
523 MS_U8 *pU8Data;
524 #endif
525
526
527
528 // MDrv_Sys_DisableWatchDog();
529
530
531 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
532 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
533 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
534 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
535 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
536 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
537
538 //// Load code thru VDMCU_IF ////
539 DBG_INTERN_DVBC(printf(">Load Code.....\n"));
540 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
541 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
542 {
543 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
544 }
545 #else
546 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
547 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
548 if ( bResult != PASS )
549 {
550 return FALSE;
551 }
552 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
553
554 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
555 InfoBlock_Flash_2_Checking_Start(&BinInfo);
556 #endif
557
558 #if OBA2
559 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
560 #else
561 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
562 #endif
563
564 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
565 InfoBlock_Flash_2_Checking_End(&BinInfo);
566 #endif
567
568 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
569 SizeBy4K=BinInfo.B_Len/0x1000;
570 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
571
572 #if (DBG_DUMP_LOAD_DSP_TIME==1)
573 u32Time = msAPI_Timer_GetTime0();
574 #endif
575
576 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
577
578 for (i=0;i<=SizeBy4K;i++)
579 {
580 if(i==SizeBy4K)
581 len=BinInfo.B_Len%0x1000;
582 else
583 len=0x1000;
584
585 srcaddr = u32GEAddr+(0x1000*i);
586 //printf("\t i = %08X\n", i);
587 //printf("\t len = %08X\n", len);
588 op = 1;
589 u16Counter = 0 ;
590 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
591 while(len--)
592 {
593 u16Counter ++ ;
594 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
595 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
596 #if OBA2
597 pU8Data = (MS_U8 *)(srcaddr);
598 #else
599 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
600 #endif
601 Data = *pU8Data;
602
603 #if 0
604 if(u16Counter < 0x100)
605 printf("0x%bx,", Data);
606 #endif
607 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
608
609 srcaddr += op;
610 }
611 // printf("\n\n\n");
612 }
613
614 #if (DBG_DUMP_LOAD_DSP_TIME==1)
615 printf("------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
616 #endif
617
618 #endif
619
620 //// Content verification ////
621 DBG_INTERN_DVBC(printf(">Verify Code...\n"));
622
623 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
624 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
625
626 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
627 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
628 {
629 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
630 if (udata != INTERN_DVBC_table[i])
631 {
632 printf(">fail add = 0x%x\n", i);
633 printf(">code = 0x%x\n", INTERN_DVBC_table[i]);
634 printf(">data = 0x%x\n", udata);
635
636 if (fail_cnt > 10)
637 {
638 printf(">DVB-C DSP Loadcode fail!");
639 return false;
640 }
641 fail_cnt++;
642 }
643 }
644 #else
645 for (i=0;i<=SizeBy4K;i++)
646 {
647 if(i==SizeBy4K)
648 len=BinInfo.B_Len%0x1000;
649 else
650 len=0x1000;
651
652 srcaddr = u32GEAddr+(0x1000*i);
653 //printf("\t i = %08LX\n", i);
654 //printf("\t len = %08LX\n", len);
655 op = 1;
656 u16Counter = 0 ;
657 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
658 while(len--)
659 {
660 u16Counter ++ ;
661 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
662 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
663 #if OBA2
664 pU8Data = (MS_U8 *)(srcaddr);
665 #else
666 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
667 #endif
668 Data = *pU8Data;
669
670 #if 0
671 if(u16Counter < 0x100)
672 printf("0x%bx,", Data);
673 #endif
674 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
675 if (udata != Data)
676 {
677 printf(">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
678 printf(">code = 0x%x\n", Data);
679 printf(">data = 0x%x\n", udata);
680
681 if (fail_cnt++ > 10)
682 {
683 printf(">DVB-C DSP Loadcode fail!");
684 return false;
685 }
686 }
687
688 srcaddr += op;
689 }
690 // printf("\n\n\n");
691 }
692 #endif
693
694 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
695 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
696 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
697 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
698
699 DBG_INTERN_DVBC(printf(">DSP Loadcode done."));
700
701
702 return TRUE;
703 }
704
705 /***********************************************************************************
706 Subject: DVB-T CLKGEN initialized function
707 Function: INTERN_DVBC_Power_On_Initialization
708 Parmeter:
709 Return: MS_BOOL
710 Remark:
711 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)712 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
713 {
714 MS_U8 temp_val;
715 //move to drvSYS MS_U8 tmp;
716 // MS_U8 udatatemp = 0x00;
717 /************************************************************************
718 * T10 U01
719 * This bit0 is mux for DMD muc and HK,
720 * bit0: 0:HK can rw bank 0x1120, 1: DMD mcu can rw bank 0x1120;
721 ************************************************************************/
722 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
723 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
724 // CLK_DMDMCU clock setting
725 // [0] disable clock
726 // [1] invert clock
727 // [4:2]
728 // 000:170 MHz(MPLL_DIV_BUf)
729 // 001:160MHz
730 // 010:144MHz
731 // 011:123MHz
732 // 100:108MHz
733 // 101:mem_clcok
734 // 110:mem_clock div 2
735 // 111:select XTAL
736 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
737 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
738
739 // set parallet ts clock
740 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
741 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
742 // wriu 0x103301 0x06
743 // wriu 0x103300 0x19
744
745
746 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
747 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
748 temp_val|=0x07;
749 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
750
751 HAL_DMD_RIU_WriteByte(0x103300,0x13);
752
753 // enable atsc, DVBTC ts clock
754 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
755 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
756 // wriu 0x103309 0x00
757 // wriu 0x103308 0x00
758
759 HAL_DMD_RIU_WriteByte(0x103309,0x00);
760 HAL_DMD_RIU_WriteByte(0x103308,0x00);
761
762 // enable dvbc adc clock
763 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
764 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
765 // wriu 0x103315 0x00
766 // wriu 0x103314 0x00
767
768 HAL_DMD_RIU_WriteByte(0x103315,0x00);
769 HAL_DMD_RIU_WriteByte(0x103314,0x00);
770
771 // enable vif DAC clock
772 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
773 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
774 // wriu 0x10331b 0x00
775 // wriu 0x10331a 0x00
776
777 //HAL_DMD_RIU_WriteByte(0x10331b,0x00);
778 //HAL_DMD_RIU_WriteByte(0x10331a,0x00);
779
780 // Select MPLLDIV2
781 // [0] : reg_atsc_adc_sel_mplldiv2
782 // [1] : reg_atsc_eq_sel_mplldiv2
783 // [2] : reg_eq25_sel_mplldiv3
784 // [3] : reg_p4_cfo_sel_eq25
785 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h14, 2'b01, 16'h0003);
786 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h14, 2'b01, 16'h0003);
787 // wriu 0x112028 0x03
788 HAL_DMD_RIU_WriteByte(0x111f28,0x04);
789
790
791 // Select MPLLDIV2
792 // [0] : reg_fed_srd_on
793 // [1] : reg_dvbt_new_tdsfo_on
794 // [2] : reg_dvbc_p4_cfo_on
795 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h15, 2'b01, 16'h0001);
796 // wriu 0x111f2a 0x01
797 HAL_DMD_RIU_WriteByte(0x111f2a,0x01);
798
799
800 // *** Set register at CLKGEN_DMD
801 // enable atsc clock
802 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
803 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
804 // wriu 0x111f03 0x04
805 // wriu 0x111f02 0x04
806
807 // HAL_DMD_RIU_WriteByte(0x111f03,0x00);
808 // HAL_DMD_RIU_WriteByte(0x111f02,0x00);
809 HAL_DMD_RIU_WriteByte(0x111f03,0x04);
810 HAL_DMD_RIU_WriteByte(0x111f02,0x04);
811
812 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
813 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
814 // wriu 0x111f05 0x00
815 // wriu 0x111f04 0x00
816
817 HAL_DMD_RIU_WriteByte(0x111f05,0x00);
818 HAL_DMD_RIU_WriteByte(0x111f04,0x00);
819 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
820 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
821 // wriu 0x111f07 0x04
822 // wriu 0x111f06 0x04
823
824 // HAL_DMD_RIU_WriteByte(0x111f07,0x00);
825 // HAL_DMD_RIU_WriteByte(0x111f06,0x00);
826
827 HAL_DMD_RIU_WriteByte(0x111f07,0x04);
828 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
829
830 // enable clk_atsc_adcd_sync
831 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
832 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
833 // wriu 0x111f0b 0x00
834 // wriu 0x111f0a 0x00
835
836 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
837 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
838
839 // enable dvbt inner clock
840 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
841 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
842 // wriu 0x111f0d 0x00
843 // wriu 0x111f0c 0x00
844
845 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
846 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
847
848 // enable dvbt inner clock
849 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
850 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
851 // wriu 0x111f0f 0x00
852 // wriu 0x111f0e 0x00
853
854 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
855 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
856
857 // enable dvbt inner clock
858 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
859 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
860 // wriu 0x111f11 0x00
861 // wriu 0x111f10 0x00
862
863 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
864 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
865
866 // enable dvbc outer clock
867 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
868 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
869 // wriu 0x111f13 0x00
870 // wriu 0x111f12 0x00
871
872 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
873 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
874
875 // enable dvbc inner-c clock
876 // [11:8]: reg_ckg_dvbtc_innc
877 // [0] : disable clock
878 // [1] : invert clock
879 // [3:2]: Select clock source
880 // 00: clk_dmdadc
881 // 01: reserved
882 // 10: reserved
883 // 11: DFT_CLK
884 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
885
886
887
888 // enable dvbc eq
889 // [3:0] : reg_ckg_dvbtc_eq8x
890 // [0] : disable clock
891 // [1] : invert clock
892 // [3:2]: Select clock source
893 // 00: clk_dmplldiv3_div2
894 // 01: reserved
895 // 10: reserved
896 // 11: DFT_CLK
897 // [12:8]: reg_ckg_dvbtc_eq
898 // [0] : disable clock
899 // [1] : invert clock
900 // [3:2]: Select clock source
901 // 00: clk_dmplldiv3_div16
902 // 01: reserved
903 // 10: reserved
904 // 11: DFT_CLK
905 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
906 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
907 // wriu 0x111f17 0x00
908 // wriu 0x111f16 0x00
909
910
911 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
912 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
913
914
915 // [9:8] : reg_ckg_adc1x_eq1x
916 // [13:12] : reg_ckg_adc0p5x_eq0p5x
917 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b10, 16'h0000);
918 // wriu 0x111f49 0x00
919 HAL_DMD_RIU_WriteByte(0x111f49,0x00); // Eiffel for power4CFO open clock
920 HAL_DMD_RIU_WriteByte(0x111f48,0x00); // Eiffel for power4CFO open clock
921
922 HAL_DMD_RIU_WriteByte(0x111f4b,0x00); // Eiffel for power4CFO open clock
923 HAL_DMD_RIU_WriteByte(0x111f4a,0x00); // Eiffel for power4CFO open clock
924 // enable sram clock
925 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
926 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
927 // wriu 0x111f19 0x00
928 // wriu 0x111f18 0x00
929
930
931
932
933 // enable vif clock
934 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
935 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
936 // wriu 0x111f1d 0x00
937 // wriu 0x111f1c 0x00
938
939 //HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
940 //HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
941
942 // enable DEMODE-DMA clock
943 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
944 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
945 // wriu 0x111f21 0x00
946 // wriu 0x111f20 0x00
947
948 //HAL_DMD_RIU_WriteByte(0x111f21,0x00);
949 //HAL_DMD_RIU_WriteByte(0x111f20,0x00);
950 // select clock
951 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
952 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
953 // wriu 0x111f23 0x04
954 // wriu 0x111f22 0x44
955 // HAL_DMD_RIU_WriteByte(0x111f23,0x00);
956 // HAL_DMD_RIU_WriteByte(0x111f22,0x00);
957
958 // select clock
959 // [3:0] : reg_ckg_frontend
960 // [0] : disable clock
961 // [1] : invert clock
962 // [3:2]: Select clock source
963 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
964 // 01: select clk_dmdadc (48 MHz, DVBT/C)
965 // 10: reserved
966 // 11: select DFT_CLK
967 // [7:4] : reg_ckg_tr
968 // [0] : disable clock
969 // [1] : invert clock
970 // [3:2]: Select clock source
971 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
972 // 01: select clk_dmdadc (48 MHz, DVBT/C)
973 // 10: reserved
974 // 11: select DFT_CLK
975 // [11:8]: reg_ckg_acifir
976 // [0] : disable clock
977 // [1] : invert clock
978 // [3:2]: Select clock source
979 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
980 // 01: select clk_dmdadc (48 MHz, DVBT/C)
981 // 10: clk_dmplldiv10_div2 (43.2 MHz, VIF)
982 // 11: select DFT_CLK
983 // [15:12]: reg_ckg_frontend_d2
984 // [0] : disable clock
985 // [1] : invert clock
986 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444); // ???
987 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
988 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
989
990 HAL_DMD_RIU_WriteByte(0x111f51,0x00);
991 HAL_DMD_RIU_WriteByte(0x111f50,0x44);
992 // Turn on New symbol rate detection
993 // [3] : reg_dvbt_new_tdsfo_on
994 // [2] : reg_fed_srd_on
995 // `M3_RIU_W( (`RIUBASE_DMD_TOP_M3>>1)+7'h00, 2'b01, 16'h0004);
996 // `M3_RIU_W( (`RIUBASE_DMD_TOP_M3>>1)+7'h00, 2'b01, 16'h0004);
997 // HAL_DMD_RIU_WriteByte(0x112000, 0x04); // Eiffel
998
999
1000 // ----------------------------------------------
1001 // start demod CLKGEN setting
1002 // ----------------------------------------------
1003 // select DMD MCU
1004 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1005 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1006 // [0] 0:TOP HK; 1:DMDMCU
1007 // [1] 0:DMDANAQ HK; 1:DMDMCU
1008 // begin BY temp patch
1009 //HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1010 //HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1011 // end
1012 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1013
1014 // ----------------------------------------------
1015 // Turn TSP
1016 // ----------------------------------------------
1017 // set the ts0_clk from demod
1018 // [3:0]: CLK_TS0 clock setting
1019 // [0] : disable
1020 // [1] : invert clock
1021 // [3:2]: Select clock source
1022 // 00: select TS0_CLK
1023 // 01: select TS1_CLK
1024 // 10: reserved
1025 // 11: clk_demod_ts_p
1026 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28 , 2'b11, 16'h000c);
1027
1028 // PWDN_REF_eco => reg_reserve0[10] = 0
1029 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1030 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1031 // swch 3
1032 // wriu 0x000e13 0x01
1033
1034 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1035 }
1036
1037 /***********************************************************************************
1038 Subject: Power on initialized function
1039 Function: INTERN_DVBC_Power_On_Initialization
1040 Parmeter:
1041 Return: MS_BOOL
1042 Remark:
1043 ************************************************************************************/
1044
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)1045 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
1046 {
1047 MS_U8 status = true;
1048 DBG_INTERN_DVBC(printf("INTERN_DVBC_Power_On_Initialization\n"));
1049
1050 #if defined(PWS_ENABLE)
1051 Mapi_PWS_Stop_VDMCU();
1052 #endif
1053
1054 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
1055 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1056 //// Firmware download //////////
1057 DBG_INTERN_DVBC(printf("INTERN_DVBC Load DSP...\n"));
1058 //MsOS_DelayTask(100);
1059
1060
1061 {
1062 if (INTERN_DVBC_LoadDSPCode() == FALSE)
1063 {
1064 printf("DVB-C Load DSP Code Fail\n");
1065 return FALSE;
1066 }
1067 else
1068 {
1069 DBG_INTERN_DVBC(printf("DVB-C Load DSP Code OK\n"));
1070 }
1071 }
1072
1073 status &= INTERN_DVBC_Reset();
1074
1075 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
1076
1077 return status;
1078 }
1079
1080 /************************************************************************************************
1081 Subject: Driving control
1082 Function: INTERN_DVBC_Driving_Control
1083 Parmeter: bInversionEnable : TRUE For High
1084 Return: void
1085 Remark:
1086 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)1087 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
1088 {
1089 MS_U8 u8Temp;
1090
1091 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1092
1093 if (bEnable)
1094 {
1095 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1096 }
1097 else
1098 {
1099 u8Temp = u8Temp & (~0x01);
1100 }
1101
1102 DBG_INTERN_DVBC(printf("---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1103 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1104 }
1105 /************************************************************************************************
1106 Subject: Clk Inversion control
1107 Function: INTERN_DVBC_Clk_Inversion_Control
1108 Parmeter: bInversionEnable : TRUE For Inversion Action
1109 Return: void
1110 Remark:
1111 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)1112 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1113 {
1114 MS_U8 u8Temp;
1115
1116 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1117
1118 if (bInversionEnable)
1119 {
1120 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1121 }
1122 else
1123 {
1124 u8Temp = u8Temp & (~0x02);
1125 }
1126
1127 DBG_INTERN_DVBC(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1128 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1129 }
1130 /************************************************************************************************
1131 Subject: Transport stream serial/parallel control
1132 Function: INTERN_DVBC_Serial_Control
1133 Parmeter: bEnable : TRUE For serial
1134 Return: MS_BOOL :
1135 Remark:
1136 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1137 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1138 {
1139 MS_U8 status = true;
1140 MS_U8 temp_val;
1141 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_ts... u8TSClk=%d\n", u8TSClk));
1142
1143 return status;
1144
1145 if (u8TSClk == 0xFF) u8TSClk=0x13;
1146 if (bEnable) //Serial mode for TS pad
1147 {
1148 // serial
1149 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1150 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1151
1152 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1153 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1154 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1155 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1156 temp_val|=0x04;
1157 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1158 #else
1159 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1160 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1161 temp_val|=0x07;
1162 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1163 #endif
1164
1165
1166 //// INTERN_DVBC TS Control: Serial //////////
1167
1168 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_SERIAL);
1169
1170 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1171 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1172 #else
1173 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1174 #endif
1175 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1176
1177 gsCmdPacketDVBC.param[0] = TS_SERIAL;
1178 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1179 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1180 #else
1181 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1182 #endif
1183 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1184 }
1185 else
1186 {
1187 //parallel
1188 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1189 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1190
1191 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1192 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1193 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1194 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1195 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1196 temp_val|=0x05;
1197 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1198 #else
1199 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1200 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1201 temp_val|=0x07;
1202 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1203 #endif
1204
1205
1206 //// INTERN_DVBC TS Control: Parallel //////////
1207
1208 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_PARALLEL);
1209
1210 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1211 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1212 #else
1213 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1214 #endif
1215 //// INTERN_DVBC TS Control: Parallel //////////
1216 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1217
1218 gsCmdPacketDVBC.param[0] = TS_PARALLEL;
1219 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1220 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1221 #else
1222 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1223 #endif
1224 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1225 }
1226
1227 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1228 DBG_INTERN_DVBC(printf("---> Inversion(Bit5) = %d \n",0 ));
1229 #else
1230 DBG_INTERN_DVBC(printf("---> Inversion(Bit5) = %d \n",1 ));
1231 #endif
1232
1233 INTERN_DVBC_Driving_Control(INTERN_DVBC_DTV_DRIVING_LEVEL);
1234 return status;
1235 }
1236
1237 /************************************************************************************************
1238 Subject: TS1 output control
1239 Function: INTERN_DVBC_PAD_TS1_Enable
1240 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1241 Return: void
1242 Remark:
1243 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)1244 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
1245 {
1246 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_TS1_Enable... \n"));
1247
1248 if(flag) // PAD_TS1 Enable TS CLK PAD
1249 {
1250 //printf("=== TS1_Enable ===\n");
1251 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1252 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1253 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1254 }
1255 else // PAD_TS1 Disable TS CLK PAD
1256 {
1257 //printf("=== TS1_Disable ===\n");
1258 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1259 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1260 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1261 }
1262 }
1263
1264 /************************************************************************************************
1265 Subject: channel change config
1266 Function: INTERN_DVBC_Config
1267 Parmeter: BW: bandwidth
1268 Return: MS_BOOL :
1269 Remark:
1270 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1271 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1272 {
1273
1274 MS_U8 status = true;
1275 MS_U8 reg_symrate_l, reg_symrate_h;
1276 //MS_U16 u16Fc = 0;
1277 MS_U8 temp_val;
1278 // force
1279 // u16SymbolRate = 0;
1280 // eQamMode = DMD_DVBC_QAMAUTO;
1281
1282 pu16_symbol_rate_list = pu16_symbol_rate_list;
1283 u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1284
1285 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk));
1286 DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime()));
1287
1288 if (u8TSClk == 0xFF) u8TSClk=0x13;
1289
1290 /*
1291 switch(u32IFFreq)
1292 {
1293 case 36125:
1294 case 36167:
1295 case 36000:
1296 case 6000:
1297 case 4560:
1298 //u16Fc = DVBC_FS - u32IFFreq;
1299 DBG_INTERN_DVBC(printf("Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1300 break;
1301 case 44000:
1302 default:
1303 printf("IF frequency not supported\n");
1304 status = false;
1305 break;
1306 }
1307 */
1308
1309 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1310 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1311
1312 status &= INTERN_DVBC_Reset();
1313
1314 if (eQamMode == DMD_DVBC_QAMAUTO)
1315 {
1316 DBG_INTERN_DVBC(printf("DMD_DVBC_QAMAUTO\n"));
1317 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1318 // give default value.
1319 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1320 }
1321 else
1322 {
1323 DBG_INTERN_DVBC(printf("DMD_DVBC_QAM %d\n", eQamMode));
1324 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1325 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1326 }
1327 // auto symbol rate enable/disable
1328 if (u16SymbolRate == 0)
1329 {
1330 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1331 }
1332 else
1333 {
1334 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1335 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1336 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1337 }
1338 // TS mode
1339 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1340
1341 // IQ Swap
1342 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1343
1344 // Fc
1345 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1346 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1347 // Lif
1348 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1349 // Fif
1350 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1351 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1352
1353 //// INTERN_DVBC system init: DVB-C //////////
1354 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1355
1356 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1357 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1358
1359 if (bSerialTS)
1360 {
1361 // serial
1362 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1363 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1364
1365 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1366 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1367 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1368 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1369 temp_val|=0x04;
1370 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1371 #else
1372 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1373 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1374 temp_val|=0x07;
1375 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1376 #endif
1377 }
1378 else
1379 {
1380 //parallel
1381 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1382 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1383
1384 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1385 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1386 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1387 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1388 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1389 temp_val|=0x05;
1390 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1391 #else
1392 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1393 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1394 temp_val|=0x07;
1395 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1396 #endif
1397 }
1398 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1399 INTERN_DVBC_Show_Demod_Version();
1400 #endif
1401
1402 return status;
1403 }
1404 /************************************************************************************************
1405 Subject: enable hw to lock channel
1406 Function: INTERN_DVBC_Active
1407 Parmeter: bEnable
1408 Return: MS_BOOL
1409 Remark:
1410 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1411 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1412 {
1413 MS_U8 status = true;
1414
1415 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_active\n"));
1416
1417 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1418
1419
1420 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1421 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1422 return status;
1423 }
1424
1425
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)1426 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1427 {
1428 MS_U16 u16Address = 0;
1429 MS_U8 cData = 0;
1430 MS_U8 cBitMask = 0;
1431
1432 if (fCurrRFPowerDbm < 100.0f)
1433 {
1434 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1435 {
1436 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1437 if (cData > 5)
1438 {
1439 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1440 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1441 }
1442 else
1443 {
1444 if ((fCurrRFPowerDbm<fNoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000))
1445 {
1446 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1447 }
1448 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1449 {
1450 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1451 #ifdef MS_DEBUG
1452 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1453 #endif
1454 return TRUE;
1455 }
1456 }
1457 #ifdef MS_DEBUG
1458 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%f Threshold:%f Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1459 #endif
1460 }
1461 }
1462
1463 {
1464 switch( eType )
1465 {
1466 case DMD_DVBC_GETLOCK_FEC_LOCK:
1467 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1468 #if (INTERN_DVBC_INTERNAL_DEBUG)
1469 INTERN_DVBC_info();
1470 #endif
1471 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_GetLock FSM 0x%x\n",cData));
1472 if (cData == 0x0C)
1473 {
1474 if(g_dvbc_lock == 0)
1475 {
1476 g_dvbc_lock = 1;
1477 DBG_INTERN_DVBC(printf("[T12][DVBC]lock++++\n"));
1478
1479 }
1480 return TRUE;
1481 }
1482 else
1483 {
1484 if(g_dvbc_lock == 1)
1485 {
1486 g_dvbc_lock = 0;
1487 DBG_INTERN_DVBC(printf("[T12][DVBC]unlock----\n"));
1488 }
1489 return FALSE;
1490 }
1491 break;
1492
1493 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1494 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1495 cBitMask = BIT(1);
1496 break;
1497
1498 case DMD_DVBC_GETLOCK_DCR_LOCK:
1499 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1500 cBitMask = BIT(0);
1501 break;
1502
1503 case DMD_DVBC_GETLOCK_AGC_LOCK:
1504 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1505 cBitMask = BIT(0);
1506 break;
1507
1508 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1509 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1510 cBitMask = BIT(2)|BIT(3)|BIT(4);
1511 #ifdef MS_DEBUG
1512 {
1513 MS_U8 reg_frz=0, FSM=0;
1514 MS_U16 u16Timer=0;
1515 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1516 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1517 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1518 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1519 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1520 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1521 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1522 u16Timer=(u16Timer<<8)+reg_frz;
1523 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1524 u16Timer=(u16Timer<<8)+reg_frz;
1525 printf("DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1526 }
1527 #endif
1528 break;
1529
1530 case DMD_DVBC_GETLOCK_ATV_DETECT:
1531 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1532 cBitMask = BIT(1); // check atv
1533 break;
1534
1535 case DMD_DVBC_GETLOCK_TR_LOCK:
1536 #if 0 // 20111108 temporarily solution
1537 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
1538 cBitMask = BIT(4);
1539 break;
1540 #endif
1541 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1542 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1543 cBitMask = BIT(4);
1544 break;
1545
1546 default:
1547 return FALSE;
1548 }
1549
1550 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1551 return FALSE;
1552
1553 if ((cData & cBitMask) != 0)
1554 {
1555 return TRUE;
1556 }
1557
1558 return FALSE;
1559 }
1560
1561 return FALSE;
1562 }
1563
1564
1565 /****************************************************************************
1566 Subject: To get the Post viterbi BER
1567 Function: INTERN_DVBC_GetPostViterbiBer
1568 Parmeter: Quility
1569 Return: E_RESULT_SUCCESS
1570 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1571 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1572 We will not read the Period, and have the "/256/8"
1573 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(float * ber)1574 MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber)
1575 {
1576 MS_BOOL status = true;
1577 MS_U8 reg = 0, reg_frz = 0;
1578 MS_U16 BitErrPeriod;
1579 MS_U32 BitErr;
1580 MS_U16 PktErr;
1581
1582 /////////// Post-Viterbi BER /////////////
1583
1584 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1585 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1586 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1587
1588 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1589 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1590 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1591 BitErrPeriod = reg;
1592
1593 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1594 BitErrPeriod = (BitErrPeriod << 8)|reg;
1595
1596 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1597 // 0x6b [15:8] reg_bit_err_num_15_8
1598 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1599 // 0x6d [15:8] reg_bit_err_num_31_24
1600 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1601 BitErr = reg;
1602
1603 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1604 BitErr = (BitErr << 8)|reg;
1605
1606 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1607 BitErr = (BitErr << 8)|reg;
1608
1609 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1610 BitErr = (BitErr << 8)|reg;
1611
1612 INTERN_DVBC_GetPacketErr(&PktErr);
1613
1614 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1615 reg_frz=reg_frz&(~0x03);
1616 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1617
1618 if (BitErrPeriod == 0 ) //protect 0
1619 BitErrPeriod = 1;
1620
1621 if (BitErr <=0 )
1622 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1623 else
1624 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1625
1626 DBG_GET_SIGNAL_DVBC(printf("INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1627
1628 return status;
1629 }
1630
1631
1632 /****************************************************************************
1633 Subject: To get the Packet error
1634 Function: INTERN_DVBC_GetPacketErr
1635 Parmeter: pktErr
1636 Return: E_RESULT_SUCCESS
1637 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1638 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1639 We will not read the Period, and have the "/256/8"
1640 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1641 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1642 {
1643 MS_BOOL status = true;
1644 MS_U8 reg = 0, reg_frz = 0;
1645 MS_U16 PktErr;
1646
1647 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1648 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1649 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1650
1651 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1652 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1653 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1654 PktErr = reg;
1655
1656 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1657 PktErr = (PktErr << 8)|reg;
1658
1659 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1660 reg_frz=reg_frz&(~0x03);
1661 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1662
1663 DBG_GET_SIGNAL_DVBC(printf("INTERN_DVBC PktErr = %d \n ", (int)PktErr));
1664
1665 *pktErr = PktErr;
1666
1667 return status;
1668 }
1669
1670 /****************************************************************************
1671 Subject: Read the signal to noise ratio (SNR)
1672 Function: INTERN_DVBC_GetSNR
1673 Parmeter: None
1674 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1675 Remark:
1676 *****************************************************************************/
INTERN_DVBC_GetSNR(float * f_snr)1677 MS_BOOL INTERN_DVBC_GetSNR(float *f_snr)
1678 {
1679 MS_BOOL status = true;
1680 MS_U8 u8Data = 0, reg_frz = 0;
1681 // MS_U8 freeze = 0;
1682 MS_U16 noisepower = 0;
1683
1684 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1685 {
1686 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1687 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1688 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1689
1690 // read vk
1691 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data);
1692 noisepower = u8Data;
1693 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data);
1694 noisepower = (noisepower<<8)|u8Data;
1695
1696 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1697 reg_frz=reg_frz&(~0x01);
1698 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1699
1700 if(noisepower == 0x0000)
1701 noisepower = 0x0001;
1702
1703 #ifdef MSOS_TYPE_LINUX
1704 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1705 #else
1706 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1707 #endif
1708
1709 }
1710 else
1711 {
1712 *f_snr = 0.0f;
1713 }
1714 return status;
1715
1716
1717 }
1718
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1719 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1720 {
1721 MS_BOOL status = true;
1722 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1723 DMD_DVBC_MODULATION_TYPE Qam_mode;
1724
1725 DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi)));
1726
1727 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1728 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1729 /* Actually, it's more reasonable, that signal level depended on cable input power level
1730 * thougth the signal isn't dvb-t signal.
1731 */
1732 // use pointer of IFAGC table to identify
1733 // case 1: RFAGC from SAR, IFAGC controlled by demod
1734 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1735 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1736 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
1737 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1738 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1739 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
1740 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
1741
1742 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1743
1744 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
1745 {
1746 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
1747 }
1748 else
1749 {
1750 ch_power_db_rel = -100.0f;
1751 }
1752
1753 if(ch_power_db_rel <= -85.0f)
1754 {*strength = 0;}
1755 else if (ch_power_db_rel <= -80.0f)
1756 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
1757 else if (ch_power_db_rel <= -75.0f)
1758 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
1759 else if (ch_power_db_rel <= -70.0f)
1760 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
1761 else if (ch_power_db_rel <= -65.0f)
1762 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
1763 else if (ch_power_db_rel <= -55.0f)
1764 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
1765 else if (ch_power_db_rel <= -45.0f)
1766 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
1767 else
1768 {*strength = 100;}
1769
1770 DBG_GET_SIGNAL_DVBC(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
1771 DBG_GET_SIGNAL_DVBC(printf(">>> SSI = %d <<<\n", (int)*strength));
1772
1773 return status;
1774 }
1775
1776 /****************************************************************************
1777 Subject: To get the DVT Signal quility
1778 Function: INTERN_DVBC_GetSignalQuality
1779 Parmeter: Quility
1780 Return: E_RESULT_SUCCESS
1781 E_RESULT_FAILURE
1782 Remark: Here we have 4 level range
1783 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1784 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1785 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1786 <4>.4th Range => Quality <10
1787 *****************************************************************************/
INTERN_DVBC_GetSignalQuality(MS_U16 * quality,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1788 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1789 {
1790
1791 float fber;
1792 float log_ber;
1793 MS_BOOL status = true;
1794 DMD_DVBC_MODULATION_TYPE Qam_mode;
1795 float f_snr;
1796
1797 fRFPowerDbm = fRFPowerDbm;
1798 status &= INTERN_DVBC_GetSNR(&f_snr);
1799 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
1800 {
1801 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
1802 {
1803 DBG_INTERN_DVBC(printf("\nGetPostViterbiBer Fail!"));
1804 return FALSE;
1805 }
1806
1807 // log_ber = log10(fber)
1808 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
1809
1810 DBG_INTERN_DVBC(printf("\nLog(BER) = %f",log_ber));
1811 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1812 if (Qam_mode == DMD_DVBC_QAM16)
1813 {
1814 if(log_ber <= (-5.5f))
1815 *quality = 100;
1816 else if(log_ber <= (-5.1f))
1817 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
1818 else if(log_ber <= (-4.9f))
1819 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1820 else if(log_ber <= (-4.5f))
1821 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
1822 else if(log_ber <= (-3.7f))
1823 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
1824 else if(log_ber <= (-3.2f))
1825 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1826 else if(log_ber <= (-2.9f))
1827 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1828 else if(log_ber <= (-2.5f))
1829 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
1830 else if(log_ber <= (-2.2f))
1831 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
1832 else if(log_ber <= (-2.0f))
1833 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1834 else
1835 *quality = 0;
1836 }
1837 else if (Qam_mode == DMD_DVBC_QAM32)
1838 {
1839 if(log_ber <= (-5.0f))
1840 *quality = 100;
1841 else if(log_ber <= (-4.7f))
1842 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
1843 else if(log_ber <= (-4.5f))
1844 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
1845 else if(log_ber <= (-3.8f))
1846 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
1847 else if(log_ber <= (-3.5f))
1848 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
1849 else if(log_ber <= (-3.0f))
1850 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
1851 else if(log_ber <= (-2.7f))
1852 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
1853 else if(log_ber <= (-2.4f))
1854 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1855 else if(log_ber <= (-2.2f))
1856 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1857 else if(log_ber <= (-2.0f))
1858 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1859 else
1860 *quality = 0;
1861 }
1862 else if (Qam_mode == DMD_DVBC_QAM64)
1863 {
1864 if(log_ber <= (-5.4f))
1865 *quality = 100;
1866 else if(log_ber <= (-5.1f))
1867 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
1868 else if(log_ber <= (-4.9f))
1869 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1870 else if(log_ber <= (-4.3f))
1871 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
1872 else if(log_ber <= (-3.7f))
1873 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
1874 else if(log_ber <= (-3.2f))
1875 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1876 else if(log_ber <= (-2.9f))
1877 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1878 else if(log_ber <= (-2.4f))
1879 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
1880 else if(log_ber <= (-2.2f))
1881 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1882 else if(log_ber <= (-2.05f))
1883 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
1884 else
1885 *quality = 0;
1886 }
1887 else if (Qam_mode == DMD_DVBC_QAM128)
1888 {
1889 if(log_ber <= (-5.1f))
1890 *quality = 100;
1891 else if(log_ber <= (-4.9f))
1892 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1893 else if(log_ber <= (-4.7f))
1894 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
1895 else if(log_ber <= (-4.1f))
1896 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
1897 else if(log_ber <= (-3.5f))
1898 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
1899 else if(log_ber <= (-3.1f))
1900 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1901 else if(log_ber <= (-2.7f))
1902 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1903 else if(log_ber <= (-2.5f))
1904 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
1905 else if(log_ber <= (-2.06f))
1906 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
1907 //else if(log_ber <= (-2.05))
1908 else
1909 {
1910 if (f_snr >= 27.2f)
1911 *quality = 20;
1912 else if (f_snr >= 25.1f)
1913 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
1914 else
1915 *quality = 0;
1916 }
1917 }
1918 else //256QAM
1919 {
1920 if(log_ber <= (-4.8f))
1921 *quality = 100;
1922 else if(log_ber <= (-4.6f))
1923 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
1924 else if(log_ber <= (-4.4f))
1925 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
1926 else if(log_ber <= (-4.0f))
1927 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
1928 else if(log_ber <= (-3.5f))
1929 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
1930 else if(log_ber <= (-3.1f))
1931 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1932 else if(log_ber <= (-2.7f))
1933 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1934 else if(log_ber <= (-2.4f))
1935 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1936 else if(log_ber <= (-2.06f))
1937 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
1938 //else if(log_ber <= (-2.05))
1939 else
1940 {
1941 if (f_snr >= 29.6f)
1942 *quality = 20;
1943 else if (f_snr >= 27.3f)
1944 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
1945 else
1946 *quality = 0;
1947 }
1948 }
1949 }
1950 else
1951 {
1952 *quality = 0;
1953 }
1954
1955 //DBG_GET_SIGNAL_DVBC(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
1956 DBG_GET_SIGNAL_DVBC(printf("BER = %8.3e\n", fber));
1957 DBG_GET_SIGNAL_DVBC(printf("Signal Quility = %d\n", *quality));
1958 return TRUE;
1959 }
1960
1961 /****************************************************************************
1962 Subject: To get the Cell ID
1963 Function: INTERN_DVBC_Get_CELL_ID
1964 Parmeter: point to return parameter cell_id
1965
1966 Return: TRUE
1967 FALSE
1968 Remark:
1969 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)1970 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
1971 {
1972 MS_BOOL status = true;
1973 MS_U8 value1 = 0;
1974 MS_U8 value2 = 0;
1975
1976 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
1977 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
1978
1979 *cell_id = ((MS_U16)value1<<8)|value2;
1980 return status;
1981 }
1982
1983 /****************************************************************************
1984 Subject: To get the DVBC Carrier Freq Offset
1985 Function: INTERN_DVBC_Get_FreqOffset
1986 Parmeter: Frequency offset (in KHz), bandwidth
1987 Return: E_RESULT_SUCCESS
1988 E_RESULT_FAILURE
1989 Remark:
1990 *****************************************************************************/
INTERN_DVBC_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)1991 MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
1992 {
1993 MS_U16 FreqB, config_Fc=0;
1994 float FreqCfo_offset,f_Fc;
1995 MS_U32 RegCfo_offset, Reg_Fc_over_Fs;
1996 MS_U8 reg_frz = 0, reg = 0;
1997 MS_BOOL status = TRUE;
1998
1999 // no use.
2000 u8BW = u8BW;
2001
2002 DBG_INTERN_DVBC(printf("INTERN_DVBC_Get_FreqOffset\n"));
2003
2004 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2005 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
2006 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
2007
2008 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, ®);
2009 RegCfo_offset = reg;
2010 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, ®);
2011 RegCfo_offset = (RegCfo_offset<<8)|reg;
2012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, ®);
2013 RegCfo_offset = (RegCfo_offset<<8)|reg;
2014 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, ®);
2015 RegCfo_offset = (RegCfo_offset<<8)|reg;
2016
2017 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2018 reg_frz=reg_frz&(~0x01);
2019 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
2020
2021 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
2022 Reg_Fc_over_Fs = reg;
2023 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
2024 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2025 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
2026 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
2028 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2029
2030 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
2031 config_Fc = reg;
2032 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
2033 config_Fc = (config_Fc<<8)|reg;
2034
2035 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
2036
2037 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
2038
2039 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
2040
2041 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
2042
2043 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
2044 DBG_INTERN_DVBC_LOCK(printf("[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
2045 FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc));
2046
2047 *pFreqOff = FreqCfo_offset;
2048
2049 return status;
2050 }
2051
2052
2053
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)2054 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
2055 {
2056
2057 bPowerOn = bPowerOn;
2058 }
2059
INTERN_DVBC_Power_Save(void)2060 MS_BOOL INTERN_DVBC_Power_Save(void)
2061 {
2062
2063 return TRUE;
2064 }
2065
2066 /****************************************************************************
2067 Subject: To get the current modulation type at the DVB-C Demod
2068 Function: INTERN_DVBC_GetCurrentModulationType
2069 Parmeter: pointer for return QAM type
2070
2071 Return: TRUE
2072 FALSE
2073 Remark:
2074 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)2075 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
2076 {
2077 MS_U8 u8Data=0;
2078
2079 DBG_INTERN_DVBC(printf("INTERN_DVBC_GetCurrentModulationType\n"));
2080
2081 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0xC4, &u8Data);
2082
2083 switch(u8Data&0x07)
2084 {
2085 case 0:
2086 *pQAMMode = DMD_DVBC_QAM16;
2087 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=16\n"));
2088 return TRUE;
2089 break;
2090 case 1:
2091 *pQAMMode = DMD_DVBC_QAM32;
2092 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=32\n"));
2093 return TRUE;
2094 break;
2095 case 2:
2096 *pQAMMode = DMD_DVBC_QAM64;
2097 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=64\n"));
2098 return TRUE;
2099 break;
2100 case 3:
2101 *pQAMMode = DMD_DVBC_QAM128;
2102 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=128\n"));
2103 return TRUE;
2104 break;
2105 case 4:
2106 *pQAMMode = DMD_DVBC_QAM256;
2107 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=256\n"));
2108 return TRUE;
2109 break;
2110 default:
2111 *pQAMMode = DMD_DVBC_QAMAUTO;
2112 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=invalid\n"));
2113 return FALSE;
2114 }
2115 }
2116
2117 /****************************************************************************
2118 Subject: To get the current symbol rate at the DVB-C Demod
2119 Function: INTERN_DVBC_GetCurrentSymbolRate
2120 Parmeter: pointer pData for return Symbolrate
2121
2122 Return: TRUE
2123 FALSE
2124 Remark:
2125 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)2126 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
2127 {
2128 MS_U8 tmp = 0;
2129 MS_U16 u16SymbolRateTmp = 0;
2130
2131 // intp
2132 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd2, &tmp);
2133 u16SymbolRateTmp = tmp;
2134 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd1, &tmp);
2135 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
2136
2137 if (abs(u16SymbolRateTmp-6900)<2)
2138 {
2139 u16SymbolRateTmp=6900;
2140 }
2141
2142 if (abs(u16SymbolRateTmp-6875)<2)
2143 {
2144 u16SymbolRateTmp=6875;
2145 }
2146
2147 *u16SymbolRate = u16SymbolRateTmp;
2148
2149 DBG_INTERN_DVBC_LOCK(printf("[dvbc]SR=%d\n",*u16SymbolRate));
2150
2151 return TRUE;
2152 }
2153
2154
2155 /****************************************************************************
2156 Subject: To get the current symbol rate offset at the DVB-C Demod
2157 Function: INTERN_DVBC_GetCurrentSymbolRate
2158 Parmeter: pointer pData for return Symbolrate offset
2159
2160 Return: TRUE
2161 FALSE
2162 Remark:
2163 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 * pData)2164 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
2165 {
2166 MS_U8 u8Data = 0, reg_frz = 0;
2167 MS_U32 u32Data = 0;
2168 // MS_S32 s32Data = 0;
2169 MS_BOOL status = TRUE;
2170 MS_U16 u16SymbolRate = 0;
2171 float f_symb_offset = 0.0f;
2172
2173
2174
2175 // bank 26 0x03 [7] reg_bit_err_num_freeze
2176 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
2177 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
2178
2179 // sel, SFO debug output.
2180 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
2181 u32Data = u8Data;
2182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
2183 u32Data = (u32Data<<8)|u8Data;
2184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
2185 u32Data = (u32Data<<8)|u8Data;
2186 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
2187 u32Data = (u32Data<<8)|u8Data;
2188
2189 // bank 26 0x03 [7] reg_bit_err_num_freeze
2190 reg_frz=reg_frz&(~0x80);
2191 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
2192 // s32Data = (MS_S32)(u32Data<<8);
2193
2194 printf("[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2195
2196 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2197
2198 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
2199 f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
2200
2201 *pData = (MS_U16)(f_symb_offset + 0.5f);
2202
2203 DBG_INTERN_DVBC_LOCK(printf("[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset));
2204
2205 return status;
2206 }
2207
INTERN_DVBC_Version(MS_U16 * ver)2208 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2209 {
2210
2211 MS_U8 status = true;
2212 MS_U8 tmp = 0;
2213 MS_U16 u16_INTERN_DVBC_Version;
2214
2215 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2216 u16_INTERN_DVBC_Version = tmp;
2217 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2218 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2219 *ver = u16_INTERN_DVBC_Version;
2220
2221 return status;
2222 }
2223
2224
INTERN_DVBC_Show_Demod_Version(void)2225 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2226 {
2227
2228 MS_BOOL status = true;
2229 MS_U16 u16_INTERN_DVBC_Version;
2230
2231 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2232
2233 printf("[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2234
2235 return status;
2236 }
2237
2238
2239
2240 #if (INTERN_DVBC_INTERNAL_DEBUG)
2241
INTERN_DVBC_Show_AGC_Info(void)2242 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2243 {
2244 MS_U8 tmp = 0;
2245 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2246 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2247 MS_U16 if_agc_err = 0;
2248 MS_BOOL status = TRUE;
2249
2250 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2251 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2252 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2254 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2255 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2256
2257
2258 // select IF gain to read
2259 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2260 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2261
2262 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2263 if_agc_gain = tmp;
2264 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2265 if_agc_gain = (if_agc_gain<<8)|tmp;
2266
2267
2268 // select d1 gain to read.
2269 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2270 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2271
2272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2273 d1_gain = tmp;
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2275 d1_gain = (d1_gain<<8)|tmp;
2276
2277 // select d2 gain to read.
2278 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2279 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2280
2281 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2282 d2_gain = tmp;
2283 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2284 d2_gain = (d2_gain<<8)|tmp;
2285
2286 // select IF gain err to read
2287 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2288 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2289
2290 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2291 if_agc_err = tmp;
2292 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2293 if_agc_err = (if_agc_err<<8)|tmp;
2294
2295 printf("[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2296 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2297
2298 printf("[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2299
2300 return status;
2301 }
2302
INTERN_DVBC_info(void)2303 void INTERN_DVBC_info(void)
2304 {
2305 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2306 MS_U8 qam,tmp = 0;
2307 MS_U8 fft_u8 = 0;
2308 MS_U16 fft_u16bw = 0;
2309 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2310 float f_snr = 0,f_freq = 0;
2311 DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2312 MS_U16 f_start = 0,f_end = 0;
2313 MS_U8 s0_count = 0;
2314 MS_U8 sc4 = 0,sc3 = 0;
2315 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2316 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2317 MS_U16 count = 0;
2318 MS_U16 fb_i_1,fb_q_1;
2319 MS_U8 e0,e1,e2,e3;
2320 MS_S16 reg_freq;
2321 float freq,mag;
2322
2323
2324
2325 INTERN_DVBC_Version(&version);
2326
2327 // fb_fs
2328 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2329 fb_fs = tmp;
2330 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2331 fb_fs = (fb_fs<<8)|tmp;
2332 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2333 fb_fs = (fb_fs<<8)|tmp;
2334 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2335 fb_fs = (fb_fs<<8)|tmp;
2336 // fc_fs
2337 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2338 fc_fs = tmp;
2339 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2340 fc_fs = (fc_fs<<8)|tmp;
2341 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2342 fc_fs = (fc_fs<<8)|tmp;
2343 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2344 fc_fs = (fc_fs<<8)|tmp;
2345 // crv
2346 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2347 crv = tmp;
2348 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2349 crv = (crv<<8)|tmp;
2350 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2351 crv = (crv<<8)|tmp;
2352 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2353 crv = (crv<<8)|tmp;
2354 // tr_error
2355 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2356 tr_error = tmp;
2357 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2358 tr_error = (tr_error<<8)|tmp;
2359 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2360 tr_error = (tr_error<<8)|tmp;
2361
2362 // intp
2363 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2364 intp = tmp;
2365 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2366 intp = (intp<<8)|tmp;
2367 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2368 intp = (intp<<8)|tmp;
2369 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2370 intp = (intp<<8)|tmp;
2371
2372 // fft info
2373 // intp
2374 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2375 fft_u16bw = tmp;
2376 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2377 fft_u16bw = (fft_u16bw<<8)|tmp;
2378 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2379 fft_u8 = tmp;
2380
2381
2382 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2383 qam = tmp;
2384
2385 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2386 f_start = tmp;
2387 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2388 f_start = (f_start<<8)|tmp;
2389 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2390 f_end = tmp;
2391 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2392 f_end = (f_end<<8)|tmp;
2393 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2394 s0_count = tmp;
2395
2396 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2397 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2398
2399 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2400 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2401 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2402 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2403 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2404 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2405 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2406
2407
2408 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2409
2410 count = 0x400;
2411 while(count--);
2412
2413 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2414 aci_e0 = tmp&0x0f;
2415 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2416 aci_e0 = aci_e0<<8|tmp;
2417
2418 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2419
2420 count = 0x400;
2421 while(count--);
2422
2423
2424 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2425 aci_e1 = tmp&0x0f;
2426 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2427 aci_e1 = aci_e1<<8|tmp;
2428
2429 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2430
2431 count = 0x400;
2432 while(count--);
2433
2434 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2435 aci_e2 = tmp&0x0f;
2436 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2437 aci_e2 = aci_e2<<8|tmp;
2438
2439 // read aci coef
2440 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2441
2442 count = 0x400;
2443 while(count--);
2444
2445 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2446 aci_e3 = tmp&0x0f;
2447 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2448 aci_e3 = aci_e3<<8|tmp;
2449
2450 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2451 fb_i_1 = tmp;
2452 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2453 fb_i_1 = fb_i_1<<8|tmp;
2454
2455 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2456 fb_q_1 = tmp;
2457 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2458 fb_q_1 = fb_q_1<<8|tmp;
2459
2460
2461 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2462 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2463 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2464 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2465
2466 reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2467 freq = (float)reg_freq*45473.0/65536.0;
2468 mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2469
2470
2471 INTERN_DVBC_GetPacketErr(&packetErr);
2472 INTERN_DVBC_GetSNR(&f_snr);
2473 INTERN_DVBC_Show_AGC_Info();
2474 INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2475 INTERN_DVBC_Get_FreqOffset(&f_freq,8);
2476 INTERN_DVBC_GetCurrentSymbolRate(&symb_rate);
2477 INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2478 INTERN_DVBC_GetCurrentModulationType(&QAMMode);
2479
2480 printf("[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2481 printf("[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2482 printf("[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2483 printf("[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2484 printf("[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2485 printf("[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2486 return;
2487 }
2488
2489
2490 #endif
2491
2492 /***********************************************************************************
2493 Subject: read register
2494 Function: MDrv_1210_IIC_Bypass_Mode
2495 Parmeter:
2496 Return:
2497 Remark:
2498 ************************************************************************************/
2499 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2500 //{
2501 // UNUSED(enable);
2502 // if (enable)
2503 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2504 // else
2505 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2506 //}
2507