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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #include <string.h>
108 #include <math.h>
109 #include "MsCommon.h"
110 #include "MsVersion.h"
111 #include "MsOS.h"
112
113 // Internal Definition
114 //#include "regCHIP.h"
115 //#include "regAVD.h"
116 //#include "mapi_tuner.h"
117 #include "drvSYS.h"
118 //#include "drvDMD_VD_MBX.h"
119 #include "drvDMD_EXTERN_MSB201X.h"
120 #include "include/drvDMD_common.h"
121 #include "include/drvSAR.h"
122 #include "drvMMIO.h"
123 #include "drvMSPI.h"
124 //-------------------------------------------------------------------------------------------------
125 // Driver Compiler Options
126 //-------------------------------------------------------------------------------------------------
127 #define ERR_DEMOD_MSB(x) x
128 #ifdef MS_DEBUG
129 #define DBG_DEMOD_MSB(x) x
130 #define DBG_DEMOD_FLOW(x) x
131 #define DBG_GET_SIGNAL(x) // x
132 #define DBG_DEMOD_LOAD_I2C(x) x
133 #define DBG_DEMOD_CHECKSUM(x) // x
134 #define DBG_FLASH_WP(x) // x
135 #endif
136 #define DBG_KIRIN_BOND(x) //x
137
138 //-------------------------------------------------------------------------------------------------
139 // Local Defines
140 //-------------------------------------------------------------------------------------------------
141 #define PRINTE(p) printf p
142
143 // BIT mask
144 #define _BIT0 0x01
145 #define _BIT1 0x02
146 #define _BIT2 0x04
147 #define _BIT3 0x08
148 #define _BIT4 0x10
149 #define _BIT5 0x20
150 #define _BIT6 0x40
151 #define _BIT7 0x80
152
153 // Demod bank number
154 #define TOP_REG_BASE 0x2000
155 #define TDP_REG_BASE 0x2100
156 #define FDP_REG_BASE 0x2200
157 #define FEC_REG_BASE 0x2300
158 #define TDF_REG_BASE 0x2700
159 #define TDFE_REG_BASE 0x2800
160 #define BACKEND_REG_BASE 0x2100
161 #define TDE_REG_BASE 0x2700
162 #define INNC_REG_BASE 0x2900
163 #define EQE_REG_BASE 0x2A00
164
165
166 MS_U8 MSB201X_DVBC_table[] = {
167 #include "MSB201X_DVBC.dat"
168 };
169
170 float MSB201X_Spur_freq_table[255] = {
171 48, 54, 56.5, 62, 64, 69, 72, 80.5, 81.5, 90,
172 92, 96, 98, 103.5, 108, 115, 118, 124, 126.5, 136,
173 138, 144, 152, 154, 161, 164, 170, 172.8, 180, 184,
174 190, 192, 193, 198, 204, 207, 208, 216, 218, 226,
175 230, 234, 236, 239, 240, 252, 253, 256, 262, 264,
176 268, 276, 288, 299, 300, 308, 311, 312, 322, 324,
177 330, 337, 340, 345, 345.6, 357, 360, 368, 380, 383,
178 386, 391, 396, 409, 412, 429, 432, 437, 452, 458,
179 460, 464, 468, 481, 484, 503, 506, 521.14, 524, 527,
180 552, 556, 573, 575, 576, 596, 599, 602, 608, 612,
181 625, 628, 644, 645, 648, 651, 668, 674, 680, 684,
182 697, 703, 713, 714, 720, 723, 736, 740, 746, 749,
183 752, 756, 759, 769, 772, 786, 789, 792, 795, 802,
184 812, 818, 828, 841, 844, 846.85, 0
185 };
186 #define MAX_SPUR_NUM 2
187 #define SRAM_Write_Buffer 128 // must < 255
188 #define SRAM_BASE 0x8000
189
190 #define LOAD_CODE_I2C_BLOCK_NUM 0x400//0x80
191
192 #define REG_MCU51_INTR 0x103400UL //need to be check
193 #define REG_DMD0_MB_CNTL 0x103500UL
194 #define REG_DMD0_MB_ADDR_L 0x103501UL
195 #define REG_DMD0_MB_ADDR_H 0x103502UL
196 #define REG_DMD0_MB_DATA 0x103503UL
197 #define REG_DMD0_FSM_EN 0x103528UL
198 #define REG_DMD1_MB_CNTL 0x103600UL
199 #define REG_DMD1_MB_ADDR_L 0x103601UL
200 #define REG_DMD1_MB_ADDR_H 0x103602UL
201 #define REG_DMD1_MB_DATA 0x103603UL
202 #define REG_DMD1_FSM_EN 0x103628UL
203 /* koln have only 2 demod
204 #define REG_DMD2_MB_CNTL 0x3300
205 #define REG_DMD2_MB_ADDR_L 0x3301
206 #define REG_DMD2_MB_ADDR_H 0x3302
207 #define REG_DMD2_MB_DATA 0x3303
208 #define REG_DMD2_FSM_EN 0x3328
209 #define REG_DMD3_MB_CNTL 0x3700
210 #define REG_DMD3_MB_ADDR_L 0x3701
211 #define REG_DMD3_MB_ADDR_H 0x3702
212 #define REG_DMD3_MB_DATA 0x3703
213 #define REG_DMD3_FSM_EN 0x3728
214 */
215 #define resetDemodTime 50
216 #define waitFlashTime 50
217
218 #define SRAM_DATA_CHECK 0
219 #define SRAM_BASE 0x8000
220 #define SPI_DEVICE_BUFFER_SIZE 256
221 #define MAX_MSB201X_LIB_LEN 131072
222
223 #define MSB201X_BOOT 0x01
224 #define MSB201X_DVBC 0x08
225 #define MSB201X_ALL 0x0F
226
227 #define MSB201X_BOOT_START_ADDR 0x00000
228 #define MSB201X_BOOT_END_ADDR 0x00FFF
229 #define MSB201X_DVBC_START_ADDR 0x18000
230 #define MSB201X_DVBC_END_ADDR 0x1FFFF
231
232 #define MSB201X_WINDOWS_BASE 0x100
233 #define MSB201X_BOOT_WINDOWS_OFFSET MSB201X_WINDOWS_BASE
234 #define MSB201X_DVBC_WINDOWS_OFFSET (MSB201X_WINDOWS_BASE + 0x18 + 0x08)
235
236 #define MSB201X_MAX_FLASH_ON_RETRY_NUM 3
237
238 #define UNUSED(x) (x=x)
239
240 /////////////// CONSTANT /////////////////
241 #define PAGE_WRITE_SIZE 256
242 #define VERSION_CODE_ADDR 0xFC0
243 #define VERSION_CODE_SIZE 32
244
245 //static eDMD_MSB201X_DbgLv eDMD_MSB201X_DbgLevel=E_DMD_MSB201X_DBGLV_NONE;
246
247 //kirin bonding option
248 #define DRV_RIU_ReadByte(_u32addr) (*(volatile MS_U32*)(_u32addr) )
249 //-------------------------------------------------------------------------------------------------
250 // Local Structurs
251 //-------------------------------------------------------------------------------------------------
252
253 //-------------------------------------------------------------------------------------------------
254 // Global Variables
255 //-------------------------------------------------------------------------------------------------
256 static MS_U8 g_dvbc_lock[DEMOD_MAX_INSTANCE][DEMOD_MAX_CHANNEL] = {{0,0}};
257
258 #if 0
259
260 #define DMD_LOCK() _Lock()
261 #define DMD_UNLOCK() _UnLock()
262
263 #else
264 #define DMD_LOCK() \
265 do{ \
266 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
267 MsOS_ObtainMutex(pDemod->s32_MSB201X_Mutex, MSOS_WAIT_FOREVER);\
268 }while(0)
269
270 #define DMD_UNLOCK() \
271 do{ \
272 MsOS_ReleaseMutex(pDemod->s32_MSB201X_Mutex);\
273 }while(0)
274
275 #endif
276 //-------------------------------------------------------------------------------------------------
277 // Local Variables
278 //-------------------------------------------------------------------------------------------------
279 #if 1
280 /*
281 static MSIF_Version _drv_dmd_MSB201X_extern_version = {
282 .MW = { DMD_MSB201X_EXTERN_VER, },
283 };
284 */
285 #else
286 static MSIF_Version _drv_dmd_msb123x_extern_version;
287 #endif
288
289 #define DEMOD_GET_ACTIVE_NODE(x) (pstDemod+x) //&_gDemodNode[x]
290
291
292 //configure
293 //--------------------------------------------------------------------- for DVB-C
294 #define TUNER_IF 5000
295
296 #define TS_SER_C 0x00 //0: parallel 1:serial
297
298 #if 1//test (INTERN_DVBC_TS_SERIAL_INVERSION)
299 #define TS_INV_C 0x01
300 #else
301 #define TS_INV_C 0x00
302 #endif
303
304 #define DVBC_FS 48000
305 #define CFG_ZIF 0x00 //For ZIF ,FC=0
306 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
307 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
308 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
309 #define FS_L_C (DVBC_FS&0xFF)
310 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
311 #define IQ_SWAP_C 0x01
312 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
313 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
314 // Symbol Rate: 6875 = 0x1ADB
315 // Symbol Rate: 6900 = 0x1AF4
316 // Symbol Rate: 7000 = 0x1B58
317 // Symbol Rate: 4000 = 0x0FA0
318 // Symbol Rate: 6125 = 0x17ED
319 #define SR0_H 0x1A
320 #define SR0_L 0xF4 //6900
321 #define SR1_H 0x1B
322 #define SR1_L 0x58 //7000
323 #define SR2_H 0x17
324 #define SR2_L 0xED //6125
325 #define SR3_H 0x0F
326 #define SR3_L 0xA0 //4000
327 #define SR4_H 0x1B
328 #define SR4_L 0x26 //6950
329 #define SR5_H 0x1A
330 #define SR5_L 0xDB //6875
331 #define SR6_H 0x1C
332 #define SR6_L 0x20 //7200
333 #define SR7_H 0x1C
334 #define SR7_L 0x52 //7250
335 #define SR8_H 0x0B
336 #define SR8_L 0xB8 //3000
337 #define SR9_H 0x03
338 #define SR9_L 0xE8 //1000
339 #define SR10_H 0x07
340 #define SR10_L 0xD0 //2000
341 #define SR11_H 0x00
342 #define SR11_L 0x00 //0000
343
344
345 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
346
347 // SAR dependent
348 #define NO_SIGNAL_TH_A 0xA3
349 // Tuner dependent
350 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
351 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
352 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
353 #define NO_SIGNAL_TH_C_H 0xff //0x00
354 #define DAGC1_REF 0x70
355 #define DAGC2_REF 0x30
356 #define AGC_REF_L 0xFF
357 #define AGC_REF_H 0x05
358
359 #define INTERN_AUTO_SR_C 1
360 #define INTERN_AUTO_QAM_C 1
361
362 #define ATV_DET_EN 1
363
364 MS_U8 MSB201X_DVBC_DSPREG_TABLE[] =
365 {
366 0x00, 0x01, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, 0x00, 0x01, 0x00, 0x88, 0x13, SR0_L, SR0_H,
367 QAM, IQ_SWAP_C, PAL_I_C, AGC_REF_L, AGC_REF_H, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H,
368 0x00,
369 };
370
371 typedef struct xMSB201X_Demod_Data
372 {
373 MS_BOOL Active;
374 MS_S32 s32_MSB201X_Mutex;
375 MS_BOOL bDMD_MSB201X_Power_init_en;
376 MS_U8 u8DMD_MSB201X_PowerOnInitialization_Flow;
377 MS_U8 u8DMD_MSB201X_Sram_Code;
378 sDMD_MSB201X_InitData _sDMD_MSB201X_InitData;
379 eDMD_MSB201X_DemodulatorType eDMD_MSB201X_CurrentDemodulatorType;
380 MS_BOOL bDemodRest;
381 MS_U8 DVBC_DSP_REG[DEMOD_MAX_CHANNEL][sizeof(MSB201X_DVBC_DSPREG_TABLE)];
382 sDMD_MSB201X_Info sDMD_MSB201X_Info[DEMOD_MAX_CHANNEL];
383 MS_U32 u32DMD_DVBC_PrevScanTime[DEMOD_MAX_CHANNEL];
384 MS_U32 u32DMD_DVBC_ScanCount[DEMOD_MAX_CHANNEL];
385 MS_BOOL DMD_Lock_Status[DEMOD_MAX_CHANNEL];
386 sDMD_MSB201X_IFAGC IFAGC_Data[DEMOD_MAX_CHANNEL];
387 e_MSB201X_DSP_ReadWrite DSP_ReadWrite_Mode;
388 sDMD_MSB201X_TS_Param sDMD_MSB201X_TS_Param;
389 MS_BOOL bDMD_MSB201X_TS_Param_Init_Done;
390 sDMD_MSB201X_extHeader sDMD_MSB201X_extHeader_Param;
391 sDMD_MSB201X_CIHeader sDMD_MSB201X_CIHeader_Param;
392 }tMSB201X_Demod_Data;
393
394 //static MS_S32 _gActiveInstanceIndex = 0;
395 //static eDMD_MSB201X_DbgLv eDMD_MSB201X_DbgLevel=E_DMD_MSB201X_DBGLV_NONE;
396 static tMSB201X_Demod_Data* pstDemod = NULL;
397 static MS_BOOL* pDemodRest = NULL;
398
399
400
401 static tMSB201X_Demod_Data MSB201X_Demod_Init=
402 {
403 FALSE,
404 -1,
405 FALSE,
406 0,
407 0,
408 {0},
409 E_DMD_MSB201X_DEMOD_DVBC,
410 TRUE,
411 {{0,0}},
412 {{0,0}},
413 {0},
414 {0},
415 {0}
416 };
417
418 // Timeout setting
419 static MS_U16 u16DMD_DVBC_AutoSymbol_Timeout = 10000, u16DMD_DVBC_FixSymbol_AutoQam_Timeout=2000, u16DMD_DVBC_FixSymbol_FixQam_Timeout=1000;
420
421 //-------------------------------------------------------------------------------------------------
422 // Debug Functions
423 //-------------------------------------------------------------------------------------------------
424 #ifdef MS_DEBUG
425 #define DMD_DBG(x) (x)
426 #else
427 #define DMD_DBG(x) //(x)
428 #endif
429 //-------------------------------------------------------------------------------------------------
430 // Local Functions
431 //-------------------------------------------------------------------------------------------------
432
433 //-------------------------------------------------------------------------------------------------
434 // Global Functions
435 //-------------------------------------------------------------------------------------------------
436 #define INDEX_TO_HANDLE(x) ((x)+1)
437 #define HANDLE_TO_INDEX(x) ((x)-1)
438 #define CFG_W_CMD 0x05
_MDrv_DMD_MSB201X_SSPI_CFG_W(MS_U8 u8_addr,MS_U8 data)439 MS_BOOL _MDrv_DMD_MSB201X_SSPI_CFG_W(MS_U8 u8_addr,MS_U8 data)
440 {
441 MS_BOOL bRet = TRUE;
442 MS_U8 Wdata[3];
443
444 Wdata[0] = CFG_W_CMD;
445 Wdata[1] = u8_addr;
446 Wdata[2] = data;
447
448 // Write operation
449 MDrv_MSPI_SlaveEnable(TRUE);
450 // send write address
451 MDrv_MSPI_Write(Wdata,sizeof(Wdata));
452 MDrv_MSPI_SlaveEnable(FALSE);
453
454 return bRet;
455 }
456
_MSB201X_I2C_CH_Reset(MS_U8 devID,MS_U8 ch_num)457 static MS_BOOL _MSB201X_I2C_CH_Reset(MS_U8 devID, MS_U8 ch_num)
458 {
459 MS_BOOL bRet=TRUE;
460 //MAPI_U8 addr[4] = {0x00, 0x00, 0x00, 0x00};
461 MS_U8 u8data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
462 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
463
464 #ifdef MS_DEBUG
465 printf("[MSB201X][beg]I2C_CH_Reset, CH=0x%x\n",ch_num);
466 #endif
467
468 if(E_MSB201X_SPI_READ_WRITE == pDemod->DSP_ReadWrite_Mode)
469 {
470 return TRUE;
471 }
472
473 //DMD_LOCK_REG_RW();
474
475 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
476 //u8data[0] = 0x53;
477 //bRet &= (*_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(E_DMD_MSB201X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8data);
478 if (pDemod->bDemodRest)
479 {
480 pDemod->bDemodRest = FALSE;
481 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
482 u8data[0] = 0x53;
483 // Don't check Ack because this passward only ack one time for the first time.
484 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8data);
485 }
486 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_
487 u8data[0] = 0x71;
488 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
489
490 // 8'hb2(SRID)->8,h81(CMD) //TV.n_iic_sel_b0
491 u8data[0] = ((ch_num & 0x01) != 0)? 0x81 : 0x80;
492 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
493
494 // 8'hb2(SRID)->8,h83(CMD) //TV.n_iic_sel_b1
495 u8data[0] = ((ch_num & 0x02) != 0)? 0x83 : 0x82;
496 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
497
498 // 8'hb2(SRID)->8,h84(CMD) //TV.n_iic_sel_b2
499 u8data[0] = ((ch_num & 0x04) != 0)? 0x85 : 0x84;
500 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
501
502 // 8'hb2(SRID)->8,h53(CMD) //TV.n_iic_ad_byte_en2, 32bit read/write
503 u8data[0] = 0x53;
504 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
505
506 // 8'hb2(SRID)->8,h7f(CMD) //TV.n_iic_sel_use_cfg
507 u8data[0] = 0x7f;
508 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
509
510 /*
511 // 8'hb2(SRID)->8,h35(CMD) //TV.n_iic_use
512 data[0] = 0x35;
513 iptr->WriteBytes(0, NULL, 1, data);
514
515 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_Re-shape
516 data[0] = 0x71;
517 iptr->WriteBytes(0, NULL, 1, data);
518 */
519 //DMD_UNLOCK_REG_RW();
520 #ifdef MS_DEBUG
521 DBG_DEMOD_LOAD_I2C(printf("[MSB201X][end]I2C_CH_Reset, CH=0x%x\n",ch_num));
522 #endif
523 return bRet;
524 }
525
_MDrv_DMD_MSB201X_GetReg(MS_U8 devID,MS_U32 u32Addr,MS_U8 * pu8Data)526 static MS_BOOL _MDrv_DMD_MSB201X_GetReg(MS_U8 devID, MS_U32 u32Addr, MS_U8 *pu8Data) //koln
527 {
528 MS_BOOL bRet=TRUE;
529 MS_U8 u8MsbData[6];
530 MS_U16 u16Addr=0;
531 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
532
533 if(E_MSB201X_SPI_READ_WRITE == pDemod->DSP_ReadWrite_Mode)
534 {
535 if((u32Addr&0x100000)==0x100000)
536 {
537 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x10);
538 }
539 else
540 {
541 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x00);
542 }
543 u16Addr=(MS_U16)u32Addr;
544 return MDrv_DMD_SSPI_RIU_Read8(u16Addr, pu8Data);
545 }
546
547 u8MsbData[0] = 0x10;
548 u8MsbData[1] = 0x00;
549 u8MsbData[2] = (u32Addr>>16)&0xff;
550 u8MsbData[3] = (u32Addr >> 8) &0xff;
551 u8MsbData[4] = u32Addr & 0xff;
552
553 u8MsbData[0] = 0x35;
554 (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
555
556 u8MsbData[0] = 0x10;
557 (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
558 bRet=(pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, pu8Data);
559
560 u8MsbData[0] = 0x34;
561
562 (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
563 #ifdef MS_DEBUG
564 if (eDMD_MSB201X_DbgLevel >= E_DMD_MSB201X_DBGLV_DEBUG)
565 {
566 printf("_MDrv_DMD_MSB201X_GetReg %x %x\n", u16Addr, *pu8Data);
567 }
568 #endif
569
570 return bRet;
571 }
572
MDrv_DMD_MSB201X_GetReg(MS_U8 devID,MS_U32 u32Addr,MS_U8 * pu8Data)573 MS_BOOL MDrv_DMD_MSB201X_GetReg(MS_U8 devID, MS_U32 u32Addr, MS_U8 *pu8Data) //koln
574 {
575 MS_BOOL bRet=TRUE;
576 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
577
578 DMD_LOCK();
579 bRet = _MDrv_DMD_MSB201X_GetReg(devID, u32Addr, pu8Data);
580 DMD_UNLOCK();
581
582 return bRet;
583 }
584
_MDrv_DMD_MSB201X_SetReg(MS_U8 devID,MS_U32 u32Addr,MS_U8 u8Data)585 static MS_BOOL _MDrv_DMD_MSB201X_SetReg(MS_U8 devID, MS_U32 u32Addr, MS_U8 u8Data) //koln
586 {
587 MS_BOOL bRet=TRUE;
588 MS_U8 u8MsbData[6];
589 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
590 MS_U16 u16Addr;
591
592 if(E_MSB201X_SPI_READ_WRITE == pDemod->DSP_ReadWrite_Mode)
593 {
594 if((u32Addr&0x100000)==0x100000)
595 {
596 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x10);
597 }
598 else
599 {
600 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x00);
601 }
602
603 u16Addr=(MS_U16)u32Addr;
604 return MDrv_DMD_SSPI_RIU_Write8(u16Addr, u8Data);
605 }
606 u8MsbData[0] = 0x10;
607 u8MsbData[1] = 0x00;
608 u8MsbData[2] = (u32Addr>>16)&0xff;
609 u8MsbData[3] = (u32Addr >> 8) &0xff;
610 u8MsbData[4] = u32Addr &0xff;
611 u8MsbData[5] = u8Data;
612
613 u8MsbData[0] = 0x35;
614 (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
615
616 u8MsbData[0] = 0x10;
617 (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
618
619 u8MsbData[0] = 0x34;
620 bRet=(pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
621 return bRet;
622 }
623
MDrv_DMD_MSB201X_SetReg(MS_U8 devID,MS_U32 u32Addr,MS_U8 u8Data)624 MS_BOOL MDrv_DMD_MSB201X_SetReg(MS_U8 devID, MS_U32 u32Addr, MS_U8 u8Data) //koln
625 {
626 MS_BOOL bRet=TRUE;
627 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
628
629 DMD_LOCK();
630 bRet = _MDrv_DMD_MSB201X_SetReg(devID, u32Addr, u8Data);
631 DMD_UNLOCK();
632
633 return bRet;
634 }
635
_MDrv_DMD_MSB201X_SetRegs(MS_U8 devID,MS_U32 u32Addr,MS_U8 * u8pData,MS_U16 data_size)636 static MS_BOOL _MDrv_DMD_MSB201X_SetRegs(MS_U8 devID, MS_U32 u32Addr, MS_U8* u8pData, MS_U16 data_size) //koln
637 {
638 MS_BOOL bRet=TRUE;
639 MS_U8 u8MsbDataValue[LOAD_CODE_I2C_BLOCK_NUM + 5];
640 MS_U16 idx = 0;
641 MS_U16 u16Addr=0;
642 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
643
644 if(E_MSB201X_SPI_READ_WRITE == pDemod->DSP_ReadWrite_Mode)
645 {
646 if((u32Addr&0x100000)==0x100000)
647 {
648 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x10);
649 }
650 else
651 {
652 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x00);
653 }
654 u16Addr=(MS_U16)u32Addr;
655 for(idx = 0; idx < data_size; idx++)
656 {
657 MDrv_DMD_SSPI_RIU_Write8(u16Addr + idx, *(u8pData + idx));
658 }
659 return TRUE;
660 }
661
662 u8MsbDataValue[0] = 0x10;
663 u8MsbDataValue[1] = 0x00;
664 u8MsbDataValue[2] = (u32Addr>>16)& 0xff;
665 u8MsbDataValue[3] = (u32Addr >> 8) &0xff;
666 u8MsbDataValue[4] = u32Addr & 0xff;
667 // u8MsbDataValue[5] = 0x00;
668
669 for(idx = 0; idx < data_size ; idx++)
670 {
671 u8MsbDataValue[5+idx] = u8pData[idx];
672 }
673
674 u8MsbDataValue[0] = 0x35;
675 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbDataValue);
676
677 u8MsbDataValue[0] = 0x10;
678 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5 + data_size, u8MsbDataValue);
679
680 u8MsbDataValue[0] = 0x34;
681 bRet &= (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access)(devID, E_DMD_MSB201X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbDataValue);
682
683 return bRet;
684 }
685
MDrv_DMD_MSB201X_SetRegs(MS_U8 devID,MS_U32 u32Addr,MS_U8 * u8pData,MS_U16 data_size)686 MS_BOOL MDrv_DMD_MSB201X_SetRegs(MS_U8 devID, MS_U32 u32Addr, MS_U8* u8pData, MS_U16 data_size) //Koln
687 {
688 MS_BOOL bRet=TRUE;
689 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
690
691 DMD_LOCK();
692 bRet = _MDrv_DMD_MSB201X_SetRegs(devID, u32Addr, u8pData, data_size);
693 DMD_UNLOCK();
694
695 return bRet;
696 }
697
_MDrv_DMD_MSB201X_SetReg2Bytes(MS_U8 devID,MS_U32 u32Addr,MS_U16 u16Data)698 static MS_BOOL _MDrv_DMD_MSB201X_SetReg2Bytes(MS_U8 devID, MS_U32 u32Addr, MS_U16 u16Data) //koln
699 {
700 MS_BOOL bRet=TRUE;
701 MS_U16 u16Addr=0;
702 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
703
704 if(E_MSB201X_SPI_READ_WRITE == pDemod->DSP_ReadWrite_Mode)
705 {
706
707 if((u32Addr&0x100000)==0x100000)
708 {
709 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x10);
710 }
711 else
712 {
713 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x00);
714 }
715
716 u16Addr=(MS_U16)u32Addr;
717
718 MDrv_DMD_SSPI_RIU_Write8(u16Addr, u16Data);
719 return MDrv_DMD_SSPI_RIU_Write8(u16Addr+1, (u16Data>>8));
720 }
721
722 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32Addr, (MS_U8)u16Data&0x00ff);
723 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
724
725 return bRet;
726 }
727
MDrv_DMD_MSB201X_SetReg2Bytes(MS_U8 devID,MS_U32 u32Addr,MS_U16 u16Data)728 MS_BOOL MDrv_DMD_MSB201X_SetReg2Bytes(MS_U8 devID, MS_U32 u32Addr, MS_U16 u16Data) //koln
729 {
730 MS_BOOL bRet=TRUE;
731 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
732 DMD_LOCK();
733
734
735
736 bRet = _MDrv_DMD_MSB201X_SetReg2Bytes(devID, u32Addr, u16Data);
737 DMD_UNLOCK();
738
739 return bRet;
740 }
741
_MDrv_DMD_MSB201X_GetDSPReg(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 u16Addr,MS_U8 * pu8Data)742 MS_BOOL _MDrv_DMD_MSB201X_GetDSPReg(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 u16Addr, MS_U8 *pu8Data)
743 {
744 MS_BOOL bRet=TRUE;
745 MS_U8 u8Cntl = 0x00;
746 MS_U16 u16Cntr = 0x00;
747 MS_U32 u32REG_MB_CNTL, u32REG_MB_ADDR_L, u32REG_MB_ADDR_H, u32REG_MB_DATA, u32REG_EXT_INTR;
748
749 switch(u8DemodIndex)
750 {
751 case 0:
752 u32REG_MB_CNTL = REG_DMD0_MB_CNTL;
753 u32REG_MB_ADDR_L = REG_DMD0_MB_ADDR_L;
754 u32REG_MB_ADDR_H = REG_DMD0_MB_ADDR_H;
755 u32REG_MB_DATA = REG_DMD0_MB_DATA;
756 u32REG_EXT_INTR = (REG_MCU51_INTR + (0x41)*2+1);
757 break;
758 case 1:
759 u32REG_MB_CNTL = REG_DMD1_MB_CNTL;
760 u32REG_MB_ADDR_L = REG_DMD1_MB_ADDR_L;
761 u32REG_MB_ADDR_H = REG_DMD1_MB_ADDR_H;
762 u32REG_MB_DATA = REG_DMD1_MB_DATA;
763 u32REG_EXT_INTR = (REG_MCU51_INTR + (0x51)*2+1);
764 break;
765 /*
766 case 2:
767 u16REG_MB_CNTL = REG_DMD2_MB_CNTL;
768 u16REG_MB_ADDR_L = REG_DMD2_MB_ADDR_L;
769 u16REG_MB_ADDR_H = REG_DMD2_MB_ADDR_H;
770 u16REG_MB_DATA = REG_DMD2_MB_DATA;
771 u16REG_EXT_INTR = (REG_MCU51_INTR + (0x60)*2);
772 break;
773 case 3:
774 u16REG_MB_CNTL = REG_DMD3_MB_CNTL;
775 u16REG_MB_ADDR_L = REG_DMD3_MB_ADDR_L;
776 u16REG_MB_ADDR_H = REG_DMD3_MB_ADDR_H;
777 u16REG_MB_DATA = REG_DMD3_MB_DATA;
778 u16REG_EXT_INTR = (REG_MCU51_INTR + (0x70)*2);
779 break;
780 */
781 default:
782 u32REG_MB_CNTL = REG_DMD0_MB_CNTL;
783 u32REG_MB_ADDR_L = REG_DMD0_MB_ADDR_L;
784 u32REG_MB_ADDR_H = REG_DMD0_MB_ADDR_H;
785 u32REG_MB_DATA = REG_DMD0_MB_DATA;
786 u32REG_EXT_INTR = (REG_MCU51_INTR + (0x40)*2+1);
787 break;
788 }
789
790 // Write into MB
791 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_MB_ADDR_H, (MS_U8)(u16Addr >> 8));
792 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_MB_ADDR_L, (MS_U8)(u16Addr));
793 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_MB_CNTL, 0x03);
794 // assert interrupt to DMD MCU51
795 bRet &= _MDrv_DMD_MSB201X_GetReg(devID, u32REG_EXT_INTR , &u8Cntl);
796 u8Cntl |= 0x02; //assert interrupt bit
797 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_EXT_INTR , u8Cntl);
798
799 do
800 {
801 bRet &= _MDrv_DMD_MSB201X_GetReg(devID, u32REG_MB_CNTL, &u8Cntl);
802 if (u16Cntr++ > 0x7ff)
803 {
804 //#ifdef MS_DEBUG
805 //if (eDMD_MSB201X_DbgLevel >= E_DMD_MSB201X_DBGLV_DEBUG)
806 {
807 printf("MSB201X_MB_READ_FAILURE\n");
808 }
809 //#endif
810 return FALSE;
811 }
812 }
813 while(u8Cntl != 0xff);
814
815 bRet &= _MDrv_DMD_MSB201X_GetReg(devID, u32REG_MB_DATA, pu8Data);
816
817
818 bRet &= _MDrv_DMD_MSB201X_GetReg(devID, u32REG_EXT_INTR , &u8Cntl);
819 u8Cntl &= (~0x02); //deassert interrupt bit
820 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_EXT_INTR , u8Cntl);
821
822 return bRet;
823 }
824
825 //1 means bypass en, 0 means bypass disable
MDrv_DMD_MSB201X_I2C_BYPASS(MS_U8 devID,MS_U8 bypass_en)826 MS_BOOL MDrv_DMD_MSB201X_I2C_BYPASS(MS_U8 devID,MS_U8 bypass_en)
827 {
828 MS_BOOL bRet=TRUE;
829 MS_U8 u8Data=0;
830 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
831 _MSB201X_I2C_CH_Reset(devID, 3);
832
833 DMD_LOCK();
834 bRet &= _MDrv_DMD_MSB201X_GetReg(devID, 0x100910, &u8Data);
835
836 if(bypass_en==1)
837 {
838 u8Data|=0x10;
839 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, 0x100910, u8Data);
840 }
841 else
842 {
843 u8Data&=(~0x10);
844 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, 0x100910, u8Data);
845 }
846 DMD_UNLOCK();
847
848 return bRet;
849 }
850
851
MDrv_DMD_MSB201X_GetDSPReg(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 u16Addr,MS_U8 * pu8Data)852 MS_BOOL MDrv_DMD_MSB201X_GetDSPReg(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 u16Addr, MS_U8 *pu8Data)
853 {
854 MS_BOOL bRet=TRUE;
855 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
856 _MSB201X_I2C_CH_Reset(devID, 3);
857
858
859
860 DMD_LOCK();
861 bRet = _MDrv_DMD_MSB201X_GetDSPReg(devID, u8DemodIndex, u16Addr, pu8Data);
862 DMD_UNLOCK();
863
864 return bRet;
865 }
866
_MDrv_DMD_MSB201X_SetDSPReg(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 u16Addr,MS_U8 u8Data)867 MS_BOOL _MDrv_DMD_MSB201X_SetDSPReg(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 u16Addr, MS_U8 u8Data)
868 {
869 MS_BOOL bRet=TRUE;
870 MS_U8 u8Cntl = 0x00;
871 MS_U16 u16Cntr = 0x00;
872
873 MS_U32 u32REG_MB_CNTL, u32REG_MB_ADDR_L, u32REG_MB_ADDR_H, u32REG_MB_DATA, u32REG_EXT_INTR;
874
875 switch(u8DemodIndex)
876 {
877 case 0:
878 u32REG_MB_CNTL = REG_DMD0_MB_CNTL;
879 u32REG_MB_ADDR_L = REG_DMD0_MB_ADDR_L;
880 u32REG_MB_ADDR_H = REG_DMD0_MB_ADDR_H;
881 u32REG_MB_DATA = REG_DMD0_MB_DATA;
882 u32REG_EXT_INTR = (REG_MCU51_INTR + (0x41)*2+1);
883 break;
884 case 1:
885 u32REG_MB_CNTL = REG_DMD1_MB_CNTL;
886 u32REG_MB_ADDR_L = REG_DMD1_MB_ADDR_L;
887 u32REG_MB_ADDR_H = REG_DMD1_MB_ADDR_H;
888 u32REG_MB_DATA = REG_DMD1_MB_DATA;
889 u32REG_EXT_INTR = (REG_MCU51_INTR + (0x51)*2+1);
890 break;
891 /*
892 case 2:
893 u16REG_MB_CNTL = REG_DMD2_MB_CNTL;
894 u16REG_MB_ADDR_L = REG_DMD2_MB_ADDR_L;
895 u16REG_MB_ADDR_H = REG_DMD2_MB_ADDR_H;
896 u16REG_MB_DATA = REG_DMD2_MB_DATA;
897 u16REG_EXT_INTR = (REG_MCU51_INTR + (0x60)*2);
898 break;
899 case 3:
900 u16REG_MB_CNTL = REG_DMD3_MB_CNTL;
901 u16REG_MB_ADDR_L = REG_DMD3_MB_ADDR_L;
902 u16REG_MB_ADDR_H = REG_DMD3_MB_ADDR_H;
903 u16REG_MB_DATA = REG_DMD3_MB_DATA;
904 u16REG_EXT_INTR = (REG_MCU51_INTR + (0x70)*2);
905 break;
906 */
907 default:
908 u32REG_MB_CNTL = REG_DMD0_MB_CNTL;
909 u32REG_MB_ADDR_L = REG_DMD0_MB_ADDR_L;
910 u32REG_MB_ADDR_H = REG_DMD0_MB_ADDR_H;
911 u32REG_MB_DATA = REG_DMD0_MB_DATA;
912 u32REG_EXT_INTR = (REG_MCU51_INTR + (0x41)*2+1);
913 break;
914 }
915
916 _MSB201X_I2C_CH_Reset(devID, 3);
917 // Write into MB
918 // pDemod->DSP_ReadWrite_Mode = E_MSB201X_SPI_READ_WRITE;
919 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_MB_DATA, u8Data);
920
921 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_MB_ADDR_H, (MS_U8)(u16Addr >> 8));
922
923 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_MB_ADDR_L, (MS_U8)(u16Addr));
924
925 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_MB_CNTL, 0x04);
926 // assert interrupt to DMD MCU51
927 bRet &= _MDrv_DMD_MSB201X_GetReg(devID, u32REG_EXT_INTR , &u8Cntl);
928 u8Cntl |= 0x02; //assert interrupt bit
929 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_EXT_INTR , u8Cntl);
930
931 u8Cntl &= (~0x02); //deassert interrupt bit
932 bRet &= _MDrv_DMD_MSB201X_SetReg(devID, u32REG_EXT_INTR , u8Cntl);
933
934 do
935 {
936 bRet &= _MDrv_DMD_MSB201X_GetReg(devID, u32REG_MB_CNTL, &u8Cntl);
937 if (u16Cntr++ > 0x7ff)
938 {
939 //#ifdef MS_DEBUG
940 //if (eDMD_MSB201X_DbgLevel >= E_DMD_MSB201X_DBGLV_DEBUG)
941 {
942 printf("MSB201X_MB_WRITE_FAILURE\n");
943 }
944 //#endif
945 return false;
946 }
947 }
948 while(u8Cntl != 0xff);
949
950
951
952
953 return bRet;
954 }
955
MDrv_DMD_MSB201X_SetDSPReg(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 u16Addr,MS_U8 u8Data)956 MS_BOOL MDrv_DMD_MSB201X_SetDSPReg(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 u16Addr, MS_U8 u8Data)
957 {
958 MS_BOOL bRet=TRUE;
959 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
960
961 DMD_LOCK();
962 bRet = _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, u16Addr, u8Data);
963 DMD_UNLOCK();
964
965 return bRet;
966 }
967
_MSB201X_Delay_Task(MS_U32 task_num)968 static MS_BOOL _MSB201X_Delay_Task(MS_U32 task_num)
969 {
970 unsigned int n = 0;
971
972 while(n < task_num)
973 {
974 n++;
975 }
976 return TRUE;
977 }
978
_MDrv_DMD_MSB201X_Version(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 * ver)979 MS_BOOL _MDrv_DMD_MSB201X_Version(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 *ver)
980 {
981
982 MS_U8 status = true;
983 MS_U8 tmp = 0;
984 MS_U16 u16_Demod_Version;
985
986 _MSB201X_I2C_CH_Reset(devID, 5);
987 status &= _MDrv_DMD_MSB201X_GetReg(devID, TOP_REG_BASE + 0xC1, &tmp);
988 u16_Demod_Version = tmp;
989 status &= _MDrv_DMD_MSB201X_GetReg(devID, TOP_REG_BASE + 0xC2, &tmp);
990 u16_Demod_Version = u16_Demod_Version<<8|tmp;
991 *ver = u16_Demod_Version;
992
993 return status;
994 }
995
996 //new TS pad switching adding
_MDrv_DMD_MSB201X_Set_TSOut(MS_U8 devID,sDMD_MSB201X_TS_Param * pDMD_MSB201X_TS_Param)997 MS_BOOL _MDrv_DMD_MSB201X_Set_TSOut(MS_U8 devID, sDMD_MSB201X_TS_Param *pDMD_MSB201X_TS_Param)
998 {
999 MS_U8 u8Data = 0, u8Data_tmp = 0, idx = 0;
1000
1001 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
1002
1003 if(TRUE == pDemod->bDMD_MSB201X_TS_Param_Init_Done)
1004 {
1005 if(pDMD_MSB201X_TS_Param->eTSMode != pDemod->sDMD_MSB201X_TS_Param.eTSMode)
1006 pDemod->bDMD_MSB201X_TS_Param_Init_Done = FALSE;
1007 }
1008
1009 _MSB201X_I2C_CH_Reset(devID, 3);
1010
1011 // reg_swrst_ts_mux
1012 _MDrv_DMD_MSB201X_SetReg(devID, 0x100B00 + (0x70)*2, 0x00);
1013
1014
1015 // Set clock
1016 if(E_DMD_MSB201X_TS_CLK_MAX == pDMD_MSB201X_TS_Param->eTSClk)
1017 {
1018 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x06);
1019 }
1020 else //TS clock setting using AP parameter //later
1021 {
1022 switch(pDMD_MSB201X_TS_Param->eTSClk)
1023 {
1024 case E_DMD_MSB201X_TS_CLK_216MHz :
1025 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x00);
1026 break;
1027 case E_DMD_MSB201X_TS_CLK_108MHz :
1028 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x01);
1029 break;
1030 case E_DMD_MSB201X_TS_CLK_72MHz :
1031 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x02);
1032 break;
1033 case E_DMD_MSB201X_TS_CLK_54MHz :
1034 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x03);
1035 break;
1036 case E_DMD_MSB201X_TS_CLK_43p2MHz:
1037 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x04);
1038 break;
1039 case E_DMD_MSB201X_TS_CLK_36MHz :
1040 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x05);
1041 break;
1042 case E_DMD_MSB201X_TS_CLK_30p8MHz:
1043 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x06);
1044 break;
1045 case E_DMD_MSB201X_TS_CLK_27MHz:
1046 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x07);
1047 break;
1048 case E_DMD_MSB201X_TS_CLK_24MHz :
1049 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x08);
1050 break;
1051 case E_DMD_MSB201X_TS_CLK_21p6MHz:
1052 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x09);
1053 break;
1054 case E_DMD_MSB201X_TS_CLK_19p6MHz :
1055 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x0a);
1056 break;
1057 case E_DMD_MSB201X_TS_CLK_18MHz :
1058 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x0b);
1059 break;
1060 case E_DMD_MSB201X_TS_CLK_16p6MHz :
1061 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x0c);
1062 break;
1063 case E_DMD_MSB201X_TS_CLK_15p4MHz :
1064 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x0d);
1065 break;
1066 case E_DMD_MSB201X_TS_CLK_14p4MHz :
1067 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x0e);
1068 break;
1069 case E_DMD_MSB201X_TS_CLK_13p5MHz :
1070 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x0f);
1071 break;
1072 default:
1073 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x06);
1074 break;
1075 }
1076
1077 //_MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 + 1, 0x06);
1078 }
1079
1080
1081 //need to clear this to output TS normally
1082 _MDrv_DMD_MSB201X_SetReg(devID,0x103100+(0x02)*2+1,0x00);
1083
1084 if(FALSE == pDemod->bDMD_MSB201X_TS_Param_Init_Done)
1085 {
1086 memcpy(&pDemod->sDMD_MSB201X_TS_Param, pDMD_MSB201X_TS_Param, sizeof(sDMD_MSB201X_TS_Param));
1087
1088 switch(pDMD_MSB201X_TS_Param->eTSMode)
1089 {
1090 case E_DMD_MSB201X_PARALLEL:
1091
1092
1093 // Out mode : 1 => Normal mode, 0 => Gating mode.
1094 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2, 0x10);
1095 //_MDrv_DMD_MSR1742_GetReg(devID, 0x0900 + (0x12)*2, &u8Data);
1096 //u8Data |= _BIT4;
1097 //_MDrv_DMD_MSR1742_SetReg(devID, 0x0900 + (0x12)*2, u8Data);
1098
1099 // Clock inverse
1100 _MDrv_DMD_MSB201X_GetReg(devID, 0x100900 + (0x12)*2, &u8Data);
1101 if(TRUE == pDMD_MSB201X_TS_Param->bCLKInverse)
1102 {
1103 u8Data |= _BIT5;
1104 }
1105 else
1106 {
1107 u8Data &= (~_BIT5);
1108 }
1109 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2, u8Data);
1110
1111 // reg_ckg_ts_mux
1112 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x1e) * 2, 0x4444);
1113
1114 // reg_ckg_ts_*
1115 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x23) * 2, 0x0000);
1116
1117 // all pad in
1118 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x28) * 2, 0x0000);
1119
1120 // Enable TS
1121 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x2e) * 2, 0x0103);
1122
1123 // Disable SSPI
1124 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x3b) * 2, 0x0000);
1125
1126
1127
1128 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2 + 1, 0x00);
1129 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, 0xff);
1130
1131 // reg_client_mask
1132 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x06) * 2, 0x0020);
1133
1134 // reg_ts_mux_swrst
1135 u8Data = 0xf0;
1136 for(idx = 0; idx<DEMOD_MAX_CHANNEL; idx++)
1137 {
1138 if(FALSE == pDMD_MSB201X_TS_Param->bEnable[idx])
1139 {
1140 u8Data_tmp = 0x01;
1141 u8Data |= (u8Data_tmp << idx);
1142 }
1143 else
1144 {
1145 u8Data_tmp = 0x01;
1146 u8Data &= (~(u8Data_tmp << idx));
1147 }
1148 }
1149 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, u8Data);
1150
1151 break;
1152 case E_DMD_MSB201X_3_WIRE_REMUX2TS0:
1153
1154 break;
1155 case E_DMD_MSB201X_3_WIRE_REMUX2TS1:
1156
1157 break;
1158 case E_DMD_MSB201X_3_WIRE_REMUX2TS2:
1159
1160 break;
1161 case E_DMD_MSB201X_3_WIRE_REMUX2TS3:
1162
1163 break;
1164 case E_DMD_MSB201X_3_WIRE_REMUX2TS4:
1165
1166 break;
1167 case E_DMD_MSB201X_3_WIRE_REMUX2TS5:
1168
1169 break;
1170 case E_DMD_MSB201X_3_WIRE_REMUX2TS6:
1171
1172 break;
1173 case E_DMD_MSB201X_3_WIRE_REMUX2TS7:
1174
1175 break;
1176 case E_DMD_MSB201X_3_WIRE_DMD0_TS0_DMD1_TS1:
1177 // Set clock
1178 //_MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x12)*2 + 1, 0x02);
1179
1180 // Out mode : 1 => Normal mode, 0 => Gating mode.
1181 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x12)*2, 0x00);
1182 //_MDrv_DMD_MSR1742_GetReg(devID, 0x0900 + (0x12)*2, &u8Data);
1183 //u8Data &= (~_BIT4);
1184 //_MDrv_DMD_MSR1742_SetReg(devID, 0x0900 + (0x12)*2, u8Data);
1185
1186 // Clock inverse
1187 _MDrv_DMD_MSB201X_GetReg(devID, 0x100900 + (0x12)*2, &u8Data);
1188 if(TRUE == pDMD_MSB201X_TS_Param->bCLKInverse)
1189 {
1190 u8Data |= _BIT5;
1191 }
1192 else
1193 {
1194 u8Data &= (~_BIT5);
1195 }
1196 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2, u8Data);
1197
1198 // reg_ckg_ts_mux
1199 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x1e) * 2, 0x4444);
1200
1201 // reg_ckg_ts_*
1202 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x23) * 2, 0x0000);
1203
1204 // all pad in
1205 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x28) * 2, 0x0000);
1206
1207 // Enable TS
1208 //wait for modified(to achieve pad compatible)
1209 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x29) * 2, 0x0000);
1210 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x2a) * 2, 0x0000);
1211 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x2d) * 2, 0x0003);
1212 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x2e) * 2, 0x0000);
1213
1214 // Disable SSPI
1215 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x3b) * 2, 0x0000);
1216
1217 // reg_ckg_ts_*
1218 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x23) * 2, 0x8888);
1219
1220 // reg_swrst_ts_mux
1221 _MDrv_DMD_MSB201X_SetReg(devID, 0x100B00 + (0x70)*2, 0x00);
1222
1223 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2 + 1, 0x00);
1224 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, 0xff);
1225
1226 // reg_serial_order
1227 u8Data = 0x00;
1228 for(idx = 0; idx<DEMOD_MAX_CHANNEL; idx++)
1229 {
1230 if(TRUE == pDMD_MSB201X_TS_Param->bEnable[idx])
1231 {
1232 u8Data_tmp = 0x01;
1233 u8Data |= (u8Data_tmp << (idx+1));
1234 }
1235 else
1236 {
1237 u8Data_tmp = 0x01;
1238 u8Data &= (~(u8Data_tmp << (idx+1)));
1239 }
1240 }
1241 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x01)*2, u8Data);
1242
1243 // reg_ts_mux_swrst
1244 u8Data = 0x0f;
1245 for(idx = 0; idx<DEMOD_MAX_CHANNEL; idx++)
1246 {
1247 if(FALSE == pDMD_MSB201X_TS_Param->bEnable[idx])
1248 {
1249 u8Data_tmp = 0x01;
1250 u8Data |= (u8Data_tmp << (idx+4));
1251 }
1252 else
1253 {
1254 u8Data_tmp = 0x01;
1255 u8Data &= (~(u8Data_tmp << (idx+4)));
1256 }
1257 }
1258 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, u8Data);
1259
1260 break;
1261 case E_DMD_MSB201X_3_WIRE_DMD0_TS1_DMD1_TS0:
1262
1263 break;
1264 case E_DMD_MSB201X_4_WIRE_REMUX2TS0:
1265
1266 break;
1267 case E_DMD_MSB201X_4_WIRE_REMUX2TS1:
1268
1269 break;
1270 case E_DMD_MSB201X_4_WIRE_REMUX2TS2:
1271
1272 break;
1273 case E_DMD_MSB201X_4_WIRE_REMUX2TS3:
1274
1275 break;
1276 case E_DMD_MSB201X_4_WIRE_REMUX2TS4:
1277
1278 break;
1279 case E_DMD_MSB201X_4_WIRE_REMUX2TS5:
1280
1281 break;
1282 case E_DMD_MSB201X_4_WIRE_DMD0_TS0_DMD1_TS1:
1283
1284 break;
1285 case E_DMD_MSB201X_4_WIRE_DMD0_TS1_DMD1_TS0:
1286
1287 break;
1288 default :
1289
1290 break;
1291 }
1292
1293 pDemod->bDMD_MSB201X_TS_Param_Init_Done = TRUE;
1294
1295 }
1296
1297 // Check reg_ts_mux_swrst
1298 _MDrv_DMD_MSB201X_GetReg(devID, 0x100B00 + (0x70)*2, &u8Data);
1299 if((u8Data & 0x01) == 0x01)
1300 {
1301 _MDrv_DMD_MSB201X_SetReg(devID, 0x100B00 + (0x70)*2, 0x00);
1302 }
1303
1304
1305 switch(pDemod->sDMD_MSB201X_TS_Param.eTSDrv)
1306 {
1307 case E_DMD_MSB201X_TS_DRVING_LO:
1308 //set to high driving
1309 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2C)*2, 0x00);
1310 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2C)*2+1, 0x00);
1311 break;
1312 case E_DMD_MSB201X_TS_DRVING_HI:
1313 //set to high driving
1314 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2C)*2, 0xff);
1315 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2C)*2+1, 0xff);
1316 break;
1317 case E_DMD_MSB201X_TS_DRVING_MAX:
1318 //set to high driving
1319 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2C)*2, 0xff);
1320 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2C)*2+1, 0xff);
1321 break;
1322 }
1323
1324
1325
1326 if(TRUE == pDemod->bDMD_MSB201X_TS_Param_Init_Done)
1327 {
1328 //if(pDMD_MSR1742_InitData->bCLKInverse != pDemod->sDMD_MSR1742_TS_Param.bCLKInverse)
1329
1330 }
1331
1332 return TRUE;
1333 }
1334
_MDrv_DMD_MSB201X_CfgExtHeader(MS_U8 devID,MS_U8 u8DemodIndex,sDMD_MSB201X_extHeader * pDMD_MSB201X_extHeader_Param)1335 MS_BOOL _MDrv_DMD_MSB201X_CfgExtHeader(MS_U8 devID, MS_U8 u8DemodIndex, sDMD_MSB201X_extHeader *pDMD_MSB201X_extHeader_Param)
1336 {
1337 MS_U8 u8Data_h = 0, u8Data_l = 0, u8Data = 0, idx = 0;
1338 MS_U16 u16Data = 0;
1339 MS_U32 u32HeaderReg = 0;
1340 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
1341
1342 _MSB201X_I2C_CH_Reset(devID, 3);
1343
1344 // Check reg_ts_mux_swrst
1345 _MDrv_DMD_MSB201X_GetReg(devID, 0x100B00 + (0x70)*2, &u8Data);
1346 if((u8Data & 0x01) == 0x01)
1347 {
1348 _MDrv_DMD_MSB201X_SetReg(devID, 0x100B00 + (0x70)*2, 0x00);
1349 }
1350
1351 // Keep original swrst settings
1352 _MDrv_DMD_MSB201X_GetReg(devID, 0x103100 + (0x00)*2 + 1, &u8Data_h);
1353 u16Data = (u8Data_h & 0x0f);
1354 _MDrv_DMD_MSB201X_GetReg(devID, 0x103100 + (0x00)*2, &u8Data_l);
1355 u16Data = (u16Data << 8) | u8Data_l;
1356
1357
1358
1359
1360 #ifdef MS_DEBUG
1361 printf("===_MDrv_DMD_MSR1742_CfgExtHeader=== Original swrst = 0x%x\n", u16Data);
1362 #endif
1363
1364 if(FALSE == pDMD_MSB201X_extHeader_Param->bEnable)
1365 {
1366 // Disable ExtHeader
1367 // Clear bit 10 and 11
1368 u16Data &= 0x03ff;
1369
1370 // Restart TS
1371 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00) * 2, 0x0fff);
1372 MsOS_DelayTask(1);
1373 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2 + 1, ((u16Data & 0x0f00)>>8));
1374 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, (u16Data & 0x00ff));
1375
1376 #ifdef MS_DEBUG
1377 printf("===Enable FALSE===\n");
1378 printf("===_MDrv_DMD_MSB201X_CfgExtHeader=== swrst = 0x%x\n", u16Data);
1379 #endif
1380
1381 return TRUE;
1382 }
1383 else
1384 {
1385 // Set extend header length
1386 //if(pDemod->sDMD_MSR1742_extHeader_Param.u8HeaderSize != pDMD_MSR1742_extHeader_Param->u8HeaderSize)
1387 {
1388 u8Data = pDMD_MSB201X_extHeader_Param->u8HeaderSize;
1389 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x07)*2 + 1, ((u8Data - 1) & 0x0f));
1390
1391 #ifdef MS_DEBUG
1392 printf("===_MDrv_DMD_MSB201X_CfgExtHeader=== header size = %d\n", (int)u8Data);
1393 _MDrv_DMD_MSB201X_GetReg(devID, 0x103100 + (0x07)*2 + 1, &u8Data);
1394 printf("===Enable TRUE===\n");
1395 printf("===_MDrv_DMD_MSB201X_CfgExtHeader=== read header size = %d\n", (int)u8Data);
1396 #endif
1397 }
1398 /* Remove header size checking
1399 else
1400 {
1401 #if(HEADER_DBG)
1402 _MDrv_DMD_MSR1742_GetReg(devID, 0x2A00 + (0x07)*2 + 1, &u8Data);
1403 printf("===_MDrv_DMD_MSR1742_CfgExtHeader=== read header size = %d\n", (int)u8Data);
1404 printf("===Enable TRUE===\n");
1405 printf("===_MDrv_DMD_MSR1742_CfgExtHeader=== header size doesn't change! \n");
1406 #endif
1407 }
1408 */
1409
1410 // Set extend header list
1411 switch(u8DemodIndex)
1412 {
1413 case DEMOD0:
1414 u32HeaderReg = 0x103100 + (0x08)*2;
1415 break;
1416 case DEMOD1:
1417 u32HeaderReg = 0x103100 + (0x10)*2;
1418 break;
1419 /*
1420 case DEMOD2:
1421 u32HeaderReg = 0x2A00 + (0x18)*2;
1422 break;
1423 case DEMOD3:
1424 u32HeaderReg = 0x2A00 + (0x20)*2;
1425 break;
1426 */
1427 default :
1428 u32HeaderReg = 0x103100 + (0x08)*2;
1429 break;
1430 }
1431 for(idx = 0; idx < pDMD_MSB201X_extHeader_Param->u8HeaderSize; idx++)
1432 {
1433 _MDrv_DMD_MSB201X_SetReg(devID, u32HeaderReg + idx, *(pDMD_MSB201X_extHeader_Param->pHeaderPtr + idx));
1434
1435
1436 }
1437
1438 // Enable ExtHeader
1439 // Clear bit 10 and 11, then set bit 10 to add extend header
1440 u16Data &= 0x03ff;
1441 u16Data |= 0x0400;
1442
1443 // Restart TS
1444 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00) * 2, 0x0fff);
1445 MsOS_DelayTask(1);
1446 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2 + 1, ((u16Data & 0x0f00)>>8));
1447 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, (u16Data & 0x00ff));
1448
1449 #ifdef MS_DEBUG
1450 printf("===_MDrv_DMD_MSR1742_CfgExtHeader=== swrst = 0x%x \n", u16Data);
1451 printf("===Done===\n");
1452 #endif
1453
1454 // Save setting parameters for next time comparison
1455 memcpy(&pDemod->sDMD_MSB201X_extHeader_Param, pDMD_MSB201X_extHeader_Param, sizeof(sDMD_MSB201X_extHeader));
1456 }
1457
1458 return TRUE;
1459 }
1460
_MDrv_DMD_MSB201X_CfgCIHeader(MS_U8 devID,MS_U8 u8DemodIndex,sDMD_MSB201X_CIHeader * pDMD_MSB201X_CIHeader_Param)1461 MS_BOOL _MDrv_DMD_MSB201X_CfgCIHeader(MS_U8 devID, MS_U8 u8DemodIndex, sDMD_MSB201X_CIHeader *pDMD_MSB201X_CIHeader_Param)
1462 {
1463 MS_U8 u8Data_h = 0, u8Data_l = 0, u8Data = 0;
1464 MS_U16 u16Data = 0;
1465 MS_U32 u32HeaderReg = 0;
1466 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
1467
1468 _MSB201X_I2C_CH_Reset(devID, 3);
1469
1470 // Check reg_ts_mux_swrst
1471 _MDrv_DMD_MSB201X_GetReg(devID, 0x100B00 + (0x70)*2, &u8Data);
1472 if((u8Data & 0x01) == 0x01)
1473 {
1474 _MDrv_DMD_MSB201X_SetReg(devID, 0x100B00 + (0x70)*2, 0x00);
1475 }
1476
1477 // Keep original swrst settings
1478 _MDrv_DMD_MSB201X_GetReg(devID, 0x103100 + (0x00)*2 + 1, &u8Data_h);
1479 u16Data = (u8Data_h & 0x0f);
1480 _MDrv_DMD_MSB201X_GetReg(devID, 0x103100 + (0x00)*2, &u8Data_l);
1481 u16Data = (u16Data << 8) | u8Data_l;
1482
1483 if(FALSE == pDMD_MSB201X_CIHeader_Param->bEnable)
1484 {
1485 // Disable ExtHeader
1486 // Clear bit 10 and 11
1487 u16Data &= 0x03ff;
1488
1489 // Restart TS
1490 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00) * 2, 0x0fff);
1491 MsOS_DelayTask(1);
1492 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2 + 1, ((u16Data & 0x0f00)>>8));
1493 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, (u16Data & 0x00ff));
1494
1495 return TRUE;
1496 }
1497 else
1498 {
1499 // Set extend header list
1500 switch(u8DemodIndex)
1501 {
1502 case DEMOD0:
1503 u32HeaderReg = 0x103100 + (0x28)*2;
1504 break;
1505 case DEMOD1:
1506 u32HeaderReg = 0x103100 + (0x28)*2 + 1;
1507 break;
1508 /*
1509 case DEMOD2:
1510 u32HeaderReg = 0x2A00 + (0x29)*2;
1511 break;
1512 case DEMOD3:
1513 u32HeaderReg = 0x2A00 + (0x29)*2 + 1;
1514 break;
1515 */
1516 default :
1517 u32HeaderReg = 0x103100 + (0x28)*2;
1518 break;
1519 }
1520 if((*pDemod->sDMD_MSB201X_CIHeader_Param.pHeaderPtr) != *(pDMD_MSB201X_CIHeader_Param->pHeaderPtr))
1521 {
1522 _MDrv_DMD_MSB201X_SetReg(devID, u32HeaderReg, *(pDMD_MSB201X_CIHeader_Param->pHeaderPtr));
1523 }
1524
1525 // Enable ExtHeader
1526 // Clear bit 10 and 11, then set bit 11 to enable CI header
1527 u16Data &= 0x03ff;
1528 u16Data |= 0x0800;
1529
1530 // Restart TS
1531 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00) * 2, 0x0fff);
1532 MsOS_DelayTask(1);
1533 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2 + 1, ((u16Data & 0x0f00)>>8));
1534 _MDrv_DMD_MSB201X_SetReg(devID, 0x103100 + (0x00)*2, (u16Data & 0x00ff));
1535
1536 // Save setting parameters for next time comparison
1537 memcpy(&pDemod->sDMD_MSB201X_CIHeader_Param, pDMD_MSB201X_CIHeader_Param, sizeof(sDMD_MSB201X_CIHeader));
1538 }
1539
1540 return TRUE;
1541 }
1542
1543
_MDrv_DMD_MSB201X_Active(MS_U8 devID,MS_U8 u8DemodIndex,MS_BOOL bEnable)1544 MS_BOOL _MDrv_DMD_MSB201X_Active(MS_U8 devID, MS_U8 u8DemodIndex, MS_BOOL bEnable)
1545 {
1546 MS_U8 status = true;
1547 MS_U32 banknum = 0;
1548
1549 _MSB201X_I2C_CH_Reset(devID, 3);
1550
1551 switch(u8DemodIndex)
1552 {
1553 case 0:
1554 banknum = REG_DMD0_MB_CNTL;
1555 break;
1556 case 1:
1557 banknum = REG_DMD1_MB_CNTL;
1558 break;
1559 /*
1560 case 2:
1561 banknum = REG_DMD2_MB_CNTL;
1562 break;
1563 case 3:
1564 banknum = REG_DMD3_MB_CNTL;
1565 break;
1566 */
1567 default:
1568 banknum = REG_DMD0_MB_CNTL;
1569 break;
1570 }
1571
1572 if(bEnable == TRUE)
1573 _MDrv_DMD_MSB201X_SetReg(devID, banknum + (0x0e)*2, 0x01);
1574 //HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1575
1576 return status;
1577 }
1578
1579
_MSB201X_Demod_LoadAll(MS_U8 devID,eDMD_MSB201X_Demod_Index eDemod_Index)1580 static MS_BOOL _MSB201X_Demod_LoadAll(MS_U8 devID, eDMD_MSB201X_Demod_Index eDemod_Index)
1581 {
1582 MS_U16 i;
1583 unsigned short tmp;
1584
1585 if(eDemod_Index != ALL_DEMOD)
1586 {
1587 return FALSE;
1588 }
1589
1590 _MSB201X_I2C_CH_Reset(devID, 3);
1591 //MCU 0
1592 //Release dmd_mcu rst to wake up dmd51
1593 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x80, 0x01);
1594 //Load code finish, eable i-side to sram
1595 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x81, 0x00);
1596 //mux select for xdata setting from top riu to dmd riu
1597 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0x1C, 0x01);
1598 //Release dmd_mcu rst to wake up dmd51
1599 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x86, 0x01);
1600 //MCU 1
1601 //Release dmd_mcu rst to wake up dmd51
1602 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa6, 0x01);
1603 //Release dmd_mcu rst to wake up dmd51
1604 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa0, 0x01);
1605 //mux select for xdata setting from top riu to dmd riu
1606 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0x1C, 0x01);
1607 //Load code finish, eable i-side to sram
1608 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa1, 0x00);
1609
1610 //disable all pad in
1611 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x51, 0x00);
1612 //DMD 51 interrupt by PM51 DMD0
1613 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x83, 0x02);
1614 //DMD 51 interrupt by PM51 DMD1
1615 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa2, 0x02);
1616 //Enable program sram clock clk sram mcu
1617 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x17, 0x02);
1618 //default
1619 //_MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x16, 0x30); //24Mhz
1620 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x16, 0x00); //108Mhz
1621
1622 //MCU0
1623 //release dmd mcu periphal rst
1624 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x86, 0x00);
1625 //set upper bound
1626 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0xe0, 0x3f);
1627 //set lower bound
1628 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0xe1, 0x20);
1629 //enable
1630 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0xe6, 0x11);
1631
1632 //MCU1
1633 //release dmd mcu periphal rst
1634 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa6, 0x00);
1635 //set upper bound
1636 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0xe0, 0x3f);
1637 //set lower bound
1638 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0xe1, 0x20);
1639 //enable
1640 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0xe6, 0x11);
1641
1642
1643 //select all demod
1644 _MDrv_DMD_MSB201X_SetReg(devID, 0x103C00 + 0x28, 0x01);
1645
1646 _MSB201X_I2C_CH_Reset(devID, 1);
1647 _MDrv_DMD_MSB201X_SetReg(devID, 0x000000 + 0x00, 0x00);
1648
1649
1650 //// Load code thru VDMCU_IF ////
1651 #ifdef MS_DEBUG
1652 printf(">Load Demod Code.....\n");
1653 #endif
1654
1655 for ( i = 0; i < sizeof(MSB201X_DVBC_table);)
1656 {
1657 tmp = SRAM_BASE + i;
1658
1659 if (i+SRAM_Write_Buffer-1<sizeof(MSB201X_DVBC_table))
1660 {
1661 MDrv_DMD_MSB201X_SetRegs(devID, tmp,MSB201X_DVBC_table+i,SRAM_Write_Buffer);
1662
1663 i=i+SRAM_Write_Buffer-1;
1664 }
1665 else
1666 {
1667 MDrv_DMD_MSB201X_SetRegs(devID, tmp,MSB201X_DVBC_table+i,sizeof(MSB201X_DVBC_table)-i);
1668
1669 i=sizeof(MSB201X_DVBC_table);
1670 }
1671 }
1672
1673 _MSB201X_I2C_CH_Reset(devID, 3);
1674
1675 //mcu0
1676 //mux select for xdata setting from top riu to dmd riu
1677 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0x1C, 0x00);
1678 //Load code finish, eable i-side to sram
1679 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x81, 0x01);
1680 //Release dmd_mcu rst to wake up dmd51
1681 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x80, 0x00);
1682
1683 //mcu1
1684 //mux select for xdata setting from top riu to dmd riu
1685 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0x1C, 0x00);
1686 //Load code finish, eable i-side to sram
1687 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa1, 0x01);
1688 //Release dmd_mcu rst to wake up dmd51
1689 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa0, 0x00);
1690
1691
1692 _MSB201X_I2C_CH_Reset(devID, 5);
1693
1694
1695 #ifdef MS_DEBUG
1696 printf(">Demod Loadcode done.");
1697 #endif
1698
1699 return TRUE;
1700 }
1701
_MSB201X_Demod_LoadSingle(MS_U8 devID,MS_U8 u8DemodIndex)1702 static MS_BOOL _MSB201X_Demod_LoadSingle(MS_U8 devID, MS_U8 u8DemodIndex)
1703 {
1704 MS_U16 i;
1705 unsigned short tmp;
1706
1707 if(u8DemodIndex >= ALL_DEMOD)
1708 {
1709 return FALSE;
1710 }
1711
1712
1713 if(u8DemodIndex==DEMOD0)
1714 {
1715 //MCU 0
1716 //Release dmd_mcu rst to wake up dmd51
1717 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x80, 0x01);
1718 //Load code finish, eable i-side to sram
1719 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x81, 0x00);
1720 //mux select for xdata setting from top riu to dmd riu
1721 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0x1C, 0x01);
1722 //Release dmd_mcu rst to wake up dmd51
1723 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x86, 0x01);
1724 }
1725
1726 if(u8DemodIndex==DEMOD1)
1727 {
1728 //MCU 1
1729 //Release dmd_mcu rst to wake up dmd51
1730 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa6, 0x01);
1731 //Release dmd_mcu rst to wake up dmd51
1732 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa0, 0x01);
1733 //mux select for xdata setting from top riu to dmd riu
1734 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0x1C, 0x01);
1735 //Load code finish, eable i-side to sram
1736 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa1, 0x00);
1737 }
1738
1739 //disable all pad in
1740 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x51, 0x00);
1741 //DMD 51 interrupt by PM51 DMD0
1742 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x83, 0x02);
1743 //DMD 51 interrupt by PM51 DMD1
1744 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa2, 0x02);
1745 //Enable program sram clock clk sram mcu
1746 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x17, 0x02);
1747 //default
1748 //_MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x16, 0x30); //24MHz
1749
1750 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + 0x16, 0x00); //108MHz
1751
1752 if(u8DemodIndex==DEMOD0)
1753 {
1754 //MCU0
1755 //release dmd mcu periphal rst
1756 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x86, 0x00);
1757 //set upper bound
1758 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0xe0, 0x3f);
1759 //set lower bound
1760 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0xe1, 0x20);
1761 //enable
1762 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0xe6, 0x11);
1763 //DMD SINGLE DEMOD0
1764 _MDrv_DMD_MSB201X_SetReg(devID, 0x103C00 + 0x28, 0x00);
1765 _MDrv_DMD_MSB201X_SetReg(devID, 0x103C00 + 0x24, 0x00);
1766 }
1767
1768 if(u8DemodIndex==DEMOD1)
1769 {
1770 //MCU1
1771 //release dmd mcu periphal rst
1772 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa6, 0x00);
1773 //set upper bound
1774 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0xe0, 0x3f);
1775 //set lower bound
1776 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0xe1, 0x20);
1777 //enable
1778 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0xe6, 0x11);
1779 //DMD SINGLE DEMOD1
1780 _MDrv_DMD_MSB201X_SetReg(devID, 0x103C00 + 0x28, 0x00);
1781 _MDrv_DMD_MSB201X_SetReg(devID, 0x103C00 + 0x24, 0x01);
1782 }
1783
1784 _MSB201X_I2C_CH_Reset(devID, 1);
1785 _MDrv_DMD_MSB201X_SetReg(devID, 0x0000 + 0x00, 0x00); // reset VD_MCU
1786
1787 //// Load code thru VDMCU_IF ////
1788 #ifdef MS_DEBUG
1789 printf(">Load Demod Code.....\n");
1790 #endif
1791
1792 for ( i = 0; i < sizeof(MSB201X_DVBC_table);)
1793 {
1794 tmp = SRAM_BASE + i;
1795
1796 if (i+SRAM_Write_Buffer-1<sizeof(MSB201X_DVBC_table))
1797 {
1798 MDrv_DMD_MSB201X_SetRegs(devID, tmp,MSB201X_DVBC_table+i,SRAM_Write_Buffer);
1799
1800 i=i+SRAM_Write_Buffer-1;
1801 }
1802 else
1803 {
1804 MDrv_DMD_MSB201X_SetRegs(devID, tmp,MSB201X_DVBC_table+i,sizeof(MSB201X_DVBC_table)-i);
1805
1806 i=sizeof(MSB201X_DVBC_table);
1807 }
1808 }
1809
1810 _MSB201X_I2C_CH_Reset(devID, 3);
1811
1812 if(u8DemodIndex==DEMOD0)
1813 {
1814 //mux select for xdata setting from top riu to dmd riu
1815 _MDrv_DMD_MSB201X_SetReg(devID, 0x103700 + 0x1C, 0x00);
1816 //Load code finish, eable i-side to sram
1817 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x81, 0x01);
1818 //Release dmd_mcu rst to wake up dmd51
1819 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0x80, 0x00);
1820
1821 }
1822
1823 if(u8DemodIndex==DEMOD1)
1824 {
1825 //mux select for xdata setting from top riu to dmd riu
1826 _MDrv_DMD_MSB201X_SetReg(devID, 0x103800 + 0x1C, 0x00);
1827 //Load code finish, eable i-side to sram
1828 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa1, 0x01);
1829 //Release dmd_mcu rst to wake up dmd51
1830 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + 0xa0, 0x00);
1831 }
1832
1833 _MSB201X_I2C_CH_Reset(devID, 5);
1834
1835
1836 #ifdef MS_DEBUG
1837 printf(">Demod Loadcode done.");
1838 #endif
1839
1840 return TRUE;
1841 }
1842
1843 /*
1844 static MS_BOOL _MDrv_DMD_MSB201X_DSPReg_Init(MS_U8 devID)
1845 {
1846 MS_U8 idx = 0, idx2 = 0;
1847 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
1848
1849 for (idx = 0; idx<sizeof(MSB201X_DVBC_DSPREG_TABLE); idx++)
1850 {
1851 for(idx2 = 0; idx2<DEMOD_MAX_CHANNEL; idx2++)
1852 {
1853 if( _MDrv_DMD_MSB201X_SetDSPReg(devID, idx2, idx, pDemod->DVBC_DSP_REG[idx2][idx])!=TRUE)
1854 {
1855 printf("dvbc dsp reg init NG\n");
1856 return FALSE;
1857 }
1858 }
1859 }
1860
1861 // FSM enable
1862 for(idx = 0; idx<DEMOD_MAX_CHANNEL; idx++)
1863 _MDrv_DMD_MSB201X_Active(devID, idx, TRUE);
1864
1865 printf("DVBC dsp reg init ok\n");
1866
1867 return TRUE;
1868 }
1869 */
1870
1871
1872 MS_U16 _MSB201X_CHIP_MATCH_TABLE[] =
1873 {
1874 //Kaiser, Kaiserin, Keltic, Kronus, Kappa
1875 0x56, 0x41, 0x72, 0x2F, 0x75,
1876 };
1877
MDrv_DMD_MSB201X_LoadDSPCode(MS_U8 devID)1878 MS_BOOL MDrv_DMD_MSB201X_LoadDSPCode(MS_U8 devID)
1879 {
1880 MS_BOOL bRet = TRUE;
1881 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
1882 DMD_LOCK();
1883 //bRet = _LoadDSPCode();
1884 DMD_UNLOCK();
1885 return bRet;
1886 }
1887
MDrv_DMD_MSB201X_SetActive(MS_U8 devID,MS_U8 u8DemodIndex,MS_BOOL bEnable)1888 MS_BOOL MDrv_DMD_MSB201X_SetActive(MS_U8 devID, MS_U8 u8DemodIndex, MS_BOOL bEnable)
1889 {
1890 MS_BOOL bRet;
1891 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
1892
1893 DMD_LOCK();
1894
1895 bRet=_MDrv_DMD_MSB201X_Active(devID, u8DemodIndex, bEnable);
1896
1897 DMD_UNLOCK();
1898 return bRet;
1899 }
1900
_MDrv_DMD_MSB201X_InitClkgen(MS_U8 devID)1901 MS_BOOL _MDrv_DMD_MSB201X_InitClkgen(MS_U8 devID) //koln need modified
1902 {
1903 _MSB201X_I2C_CH_Reset(devID, 3);
1904
1905 //inivec.task.cpp
1906
1907
1908 // DMD HK init clk start
1909 // -------------------------------------------------------------------
1910 // Initialize DMD_ANA_MISC
1911 // -------------------------------------------------------------------
1912
1913 // Koln add
1914 // [0] reg_pd_ldo25i_ana // 2.5v LDO power down
1915 // [1] reg_pd_ldo25q_ana // 2.5v LDO power down
1916 // [2] reg_pd_ldo25i_dig // 2.5v LDO power down
1917 // [3] reg_pd_ldo25q_dig // 2.5v LDO power down
1918 // [4] reg_pd_ldo25_ref // 2.5v LDO power down
1919 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h53, 2'b01, 16'h0000);
1920 //wreg 4106 0x53 0x0000
1921 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x53)*2 , 0x00);
1922 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x53)*2+1, 0x00);
1923
1924 // [0] reg_tst_ldo25i
1925 // [1] reg_tst_ldo25q
1926 // [5:4] reg_tst_ldo25i_selfb
1927 // [7:6] reg_tst_ldo25q_selfb
1928 // [8] reg_pd_dm2p5ldoi = 1'b0
1929 // [9] reg_pd_dm2p5ldoq = 1'b0
1930 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h4f, 2'b11, 16'h0000);
1931 // wreg 4106 0x4f 0x0000
1932 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4f)*2 , 0x00);
1933 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4f)*2+1, 0x00);
1934
1935 // [0] reg_tst_ldo11_clk
1936 // [1] reg_tst_ldo26
1937 // [2] reg_tst_ldo11_cmp
1938 // [3] reg_pd_dm1p1ldo_clk = 1'b0
1939 // [4] reg_pd_dm1p1ldo_cmp = 1'b0
1940 // [6] reg_tst_ldo26_selfb
1941 // [7] reg_pd_dm2p6ldo = 1'b0
1942 // [9:8] reg_tst_ldo11_cmp_selfb
1943 // [11:10] reg_tst_ldo11_clk_selfb
1944 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h4e, 2'b11, 16'h0000);
1945 //wreg 4106 0x4e 0x0000
1946 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4e)*2 , 0x00);
1947 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4e)*2+1, 0x00);
1948
1949
1950 // [1:0] reg_mpll_loop_div_first feedback divider 00:div by 1 01:div by 2 10:div by 4 11:div by 8
1951 // [15:8] reg_mpll_loop_div_second feedback divider, div by binary data number
1952 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h33, 2'b11, 16'h1201); // Loop divider ; VCO = 24*(2^2)*9 = 864
1953 // wreg 4106 0x33 0x1201
1954 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x33)*2 , 0x01);
1955 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x33)*2+1, 0x12);
1956
1957 // [2:0] reg_mpll_ictrl charge pump current control
1958 // [3] reg_mpll_in_sel 1.8V or 3.3V reference clock domain select (1'b0=0==>3.3 V reference clock domain)
1959 // [4] reg_mpll_xtal2adc_sel select the XTAL clock bypass to MPLL_ADC_CLK
1960 // [5] reg_mpll_xtal2next_pll_sel crystal clock bypass to next PLL select
1961 // [6] reg_mpll_vco_offset set VCO initial offset frequency
1962 // [7] reg_mpll_pd gated reference clock and power down PLL analog_3v: 1=power down
1963 // [8] reg_xtal_en XTAL enable register; 1: enable
1964 // [10:9] reg_xtal_sel XTAL driven strength select.
1965 // [11] reg_mpll_porst MPLL input power on reset, connect to reg as MPLL_RESET
1966 // [12] reg_mpll_reset PLL software reset; 1:reset
1967 // [13] reg_pd_dmpll_clk XTAL to MPLL clock reference power down
1968 // [14] reg_pd_3p3_1 XTAL to CLK_24M_3P3_1 power down
1969 // [15] reg_pd_3p3_2 XTAL to CLK_24M_3P3_2 power down
1970 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h35, 2'b11, 16'h1803); // MPLL reset
1971 //wreg 4106 0x35 0x1803
1972 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2 , 0x03);
1973 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2+1, 0x18);
1974
1975 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h35, 2'b11, 16'h0003); // release MPLl reset
1976 //wreg 4106 0x35 0x0003
1977 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2 , 0x03);
1978 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2+1, 0x00);
1979
1980 // [0] reg_mpll_clk_dp_pd dummy
1981 // [1] reg_adc_clk_pd ADC output clock power down
1982 // [2] reg_mpll_div2_pd MPLL_DIV2 power down
1983 // [3] reg_mpll_div3_pd MPLL_DIV3 power down
1984 // [4] reg_mpll_div4_pd MPLL_DIV4 power down
1985 // [5] reg_mpll_div8_pd MPLL_DIV8 power down
1986 // [6] reg_mpll_div10_pd MPLL_DIV10 power down
1987 // [13:8] reg_mpll_adc_div_sel select the ADC clock divide ratio,ADC clk=XTAL_IN
1988 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h30, 2'b11, 16'h1e00); // divide ADC clock to 28.8Mhz = 24*36/30
1989 //wreg 4106 0x30 0x1e00
1990 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x30)*2 , 0x00);
1991 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x30)*2+1, 0x1e);
1992
1993
1994 //$display("--------------------------------------");
1995 //$display("Initialize ADC I/Q");
1996 //$display("--------------------------------------");
1997
1998 // [0] Q channel ADC power down
1999 // [1] I channel ADC power down
2000 // [2] Q channel clamp enable. 0:enable, 1:disable
2001 // [3] I channel clamp enable. 0:enable, 1:disable
2002 // [6:4] I channel input mux control;
2003 // 3'b000=I channel ADC calibration mode input
2004 // 3'b001=VIF signal from VIFPGA
2005 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
2006 // all the other combination are only for test mode, don't use without understanding.
2007 // [10:8] Q channel input mux control;
2008 // 3'b000=Q channel ADC calibration mode input
2009 // 3'b001=VIF signal from VIFPGA 3'b010 = SSIF signal from PAD_SIFP(M)
2010 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
2011 // all the other combination are only for test mode, don't use without understanding.
2012 // [12] ADC I,Q swap enable; 1: swap
2013 // [13] ADC clock out select; 1: ADC_CLKQ
2014 // [14] ADC linear calibration bypass enable; 1:enable
2015 // [15] ADC internal 1.2v regulator control always 0 in T3
2016 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h01, 2'b11, 16'h0440); // Set IMUXS QMUXS
2017 //wreg 4106 0x01 0x0440
2018 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x01)*2 , 0x40);
2019 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x01)*2+1, 0x04);
2020
2021 // [2:0] reg_imuxs_s
2022 // [6:4] reg_qmuxs_s
2023 // [9:8] reg_iclpstr_s
2024 // [13:12] reg_qclpstr_s
2025 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h45, 2'b01, 16'h0000); // Set IMUXS QMUXS
2026 //wreg 4106 0x45 0x0000
2027 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x45)*2 , 0x00);
2028 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x45)*2+1, 0x00);
2029
2030
2031 // [0] Channel I ADC power down: 1=power dwon
2032 // [1] Channel Q ADC power down: 1=power dwon
2033 // [2] power down clamp buffer for test mode
2034 // [3] change ADC reference voltage for SSIF
2035 // [6:4] ADC source bias current control
2036 // [9:8] XTAL receiver amp gain
2037 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h0c, 2'b11, 16'h0000); // Set enable ADC clock
2038 // wreg 4106 0x0c 0x0000
2039 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0c)*2 , 0x00);
2040 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0c)*2+1, 0x00);
2041
2042
2043 // [0] reg_linear_cal_start_q 0 0 1
2044 // [1] reg_linear_cal_mode_q 0 0 1
2045 // [2] reg_linear_cal_en_q 0 0 1
2046 // [3] reg_linear_cal_code0_oren_q 0 0 1
2047 // [6:4] reg_linear_cal_status_sel_q 2 0 3
2048 // [7] reg_pwdn_vcalbuf 0 0 1
2049
2050 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h0f, 2'b01, 16'h0000); // Set reg_pwdn_vcalbuf = 1'b0
2051 // wreg 4106 0x0f 0x0000
2052 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0f)*2 , 0x00);
2053 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0f)*2+1, 0x00);
2054
2055
2056 // [3:0] clamp voltage control
2057 // 3'b000 = 0.7v
2058 // 3'b001 = 0.75v
2059 // 3'b010 = 0.5v
2060 // 3'b011 = 0.4v
2061 // 3'b100 = 0.8v
2062 // 3'b101 = 0.9v
2063 // 3'b110 = 0.65v
2064 // 3'b111 = 0.60v
2065 // [4] REFERENCE power down
2066 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h20, 2'b11, 16'h0000); // Disable PWDN_REF
2067 //wreg 4106 0x20 0x0000
2068 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x20)*2 , 0x00);
2069 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x20)*2+1, 0x00);
2070 // Set ADC gain is 1
2071 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h0b, 2'b11, 16'h0505);
2072 //wreg 4106 0x0b 0x0505
2073 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0b)*2 , 0x05);
2074 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0b)*2+1, 0x05);
2075
2076 // Disable ADC Sign bit
2077 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h2e, 2'b11, 16'h0000);
2078 //wreg 4106 0x2e 0x0000
2079 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2e)*2 , 0x00);
2080 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2e)*2+1, 0x00);
2081
2082 // ADC I channel offset
2083 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h2a, 2'b11, 16'h0c00);
2084 //wreg 4106 0x2a 0x0c00
2085 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2a)*2 , 0x00);
2086 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2a)*2+1, 0x0c);
2087
2088 // ADC Q channel offset
2089 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h2b, 2'b11, 16'h0c00);
2090 //wreg 4106 0x2b 0x0c00
2091 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2b)*2 , 0x00);
2092 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2b)*2+1, 0x0c);
2093
2094
2095 // [5:0]reg_ckg_mcu
2096 // [6] reg_power_good_mask
2097 // [11:8]reg_ckg_inner
2098 // [15:12]reg_ckg_iicm1
2099 // `RIU_W((`RIUBASE_TOP>>1)+7'h0b, 2'b11, 16'h0430);
2100 //wreg 4105 0x0b 0x0030
2101 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2b)*2 , 0x30);
2102 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2b)*2+1, 0x00);
2103
2104
2105 // [1:0]reg_chanout_sel
2106 // [2] reg_iq_filter_enable = 1
2107 // [3] reg_iq_filter_sel
2108 // [5:4]reg_adc_debug_clk_sel
2109 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h17, 2'b11, 16'h0004);
2110 //wreg 4106 0x17 0x0004
2111 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x17)*2 , 0x04);
2112 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x17)*2+1, 0x00);
2113
2114
2115
2116 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h51, 2'b01, 16'h0081); // 2 channel DVBC
2117 //wreg 4106 0x51 0x0081
2118 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2 , 0x81);
2119 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2+1, 0x00);
2120
2121
2122 // -------------------------------------------------------------------
2123 // Release clock gating
2124 // -------------------------------------------------------------------
2125 //$display("--------------------------------------");
2126 //$display("Release clock gating");
2127 //$display("--------------------------------------");
2128
2129 // [0] reg_xtal_en
2130 // [9:8] reg_clk_pd_iic
2131 // [10] reg_clk_pd_all
2132 // `RIU_W((`RIUBASE_TOP>>1)+7'h09, 2'b11, 16'h0101);
2133 //wreg 4105 0x09 0x0101
2134 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2 , 0x01);
2135 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2+1, 0x01);
2136
2137 // [3:0] reg_ckg_adcd
2138 // [7:4] reg_ckg_sadc
2139 // [11:8] reg_ckg_iicm
2140 // [13:12] reg_ckg_sbus
2141 // `RIU_W((`RIUBASE_TOP>>1)+7'h0a, 2'b11, 16'h0000);
2142 //wreg 4105 0x0a 0x0000
2143 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2 , 0x00);
2144 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2+1, 0x00);
2145
2146 // [5:0] reg_ckg_mcu
2147 // [6] reg_ckg_live
2148 // [11:8] reg_ckg_inner
2149 // `RIU_W((`RIUBASE_TOP>>1)+7'h0b, 2'b11, 16'h0030);
2150 // wreg 4105 0x0b 0x0030
2151 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0b)*2 , 0x00);
2152 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0b)*2+1, 0x00);
2153
2154
2155 // @0x0912
2156 // [3:0] reg_ckg_dvbtm_ts
2157 // [4] reg_dvbtm_ts_out_mode
2158 // [5] reg_dvbtm_ts_clk_pol
2159 // [15:8] reg_dvbtm_ts_clk_divnum
2160 // `RIU_W((`RIUBASE_TOP>>1)+7'h12, 2'b11, 16'h1418);
2161 //wreg 4105 0x12 0x1418
2162 //_MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 , 0x18);
2163 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 , 0x10);
2164 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2+1, 0x14);
2165
2166 // @0x0913
2167 // [5:0] reg_ckg_spi
2168 // `RIU_W((`RIUBASE_TOP>>1)+7'h13, 2'b11, 16'h0020);
2169 //wreg 4105 0x13 0x0020
2170 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x13)*2 , 0x20);
2171 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x13)*2+1, 0x00);
2172
2173
2174 // @0x091b
2175 // [10:8] reg_ckg_syn_miu
2176 // [14:12] reg_ckg_syn_ts
2177 // `RIU_W((`RIUBASE_TOP>>1)+7'h1b, 2'b11, 16'h0000);
2178 // wreg 4105 0x1b 0x0000
2179 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1b)*2 , 0x00);
2180 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1b)*2+1, 0x00);
2181
2182
2183
2184 // @0x091c
2185 // [4:0] reg_ckg_bist
2186 // [11:8] reg_ckg_adcd_d2
2187 // `RIU_W((`RIUBASE_TOP>>1)+7'h1c, 2'b11, 16'h0000);
2188 //wreg 4105 0x1c 0x0000
2189
2190 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1c)*2 , 0x00);
2191 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1c)*2+1, 0x00);
2192
2193
2194 // [1:0] reg_iicm_pad_sel
2195 // [4] reg_i2c_sbpm_en
2196 // [12:8] reg_i2c_sbpm_idle_num
2197 // `RIU_W((`RIUBASE_TOP>>1)+7'h08, 2'b01, 16'h0a01);
2198 //wreg 4105 0x08 0x0a01
2199
2200 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x08)*2 , 0x01);
2201 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x08)*2+1, 0x0a);
2202
2203 // [8] reg_turn_off_pad
2204 // `RIU_W((`RIUBASE_TOP>>1)+7'h28, 2'b10, 16'h0000);
2205 // wreg 4105 0x28 0x0000
2206 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x28)*2 , 0x00);
2207 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x28)*2+1, 0x00);
2208
2209
2210
2211
2212 //$display("--------------------------------------");
2213 //$display("Initialize Transport Stream synthesizer and APLL");
2214 //$display("--------------------------------------");
2215
2216 // ////////////////////////////////////////////////////
2217 //
2218 // According to analog APLL designer's suggest:
2219 // APLL_LOOP_DIV = 5'b00000
2220 // apll input frequency range 54MHz~106MHz synthesizer clock
2221 // so apll_1x_out = synthesizer_out * (apll_ts_mode + 1)
2222 //
2223 // => apll_1x_out should 40Mhz ~ 130Mhz
2224 //
2225 // Current setting:
2226 // apll_1x_out = (432/8.0) * (1+1) = 108MHz
2227 // choose reg_ckg_ts_apll_div[2:0] = 3'd4
2228 // ts_clk_apll_div = 108/(2^4) = 6.75MHz
2229 //
2230 // ////////////////////////////////////////////////////
2231
2232
2233 // [15:0] reg_synth_set[15: 0]
2234 // [ 7:0] reg_synth_set[23:16]
2235 // `RIU_W((`RIUBASE_TOP>>1)+7'h51, 2'b11, 16'h0000);
2236 //wreg 4105 0x51 0x0000
2237 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x51)*2 , 0x00);
2238 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x51)*2+1, 0x00);
2239 // `RIU_W((`RIUBASE_TOP>>1)+7'h52, 2'b11, 16'h0040);
2240 //wreg 4105 0x52 0x0040
2241 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x52)*2 , 0x40);
2242 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x52)*2+1, 0x00);
2243
2244
2245 // [0] reg_synth_reset
2246 // [1] reg_synth_ssc_en
2247 // [2] reg_synth_ssc_mode
2248 // [4] reg_synth_sld
2249 // `RIU_W((`RIUBASE_TOP>>1)+7'h50, 2'b01, 16'h0010);
2250 //wreg 4105 0x50 0x0010
2251
2252 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x50)*2 , 0x10);
2253 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x50)*2+1, 0x00);
2254
2255 // #10_000;
2256 //delay 0 ****
2257
2258
2259 // [1:0] reg_apll_loop_div_first
2260 // [15:8] reg_apll_loop_div_second
2261 // `RIU_W((`RIUBASE_TOP>>1)+7'h57, 2'b11, 16'h0000);
2262 //wreg 4105 0x57 0x0000
2263
2264 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x57)*2 , 0x00);
2265 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x57)*2+1, 0x00);
2266
2267
2268 // [0] reg_apll_pd
2269 // [1] reg_apll_reset
2270 // [2] reg_apll_porst
2271 // [3] reg_apll_vco_offset
2272 // [4] reg_apll_en_ts
2273 // [5] reg_apll_endcc
2274 // [6] reg_apll_clkin_sel
2275 // [8] reg_apll_ts_mode
2276 // `RIU_W((`RIUBASE_TOP>>1)+7'h55, 2'b11, 16'h0100);
2277 //wreg 4105 0x55 0x0100
2278 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2 , 0x00);
2279 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2+1, 0x01);
2280 // `RIU_W((`RIUBASE_TOP>>1)+7'h55, 2'b01, 16'h0110);
2281 //wreg 4105 0x55 0x0110
2282 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2 , 0x10);
2283 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2+1, 0x01);
2284
2285 // [16:0] reg_apll_test
2286 // `RIU_W((`RIUBASE_TOP>>1)+7'h59, 2'b11, 16'h0000);
2287 //wreg 4105 0x59 0x0000
2288 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x59)*2 , 0x00);
2289 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x59)*2+1, 0x00);
2290
2291 // 0x0920
2292 // [3:0] reg_ckg_ts_apll_div[2:0]
2293 // `RIU_W((`RIUBASE_TOP>>1)+7'h20, 2'b01, 16'h0004);
2294 //wreg 4105 0x20 0x0004
2295 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x20)*2 , 0x04);
2296 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x20)*2+1, 0x00);
2297
2298 // Following register control by reg_CLKGEN1
2299 // reg_ckg_atsc_dvb_div_sel, (clkgen0)
2300 // reg_ckg_atsc_dvbtc_ts_inv, (clkgen0)
2301 // reg_ckg_atsc_ts, (clkgen0)
2302 // reg_ckg_demod_test_in_en, (clkgen0, clkgen_dmd)
2303 // reg_ckg_dmdmcu, (clkgen0)
2304 // reg_ckg_dvbtc_adc, (clkgen0, clkgen_dmd)
2305 // reg_ckg_dvbtc_ts, (clkgen0)
2306 // reg_ckg_dvbtm_ts_divnum, (clkgen0)
2307 // reg_ckg_dvbtm_ts_out_mode, (clkgen0)
2308 // reg_ckg_vifdbb_dac, (clkgen0, clkgen_dmd)
2309 // reg_ckg_vifdbb_vdac, (clkgen0, clkgen_dmd)
2310
2311
2312
2313 //$display("Set register at TOP (clkgen) ......");
2314
2315 // { 1'b0, reg_ckg_adcd1[3:0], reg_clk_pd_all, 1'b0, reg_clk_pd_iic, 7'h0, reg_xtal_en }
2316 // `RIU_W((`RIUBASE_TOP>>1)+7'h09, 2'b10, 16'h0000);
2317 //wreg 4105 0x09 0x0000
2318 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2 , 0x00);
2319 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2+1, 0x00);
2320 // { 2'h0, reg_ckg_sbus[1:0], reg_ckg_iicm[3:0], reg_ckg_sadc[3:0], reg_ckg_adcd[3:0] }
2321 // `RIU_W((`RIUBASE_TOP>>1)+7'h0a, 2'b01, 16'h1110);
2322 // wreg 4105 0x0a 0x1110
2323 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2 , 0x10);
2324 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2+1, 0x11);
2325
2326 // { reg_ckg_demod_mpll[3:0], 4'h0, reg_ckg_dmdxtali[3:0], reg_ckg_dmdmcu[3:0] }
2327 // `RIU_W((`RIUBASE_TOP>>1)+7'h0d, 2'b10, 16'h0000);
2328 //wreg 4105 0x0d 0x0000
2329 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0d)*2 , 0x00);
2330 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0d)*2+1, 0x00);
2331
2332 // DVBC : 24*36/30=28.8 MHz
2333 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h33, 2'b11, 16'h1201); // Set MPLL_LOOP_DIV_FIRST and SECOND
2334 //wreg 4106 0x33 0x1201
2335 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x33)*2 , 0x01);
2336 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x33)*2+1, 0x12);
2337 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h30, 2'b11, 16'h1e00+16'h1); // Set MPLL_ADC_DIV_SEL
2338
2339 // reg_ckg_ts_0 = 4'd0;
2340 // reg_ckg_ts_1 = 4'd0;
2341 // `RIU_W((`RIUBASE_TOP>>1)+7'h23, 2'b01, 16'h0000);
2342 //wreg 4105 0x23 0x0000
2343 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x23)*2 , 0x00);
2344 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x23)*2+1, 0x00);
2345
2346 //$display("=================================================");
2347 //$display("start demod atop ADC setting ......");
2348 //$display("=================================================");
2349
2350 // { 8'h0, reg_ana_setting_sel[3:0], 3'h0, reg_ana_setting_enable } )
2351 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h51, 2'b01, 16'h0081);
2352 //wreg 4106 0x51 0x0081
2353 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2 , 0x81);
2354 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2+1, 0x00);
2355
2356 //if agc enable
2357 //wreg 4106 0x18 0x0101
2358 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x18)*2 , 0x01);
2359 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x18)*2+1, 0x01);
2360
2361 //wreg 4106 0x30 0x1200
2362 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x30)*2 , 0x00);
2363 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x30)*2+1, 0x12);
2364
2365
2366
2367
2368
2369 return TRUE;
2370 }
2371
_MDrv_DMD_MSB201X_SoftStop(MS_U8 devID,MS_U8 u8DemodIndex)2372 MS_BOOL _MDrv_DMD_MSB201X_SoftStop(MS_U8 devID, MS_U8 u8DemodIndex)
2373 {
2374 MS_U16 u8WaitCnt=0;
2375 MS_U16 banknum;
2376 MS_U8 tmp, intr_shift;
2377
2378 _MSB201X_I2C_CH_Reset(devID, 3);
2379 // Select mailbox bank number
2380 switch(u8DemodIndex)
2381 {
2382 case 0:
2383 banknum = 0x2600;
2384 intr_shift = 0x41;
2385 break;
2386 case 1:
2387 banknum = 0x2900;
2388 intr_shift = 0x51;
2389 break;
2390 case 2:
2391 banknum = 0x3300;
2392 intr_shift = 0x61;
2393 break;
2394 case 3:
2395 banknum = 0x3700;
2396 intr_shift = 0x71;
2397 break;
2398 default :
2399 banknum = 0x2600;
2400 intr_shift = 0x41;
2401 break;
2402 }
2403
2404 _MDrv_DMD_MSB201X_SetReg(devID, banknum + 0x00, 0xA5); // MB_CNTL set read mode
2405
2406 _MDrv_DMD_MSB201X_SetReg(devID, 0x3400 + (intr_shift * 2) + 1, 0x02); // assert interrupt to VD MCU51
2407 _MDrv_DMD_MSB201X_SetReg(devID, 0x3400 + (intr_shift * 2) + 1, 0x00); // de-assert interrupt to VD MCU51
2408
2409 _MDrv_DMD_MSB201X_GetReg(devID, banknum + 0x00, &tmp);
2410 while(tmp != 0x5A) // wait MB_CNTL set done
2411 {
2412 if (u8WaitCnt++ >= 0xFF)
2413 {
2414 printf(">> SoftStop Fail!\n");
2415 return FALSE;
2416 }
2417 _MDrv_DMD_MSB201X_GetReg(devID, banknum + 0x00, &tmp);
2418 }
2419
2420 _MDrv_DMD_MSB201X_SetReg(devID, banknum + 0x00, 0x00); // MB_CNTL clear
2421
2422 return TRUE;
2423 }
2424
_MDrv_DMD_MSB201X_Select_Demod_RIU(MS_U8 devID,MS_U8 u8DemodIndex)2425 MS_BOOL _MDrv_DMD_MSB201X_Select_Demod_RIU(MS_U8 devID, MS_U8 u8DemodIndex) //koln
2426 {
2427 _MSB201X_I2C_CH_Reset(devID, 3);
2428 _MDrv_DMD_MSB201X_SetReg(devID, 0x103C00 + (0x13)*2, u8DemodIndex);
2429
2430 return TRUE;
2431 }
2432
2433 #if(0)
_MDrv_DMD_MSB201X_TS_MUX_Serial(MS_U8 devID)2434 MS_BOOL _MDrv_DMD_MSB201X_TS_MUX_Serial(MS_U8 devID)
2435 {
2436
2437
2438 _MSB201X_I2C_CH_Reset(devID, 3);
2439
2440 // This file is translated by Steven Hung's riu2script.pl test
2441
2442 // `RIU_W ((`RIUBASE_TOP>>1)+7'h12, 2'b11, 16'h0610); //reg_ckg_dvbtm_ts_mux
2443 //wreg 0x1009 0x12 0x0220
2444 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x12)*2, 0x0220);
2445 // `RIU_W ((`RIUBASE_TOP>>1)+7'h1e, 2'b11, 16'h4444); //reg_ckg_ts_mux
2446 //wreg 0x1009 0x1e 0x4444
2447 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x1e)*2, 0x4444);
2448 // `RIU_W ((`RIUBASE_TOP>>1)+7'h23, 2'b11, 16'h0000); //reg_ckg_ts_*
2449 //wreg 0x1009 0x23 0x0000
2450 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x23)*2, 0x0000);
2451 // `RIU_W ((`RIUBASE_TOP>>1)+7'h28, 2'b11, 16'h0000); //all pad in
2452 //wreg 0x1009 0x28 0x0000
2453 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x28)*2, 0x0000);
2454 // `RIU_W ((`RIUBASE_TOP>>1)+7'h2e, 2'b11, 16'h0103); //en ts
2455 // reg_en_ts_err_pad
2456 ////wreg 0x1009 0x2e 0x0103
2457 // reg_en_ts_pad_serial_3wire_mode
2458 //wreg 0x1009 0x2d 0x0003
2459 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x2d)*2, 0x0003);
2460 // reg_en_ts_pad_parallel_mode
2461 //wreg 0x1009 0x2e 0x0000
2462 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x2e)*2, 0x0000);
2463 // reg_en_ts_pad_serial_4wire_mode
2464 //wreg 0x1009 0x29 0x0100
2465 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x29)*2, 0x0100);
2466 // `RIU_W ((`RIUBASE_TOP>>1)+7'h3b, 2'b11, 16'h0000); //disable reg_ts_sspi_en
2467 //wreg 0x1009 0x3b 0x0000
2468 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x3b)*2, 0x0000);
2469
2470 // reg_ckg_ts_0~3
2471 //wreg 0x1009 0x23 0x8888
2472 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100900 + (0x23)*2, 0x8888);
2473
2474 // `RIU_W ((`RIUBASE_DIG>>1)+7'h70, 2'b11, 16'h0000); //reg_swrst_ts_mux
2475 //wreg 0x100b 0x70 0x0000
2476 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x100b00 + (0x70)*2, 0x0000);
2477
2478
2479 //TS remux bank setting
2480 // wreg 42 0x00 0x00ff
2481 //wreg 0x1031 0x00 0x00ff
2482 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00)*2, 0x00ff);
2483
2484 //serial mode
2485 //wreg 42 0x01 0x001e
2486 //wreg 0x1031 0x01 0x001e
2487 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x01)*2, 0x001e);
2488
2489
2490 //*****************************/
2491 //wreg 0x1031 0x04 0x802a
2492 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x04)*2, 0x802a);
2493 // `RIU_W ((`RIUBASE_TS_MUX>>1)+7'h06, 2'b11, 16'h0020); //reg_client_mask
2494 //wreg 0x1031 0x06 0x0020
2495 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x06)*2, 0x0020);
2496
2497 //disable sync mask function
2498 //wreg 0x1031 0x02 0x001f
2499 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x02)*2, 0x001f);
2500 // _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x02)*2, 0x001f);
2501 //*******************************/
2502
2503 // wreg 42 0x00 0x03ff
2504 //wreg 0x1031 0x00 0x03ff
2505 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00)*2, 0x03ff);
2506 // wreg 42 0x00 0x00ff
2507 //wreg 0x1031 0x00 0x00ff
2508 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00)*2, 0x00ff);
2509 // wreg 42 0x00 0x000f
2510 //wreg 0x1031 0x00 0x000f
2511 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x103100 + (0x00)*2, 0x000f);
2512
2513 return TRUE;
2514 }
2515 #endif
2516
_MDrv_DMD_MSB201X_Restart(MS_U8 devID,MS_U8 u8DemodIndex)2517 MS_BOOL _MDrv_DMD_MSB201X_Restart(MS_U8 devID, MS_U8 u8DemodIndex)
2518 {
2519 MS_U8 reset_shift;
2520 MS_U16 banknum;
2521
2522
2523 // Select mailbox bank number and DMD_MCU reset shift
2524 switch(u8DemodIndex)
2525 {
2526 case 0:
2527 banknum = 0x1035;
2528 reset_shift = 0x40;
2529 break;
2530 case 1:
2531 banknum = 0x1036;
2532 reset_shift = 0x50;
2533 break;
2534 /*
2535 case 2:
2536 banknum = 0x3300;
2537 reset_shift = 0x60;
2538 break;
2539 case 3:
2540 banknum = 0x3700;
2541 reset_shift = 0x70;
2542 break;
2543 */
2544 default :
2545 banknum = 0x1035;
2546 reset_shift = 0x40;
2547 break;
2548 }
2549
2550 printf(" @MDrv_DMD_MSB201X_Restart!\n");
2551
2552 _MSB201X_I2C_CH_Reset(devID, 3);
2553 _MDrv_DMD_MSB201X_SoftStop(devID, u8DemodIndex);
2554
2555 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
2556
2557 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + reset_shift*2, 0x01); // reset DMD_MCU
2558
2559 _MSB201X_Delay_Task(5);
2560 _MDrv_DMD_MSB201X_SetReg(devID, banknum + 0x00 , 0x00); // clear MB_CNTL
2561
2562 _MDrv_DMD_MSB201X_SetReg(devID, 0x103400 + reset_shift*2, 0x00);
2563 _MSB201X_Delay_Task(5);
2564
2565 _MDrv_DMD_MSB201X_SetReg(devID, banknum + 0x00 , 0x00);
2566
2567 return TRUE;
2568 }
2569
MDrv_DMD_MSB201X_Restart(MS_U8 devID,MS_U8 u8DemodIndex)2570 MS_BOOL MDrv_DMD_MSB201X_Restart(MS_U8 devID, MS_U8 u8DemodIndex)
2571 {
2572 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
2573 DMD_LOCK();
2574
2575 _MDrv_DMD_MSB201X_Restart(devID, u8DemodIndex);
2576
2577 DMD_UNLOCK();
2578 return TRUE;
2579 }
2580
_MDrv_DMD_MSB201X_GetPacketErr(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 * pktErr)2581 MS_BOOL _MDrv_DMD_MSB201X_GetPacketErr(MS_U8 devID,MS_U8 u8DemodIndex, MS_U16 *pktErr)
2582 {
2583 MS_U8 reg = 0, reg_frz = 0;
2584 MS_U16 PktErr;
2585
2586 _MSB201X_I2C_CH_Reset(devID, 5);
2587
2588 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2589 _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x03, ®_frz);
2590 _MDrv_DMD_MSB201X_SetReg(devID, BACKEND_REG_BASE+0x03, reg_frz|0x03);
2591
2592 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
2593 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
2594 _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x67, ®);
2595 PktErr = reg;
2596
2597 _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x66, ®);
2598 PktErr = (PktErr << 8)|reg;
2599
2600 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2601 reg_frz=reg_frz&(~0x03);
2602 _MDrv_DMD_MSB201X_SetReg(devID, BACKEND_REG_BASE+0x03, reg_frz);
2603
2604 #if 1
2605 printf("MSB201X Demod %d PktErr = %d \n ", (int)u8DemodIndex, (int)PktErr);
2606 #endif
2607
2608 *pktErr = PktErr;
2609
2610 return TRUE;
2611 }
2612
MDrv_DMD_MSB201X_GetPacketErr(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 * pktErr)2613 MS_BOOL MDrv_DMD_MSB201X_GetPacketErr(MS_U8 devID,MS_U8 u8DemodIndex, MS_U16 *pktErr)
2614 {
2615 MS_BOOL status = true;
2616 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
2617 DMD_LOCK();
2618
2619 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
2620 _MDrv_DMD_MSB201X_GetPacketErr(devID,u8DemodIndex, pktErr);
2621
2622 DMD_UNLOCK();
2623
2624 return status;
2625 }
2626
_MDrv_DMD_MSB201X_GetPostViterbiBer(MS_U8 devID,MS_U8 u8DemodIndex,float * ber)2627 MS_BOOL _MDrv_DMD_MSB201X_GetPostViterbiBer(MS_U8 devID,MS_U8 u8DemodIndex, float *ber)
2628 {
2629 MS_BOOL status = true;
2630 MS_U8 reg = 0, reg_frz = 0;
2631 MS_U16 BitErrPeriod;
2632 MS_U32 BitErr;
2633
2634 _MSB201X_I2C_CH_Reset(devID, 5);
2635
2636 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2637 _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x03, ®_frz);
2638 _MDrv_DMD_MSB201X_SetReg(devID, BACKEND_REG_BASE+0x03, reg_frz|0x03);
2639
2640 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
2641 // 0x47 [15:8] reg_bit_err_sblprd_15_8
2642 _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x47, ®);
2643 BitErrPeriod = reg;
2644
2645 _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x46, ®);
2646 BitErrPeriod = (BitErrPeriod << 8)|reg;
2647
2648 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
2649 // 0x6b [15:8] reg_bit_err_num_15_8
2650 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
2651 // 0x6d [15:8] reg_bit_err_num_31_24
2652 status &= _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x6d, ®);
2653 BitErr = reg;
2654
2655 status &= _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x6c, ®);
2656 BitErr = (BitErr << 8)|reg;
2657
2658 status &= _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x6b, ®);
2659 BitErr = (BitErr << 8)|reg;
2660
2661 status &= _MDrv_DMD_MSB201X_GetReg(devID, BACKEND_REG_BASE+0x6a, ®);
2662 BitErr = (BitErr << 8)|reg;
2663
2664 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2665 reg_frz=reg_frz&(~0x03);
2666 _MDrv_DMD_MSB201X_SetReg(devID, BACKEND_REG_BASE+0x03, reg_frz);
2667
2668 if (BitErrPeriod == 0 ) //protect 0
2669 BitErrPeriod = 1;
2670
2671 if (BitErr <=0 )
2672 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
2673 else
2674 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
2675
2676 printf("MSB201X Demod %d PostVitBER = %8.3e \n ", (int)u8DemodIndex, *ber);
2677
2678 return TRUE;
2679 }
2680
MDrv_DMD_MSB201X_GetPostViterbiBer(MS_U8 devID,MS_U8 u8DemodIndex,float * ber)2681 MS_BOOL MDrv_DMD_MSB201X_GetPostViterbiBer(MS_U8 devID,MS_U8 u8DemodIndex, float *ber)
2682 {
2683 MS_BOOL status = true;
2684 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
2685 DMD_LOCK();
2686
2687 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
2688 _MDrv_DMD_MSB201X_GetPostViterbiBer(devID,u8DemodIndex, ber);
2689
2690 DMD_UNLOCK();
2691
2692 return status;
2693 }
2694
_MDrv_DMD_MSB201X_GetSNR(MS_U8 devID,MS_U8 u8DemodIndex,float * f_snr)2695 MS_BOOL _MDrv_DMD_MSB201X_GetSNR(MS_U8 devID,MS_U8 u8DemodIndex, float *f_snr)
2696 {
2697 MS_BOOL status = true;
2698 MS_U8 u8Data = 0;//reg_frz = 0;
2699 // MS_U8 freeze = 0;
2700 MS_U16 noisepower = 0;
2701
2702 if (TRUE == MDrv_DMD_MSB201X_Demod_GetLock(devID, u8DemodIndex) )
2703 {
2704 _MSB201X_I2C_CH_Reset(devID, 5);
2705
2706 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2707 status &= _MDrv_DMD_MSB201X_SetReg(devID, EQE_REG_BASE + 0x3a, 0x20);
2708 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x80);
2709 // read vk
2710 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x45, &u8Data);
2711 noisepower = u8Data;
2712 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x44, &u8Data);
2713 noisepower = (noisepower<<8)|u8Data;
2714
2715 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2716 status &= _MDrv_DMD_MSB201X_SetReg(devID, EQE_REG_BASE + 0x3a, 0x00);
2717 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x00);
2718
2719 if(noisepower == 0x0000)
2720 noisepower = 0x0001;
2721
2722 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
2723
2724 }
2725 else
2726 {
2727 *f_snr = 0.0f;
2728 }
2729
2730 return status;
2731 }
2732
MDrv_DMD_MSB201X_GetSNR(MS_U8 devID,MS_U8 u8DemodIndex,float * fSNR)2733 MS_BOOL MDrv_DMD_MSB201X_GetSNR(MS_U8 devID,MS_U8 u8DemodIndex, float *fSNR)
2734 {
2735 MS_BOOL bRet;
2736 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
2737 DMD_LOCK();
2738
2739 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
2740 bRet=_MDrv_DMD_MSB201X_GetSNR(devID, u8DemodIndex, fSNR);
2741
2742 DMD_UNLOCK();
2743
2744 return bRet;
2745 }
2746
_MDrv_DMD_MSB201X_Variable_alloc(void)2747 static MS_BOOL _MDrv_DMD_MSB201X_Variable_alloc(void)
2748 {
2749 MS_U8 i;
2750 tMSB201X_Demod_Data *pMSB201X = NULL;
2751
2752 if(NULL == pstDemod)
2753 {
2754 pstDemod = (tMSB201X_Demod_Data *)malloc(sizeof(tMSB201X_Demod_Data) * DEMOD_MAX_INSTANCE);
2755 if(NULL == pstDemod)
2756 {
2757 return FALSE;
2758 }
2759 else
2760 {
2761 for(i=0; i< DEMOD_MAX_INSTANCE; i++)
2762 {
2763 pMSB201X = (pstDemod + i);
2764 memcpy(pMSB201X, &MSB201X_Demod_Init, sizeof(tMSB201X_Demod_Data));
2765 }
2766 }
2767 }
2768
2769 if(NULL == pDemodRest)
2770 {
2771 pDemodRest = (MS_BOOL*)malloc(sizeof(MS_BOOL) * DEMOD_MAX_INSTANCE);
2772 if(NULL == pDemodRest)
2773 {
2774 return FALSE;
2775 }
2776 else
2777 {
2778 for(i=0; i< DEMOD_MAX_INSTANCE; i++)
2779 *(pDemodRest + i) = TRUE;
2780 }
2781 }
2782
2783 return TRUE;
2784 }
2785
2786
2787
2788
2789
2790
2791
2792
2793
_MSB201X_Demod_SPILoadAll(MS_U8 devID,eDMD_MSB201X_Demod_Index eDemod_Index,MS_U8 * u8_ptr,MS_U16 data_length)2794 static MS_BOOL _MSB201X_Demod_SPILoadAll(MS_U8 devID, eDMD_MSB201X_Demod_Index eDemod_Index, MS_U8 *u8_ptr, MS_U16 data_length)
2795 {
2796 MS_BOOL bRet = TRUE;
2797 MS_U32 u32Addr = 0;
2798
2799 _MSB201X_I2C_CH_Reset(devID, 3);
2800
2801
2802
2803 //2.Enable sspi2dmd51 sram & select sspi mode
2804 //SSPI_RIU_W, addr:0x0974, data:0x3100 (dmdall)
2805 MDrv_DMD_SSPI_RIU_Write8(0x0974, 0x00);
2806 MDrv_DMD_SSPI_RIU_Write8(0x0975, 0x30);
2807 //3. Disable all pad in
2808 //SSPI_RIU_W, addr:0x0950, data:0x0000 (dmdall)
2809 MDrv_DMD_SSPI_RIU_Write8(0x0950, 0x00);
2810 MDrv_DMD_SSPI_RIU_Write8(0x0951, 0x00);
2811 //4. DMD51 interrupt by PM51 (Option)
2812 //SSPI_RIU_W, addr:0x3482, data:0x0200
2813 MDrv_DMD_SSPI_RIU_Write8(0x3482, 0x00);
2814 MDrv_DMD_SSPI_RIU_Write8(0x3483, 0x02);
2815 //5. Enable program sram clock
2816
2817
2818
2819
2820 #if(0)
2821 /* bryan mark test for SPI
2822 //b. SSPI_RIU_W, addr:0x0916, data:0x1c30 //xtali
2823 MDrv_DMD_SSPI_RIU_Write8(0x0916,0x30);
2824 MDrv_DMD_SSPI_RIU_Write8(0x0917,0x1C);
2825 //SSPI_RIU_W, addr:0x0916, data:0x1c20 //[5]deglitch
2826 MDrv_DMD_SSPI_RIU_Write8(0x0916,0x20);
2827 MDrv_DMD_SSPI_RIU_Write8(0x0917,0x1c);
2828 */
2829 #else
2830 //b. SSPI_RIU_W, addr:0x0916, data:0x1c30 //xtali
2831 MDrv_DMD_SSPI_RIU_Write8(0x0916,0x00);
2832 MDrv_DMD_SSPI_RIU_Write8(0x0917,0x00);
2833 #endif
2834
2835 //6. Release dmd_mcu periphal rst (All/Single)
2836 //SSPI_RIU_W, addr:0x3486, data:0x0000 (dmd0)
2837
2838 //load all demod
2839 MDrv_DMD_SSPI_RIU_Write8(0x3486,0x00);
2840 MDrv_DMD_SSPI_RIU_Write8(0x3487,0x00);
2841 MDrv_DMD_SSPI_RIU_Write8(0x34a6,0x00);
2842 MDrv_DMD_SSPI_RIU_Write8(0x34a7,0x00);
2843
2844 u32Addr = 0x80000000;//SRAM_BASE<<16;
2845 bRet &= MDrv_DMD_SSPI_MIU_Writes(u32Addr, u8_ptr, data_length);
2846
2847 MDrv_DMD_SSPI_RIU_Write8(0x0974, 0x00);
2848 MDrv_DMD_SSPI_RIU_Write8(0x0975, 0x00);//0x01
2849
2850 //MDrv_DMD_SSPI_RIU_Write8(0x0919, 0x00);
2851
2852 MDrv_DMD_SSPI_RIU_Write8(0x3480, 0x00);
2853 MDrv_DMD_SSPI_RIU_Write8(0x3481, 0x01);
2854 MDrv_DMD_SSPI_RIU_Write8(0x34A0, 0x00);
2855 MDrv_DMD_SSPI_RIU_Write8(0x34A1, 0x01);
2856
2857
2858 return bRet;
2859 }
2860
MDrv_DMD_MSB201X_Init(MS_U8 devID,MS_U8 u8DemodIndex,sDMD_MSB201X_InitData * pDMD_MSB201X_InitData,MS_U32 u32InitDataLen)2861 MS_BOOL MDrv_DMD_MSB201X_Init(MS_U8 devID, MS_U8 u8DemodIndex, sDMD_MSB201X_InitData *pDMD_MSB201X_InitData, MS_U32 u32InitDataLen)
2862 {
2863 MS_U8 idx = 0, u8Mask = 0, u8RegWrite = 0, u8Channel = 0;
2864 MS_U16 u16DspAddr = 0;
2865 MS_U8 idx2 = 0;
2866 MS_U8 u8Data;
2867 MS_U8 *code_ptr;
2868 MS_U16 code_size;
2869
2870 _MDrv_DMD_MSB201X_Variable_alloc();
2871 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
2872
2873 DMD_LOCK();
2874
2875 if ( sizeof(sDMD_MSB201X_InitData) == u32InitDataLen)
2876 {
2877 memcpy(&pDemod->_sDMD_MSB201X_InitData, pDMD_MSB201X_InitData, u32InitDataLen);
2878 }
2879 else
2880 {
2881 DMD_DBG(printf("MDrv_DMD_MSB201X_Init input data structure incorrect\n"));
2882 //DMD_UNLOCK();
2883 return FALSE;
2884 }
2885
2886 pDemod->DSP_ReadWrite_Mode = E_MSB201X_I2C_READ_WRITE;
2887
2888
2889
2890 if(u8DemodIndex == ALL_DEMOD)
2891 {
2892 //for SPI communication
2893 if (pDemod->_sDMD_MSB201X_InitData.bEnableSPILoadCode &&
2894 pDemod->_sDMD_MSB201X_InitData.fpMSB201X_SPIPAD_En != NULL)
2895 {
2896 _MSB201X_I2C_CH_Reset(devID, 3);
2897 if (!MDrv_DMD_SSPI_Init(0))
2898 {
2899 printf("MDrv_DMD_MSB201X_Init Init MDrv_DMD_SSPI_Init Fail \n");
2900 }
2901 //add today
2902 pDemod->DSP_ReadWrite_Mode = E_MSB201X_I2C_READ_WRITE;
2903
2904
2905 MDrv_MasterSPI_CsPadConfig(0, 0xff);
2906 MDrv_MasterSPI_MaxClkConfig(0, 1);
2907 //switch SPI pad on demod side
2908 (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_SPIPAD_En)(TRUE);
2909 // ------enable to use TS_PAD as SSPI_PAD
2910 // [0:0] reg_en_sspi_pad
2911 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
2912 _MDrv_DMD_MSB201X_SetReg2Bytes(devID,0x100900 + (0x3b) * 2, 0x0002);
2913
2914
2915 /*
2916 //Turn off all pad in
2917 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x0900 + (0x28) * 2, 0x0000);
2918 //Transport Stream pad on
2919 _MDrv_DMD_MSB201X_SetReg2Bytes(devID, 0x0900 + (0x2d) * 2, 0x00ff);
2920 */
2921 // ------- MSPI protocol setting
2922 // [8] cpha
2923 // [9] cpol
2924 _MDrv_DMD_MSB201X_GetReg(devID,0x100900+(0x3a)*2+1,&u8Data);
2925 u8Data &= 0xFC;
2926 _MDrv_DMD_MSB201X_SetReg(devID,0x100900+(0x3a)*2+1, u8Data);
2927 // ------- MSPI driving setting
2928 _MDrv_DMD_MSB201X_SetReg2Bytes(devID,0x100900+(0x2c)*2, 0x07ff);
2929
2930
2931 _MDrv_DMD_MSB201X_SSPI_CFG_W(0x02,0x10);
2932
2933 _MDrv_DMD_MSB201X_InitClkgen(devID);
2934
2935 code_ptr = MSB201X_DVBC_table;
2936 code_size = sizeof(MSB201X_DVBC_table);
2937 _MSB201X_Demod_SPILoadAll(devID, ALL_DEMOD, code_ptr, code_size); //load demod FW code via SPI
2938
2939 //_MDrv_DMD_MSR1742_SetReg2Bytes(devID, 0x0900 + (0x3b) * 2, 0x0000);
2940 //(pDemod->_sDMD_MSR1742_InitData.fpMSR1742_SPIPAD_En)(FALSE);
2941
2942 //time_end = MsOS_GetSystemTime();
2943 //printf("=====Brown Demod SPI load code time = %d\n", (time_end-time_start));
2944 pDemod->DSP_ReadWrite_Mode = E_MSB201X_SPI_READ_WRITE;
2945
2946
2947
2948 }
2949 else
2950 {
2951 _MDrv_DMD_MSB201X_InitClkgen(devID);
2952 pDemod->_sDMD_MSB201X_InitData.bEnableSPILoadCode = FALSE;
2953 _MSB201X_Demod_LoadAll(devID, ALL_DEMOD); //load demod FW code
2954 pDemod->DSP_ReadWrite_Mode = E_MSB201X_I2C_READ_WRITE;
2955 }
2956
2957
2958 // Init DSP table for all channels
2959 for(idx = 0; idx < DEMOD_MAX_CHANNEL; idx++)
2960 {
2961 memcpy (&pDemod->DVBC_DSP_REG[idx][0],
2962 MSB201X_DVBC_DSPREG_TABLE ,
2963 sizeof(MSB201X_DVBC_DSPREG_TABLE));
2964
2965
2966
2967
2968
2969
2970
2971 for(idx2 = 0; idx2 < sizeof(MSB201X_DVBC_DSPREG_TABLE); idx2++)
2972 {
2973 _MDrv_DMD_MSB201X_SetDSPReg(devID, idx, idx2, MSB201X_DVBC_DSPREG_TABLE[idx2]);
2974
2975 }
2976
2977
2978 }
2979
2980
2981
2982 }
2983 else
2984 {
2985 _MDrv_DMD_MSB201X_InitClkgen(devID);
2986 _MSB201X_Demod_LoadSingle(devID, u8DemodIndex); //load demod FW code
2987
2988
2989 memcpy (&pDemod->DVBC_DSP_REG[u8DemodIndex][0],
2990 MSB201X_DVBC_DSPREG_TABLE ,
2991 sizeof(MSB201X_DVBC_DSPREG_TABLE));
2992
2993
2994
2995 for(idx2 = 0; idx2 < sizeof(MSB201X_DVBC_DSPREG_TABLE); idx2++)
2996 {
2997 _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, idx2, MSB201X_DVBC_DSPREG_TABLE[idx2]);
2998 }
2999
3000 }
3001
3002 /* DSP table example :
3003 static MS_U8 u8DSPTable[] =
3004 {
3005 //addr_L add_H mask value demod_channel
3006 0x01, 00,
3007 0x16, 0x00, 0xff, 0xBB, 0, //FS_H 45.474M :0xB1 48M:0xBB
3008 0x15, 0x00, 0xff, 0x80, 0, //FS_L 45.474M :0xA2 48M:0x80
3009 };
3010 */
3011
3012 if (pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG!= NULL)
3013 {
3014
3015
3016 if(1 == pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG[0])
3017 {
3018 pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG += 2;
3019 for(idx = 0; idx < pDemod->_sDMD_MSB201X_InitData.DVBC_DSP_REG_Length-2; idx++)
3020 {
3021 u16DspAddr = *(pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG);
3022 pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG ++;
3023 u16DspAddr = (u16DspAddr) + (*(pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG)<<8);
3024 pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG ++;
3025 u8Mask = *(pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG);
3026 pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG ++;
3027 u8RegWrite = (*(pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG)) & u8Mask;
3028 pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG ++;
3029 u8Channel = *(pDemod->_sDMD_MSB201X_InitData.pDVBC_DSP_REG);
3030
3031 //pDemod->DVBC_DSP_REG[u8Channel][u16DspAddr] = u8RegWrite;
3032
3033 if(ALL_DEMOD == u8DemodIndex)
3034 _MDrv_DMD_MSB201X_SetDSPReg(devID, u8Channel, u16DspAddr, u8RegWrite);
3035 else if(u8Channel == u8DemodIndex)
3036 _MDrv_DMD_MSB201X_SetDSPReg(devID, u8Channel, u16DspAddr, u8RegWrite);
3037
3038 memcpy (&pDemod->DVBC_DSP_REG[u8Channel][u16DspAddr],
3039 &u8RegWrite ,
3040 1);
3041
3042 }
3043 }
3044 }
3045
3046
3047
3048 if(u8DemodIndex == ALL_DEMOD)
3049 {
3050 for(idx = 0; idx < DEMOD_MAX_CHANNEL; idx++)
3051 {
3052 // Demod active for all channel
3053 _MDrv_DMD_MSB201X_Active(devID, idx, TRUE);
3054 }
3055 }
3056 else
3057 {
3058 // Demod active for single channel
3059 _MDrv_DMD_MSB201X_Active(devID, u8DemodIndex, TRUE);
3060 }
3061
3062
3063 if (E_MSB201X_SPI_READ_WRITE==pDemod->DSP_ReadWrite_Mode)
3064 {
3065 //SPI function
3066 // ------disable to use TS_PAD as SSPI_PAD after load code
3067 // [0:0] reg_en_sspi_pad
3068 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
3069 pDemod->DSP_ReadWrite_Mode = E_MSB201X_I2C_READ_WRITE;
3070 //_MDrv_DMD_MSB201X_SetReg2Bytes(devID,0x100900 + (0x3b) * 2, 0x0001);
3071 _MDrv_DMD_MSB201X_SetReg2Bytes(devID,0x100900 + (0x3b) * 2, 0x0000);
3072 (pDemod->_sDMD_MSB201X_InitData.fpMSB201X_SPIPAD_En)(FALSE);
3073
3074 }
3075
3076 DMD_UNLOCK();
3077 return TRUE;
3078 }
3079
3080
_MDrv_DMD_MSB201X_GetRFLevel(MS_U8 devID,MS_U8 u8DemodIndex,float * fRFPowerDbmResult,float fRFPowerDbm,sDMD_MSB201X_IFAGC_SSI * pIfagcSsi_LoRef,MS_U16 u16IfagcSsi_LoRef_Size,sDMD_MSB201X_IFAGC_ERR * pIfagcErr_LoRef,MS_U16 u16IfagcErr_LoRef_Size)3081 MS_BOOL _MDrv_DMD_MSB201X_GetRFLevel(MS_U8 devID, MS_U8 u8DemodIndex, float *fRFPowerDbmResult, float fRFPowerDbm,
3082 sDMD_MSB201X_IFAGC_SSI *pIfagcSsi_LoRef, MS_U16 u16IfagcSsi_LoRef_Size,
3083 sDMD_MSB201X_IFAGC_ERR *pIfagcErr_LoRef, MS_U16 u16IfagcErr_LoRef_Size)
3084 {
3085 sDMD_MSB201X_IFAGC_SSI *ifagc_ssi;
3086 sDMD_MSB201X_IFAGC_ERR *ifagc_err;
3087 float ch_power_db=0.0f;
3088 float ch_power_rf=0.0f;
3089 float ch_power_if=0.0f, ch_power_ifa = 0.0f, ch_power_ifb =0.0f;
3090 float ch_power_takeover=0.0f;
3091 MS_U16 if_agc_err = 0;
3092 MS_U8 status = true;
3093 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0,if_agc_val =0, if_agc_vala =0, if_agc_valb =0, if_agc_val_lsb =0, i;
3094 MS_U8 ssi_tbl_len = 0, err_tbl_len = 0;
3095
3096 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
3097 _MSB201X_I2C_CH_Reset(devID, 5);
3098 if (pIfagcSsi_LoRef !=NULL)
3099 {
3100 ch_power_rf = fRFPowerDbm;
3101 // get IFAGC status
3102 {
3103 #ifdef MS_DEBUG
3104 printf("AGC_REF = %d\n", (MS_U16)reg_tmp);
3105 #endif
3106
3107 ifagc_ssi = pIfagcSsi_LoRef;
3108 ssi_tbl_len = u16IfagcSsi_LoRef_Size;
3109 ifagc_err = pIfagcErr_LoRef;
3110 err_tbl_len = u16IfagcErr_LoRef_Size;
3111
3112 // bank 5 0x24 [15:0] reg_agc_gain2_out
3113 // use only high byte value
3114
3115 // select IF gain to read
3116 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x16, 0x03);
3117 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x03, ®_frz);
3118 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x03, reg_frz | 0x80);
3119 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x19, ®_tmp);
3120 if_agc_val = reg_tmp;
3121 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x18, ®_tmp);
3122 if_agc_val_lsb = reg_tmp;
3123 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x03, reg_frz);
3124 #ifdef MS_DEBUG
3125 printf("SSI_IFAGC_H = 0x%x 0x%x\n", if_agc_val,if_agc_val_lsb);
3126 #endif
3127
3128 ch_power_if=ifagc_ssi[0].power_db;
3129 if (if_agc_val >=ifagc_ssi[0].agc_val)
3130 {
3131 for(i = 1; i < ssi_tbl_len; i++)
3132 {
3133 if (if_agc_val < ifagc_ssi[i].agc_val)
3134 {
3135 if_agc_valb = ifagc_ssi[i].agc_val;
3136 ch_power_ifb = ifagc_ssi[i].power_db;
3137
3138 i--;
3139 if_agc_vala = ifagc_ssi[i].agc_val;
3140 ch_power_ifa=ifagc_ssi[i].power_db;
3141 while ((i>1) && (if_agc_vala==ifagc_ssi[i-1].agc_val))
3142 {
3143 ch_power_ifa=ifagc_ssi[i-1].power_db;
3144 i--;
3145 }
3146 ch_power_if = ch_power_ifa+(ch_power_ifb-ch_power_ifa)*(float)((if_agc_val-if_agc_vala)*256+if_agc_val_lsb)/((if_agc_valb-if_agc_vala)*256);
3147 break;
3148 }
3149 }
3150 }
3151 #ifdef MS_DEBUG
3152 printf("if prev %f %x\n", ch_power_ifa, if_agc_vala);
3153 printf("if next %f %x\n", ch_power_ifb, if_agc_valb);
3154 #endif
3155
3156 for(i = 0; i < ssi_tbl_len; i++)
3157 {
3158 if (ifagc_ssi[i].agc_val <= ifagc_ssi[i+1].agc_val)
3159 {
3160 ch_power_takeover = ifagc_ssi[i+1].power_db;
3161 break;
3162 }
3163 }
3164
3165 // Only use IFAGC
3166 if(fRFPowerDbm >= 200.0)
3167 {
3168 ch_power_takeover = 100.0;
3169 }
3170
3171 #ifdef MS_DEBUG
3172 printf("ch_power_rf = %f\n", ch_power_rf);
3173 printf("ch_power_if = %f\n", ch_power_if);
3174 printf("ch_power_takeover = %f\n", ch_power_takeover);
3175 #endif
3176
3177 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_rf : ch_power_if;
3178
3179 if(ch_power_rf > (ch_power_takeover + 0.5))
3180 {
3181 ch_power_db = ch_power_rf;
3182 }
3183 else if(ch_power_if < (ch_power_takeover - 0.5))
3184 {
3185 ch_power_db = ch_power_if;
3186 }
3187 else
3188 {
3189 ch_power_db = (ch_power_if + ch_power_rf)/2;
3190 }
3191
3192 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_if : ch_power_rf;
3193
3194 ///////// IF-AGC Error for Add. Attnuation /////////////
3195 if(if_agc_val == 0xff)
3196 {
3197 #if 0
3198 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
3199 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, ®_tmp);
3200 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (reg_tmp&0xf0));
3201 #endif
3202 #endif
3203 // bank 5 0x04 [15] reg_tdp_lat
3204 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x16, 0x00);
3205 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x03, ®_frz);
3206 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x03, reg_frz | 0x80);
3207 #if 0
3208 //#if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
3209 // bank 5 0x2c [9:0] reg_agc_error
3210 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, ®_tmp);
3211 // if_agc_err = reg_tmp & 0x03;
3212 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, ®_tmp2);
3213 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
3214 //#else
3215 #endif
3216 // bank 5 0x2c [9:0] reg_agc_error
3217 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x19, ®_tmp);
3218 // if_agc_err = reg_tmp & 0x03;
3219 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x18, ®_tmp2);
3220 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
3221 //#endif
3222
3223 if(reg_tmp&0x2)
3224 {
3225 if_agc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
3226 }
3227 else
3228 {
3229 if_agc_err = reg_tmp<<8|reg_tmp2;
3230 }
3231
3232 // release latch
3233 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x03, reg_frz);
3234
3235 for(i = 0; i < err_tbl_len; i++)
3236 {
3237 if ( if_agc_err <= ifagc_err[i].agc_err ) // signed char comparison
3238 {
3239 ch_power_db += ifagc_err[i].attn_db;
3240 break;
3241 }
3242 }
3243 #ifdef MS_DEBUG
3244 printf("if_agc_err = 0x%x\n", if_agc_err);
3245 #endif
3246 }
3247
3248 // BY 20110812 temporaily remove ch_power_db += SIGNAL_LEVEL_OFFSET;
3249 }
3250 }
3251 else
3252 {
3253 #ifdef MS_DEBUG
3254 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
3255 {
3256 printf("Error!! please add AGC table\n");
3257 }
3258 #endif
3259 ch_power_db = fRFPowerDbm;
3260 }
3261 *fRFPowerDbmResult=ch_power_db;
3262 return status;
3263 }
3264
3265 //MS_BOOL MDrv_DMD_MSB201X_SPI_Pre_Setting(MS_U8 devID, sDMD_MSB201X_InitData *pDMD_MSB201X_InitData)
MDrv_DMD_MSB201X_SPI_Pre_Setting(MS_U8 devID)3266 MS_BOOL MDrv_DMD_MSB201X_SPI_Pre_Setting(MS_U8 devID)
3267 {
3268 // tMSB201X_Demod_Data *pDemod;
3269 MS_U8 i;
3270 tMSB201X_Demod_Data *pMSB201X = NULL;
3271 {
3272 pstDemod = (tMSB201X_Demod_Data *)malloc(sizeof(tMSB201X_Demod_Data) * DEMOD_MAX_INSTANCE);
3273 if(NULL == pstDemod)
3274 {
3275 return FALSE;
3276 }
3277 else
3278 {
3279 for(i=0; i< DEMOD_MAX_INSTANCE; i++)
3280 {
3281 pMSB201X = (pstDemod + i);
3282 memcpy(pMSB201X, &MSB201X_Demod_Init, sizeof(tMSB201X_Demod_Data));
3283 }
3284 }
3285 }
3286
3287 pMSB201X = pstDemod + devID;
3288 //pMSB201X->_sDMD_MSB201X_InitData.fpMSB201X_I2C_Access = pDMD_MSB201X_InitData->fpMSB201X_I2C_Access;
3289 pMSB201X->DSP_ReadWrite_Mode = E_MSB201X_SPI_READ_WRITE;
3290
3291 // pDemod = DEMOD_GET_ACTIVE_NODE(devID);
3292
3293 // _MSB201X_I2C_CH_Reset(devID, 3);
3294
3295 //pMSB201X->DSP_ReadWrite_Mode = E_MSB201X_SPI_READ_WRITE; //for inseting the SPI and I2C mode
3296
3297 // DMD HK init clk start
3298 // -------------------------------------------------------------------
3299 // Initialize DMD_ANA_MISC
3300 // -------------------------------------------------------------------
3301
3302 // Koln add
3303 // [0] reg_pd_ldo25i_ana // 2.5v LDO power down
3304 // [1] reg_pd_ldo25q_ana // 2.5v LDO power down
3305 // [2] reg_pd_ldo25i_dig // 2.5v LDO power down
3306 // [3] reg_pd_ldo25q_dig // 2.5v LDO power down
3307 // [4] reg_pd_ldo25_ref // 2.5v LDO power down
3308 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h53, 2'b01, 16'h0000);
3309 //wreg 4106 0x53 0x0000
3310 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x53)*2 , 0x00);
3311 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x53)*2+1, 0x00);
3312
3313 // [0] reg_tst_ldo25i
3314 // [1] reg_tst_ldo25q
3315 // [5:4] reg_tst_ldo25i_selfb
3316 // [7:6] reg_tst_ldo25q_selfb
3317 // [8] reg_pd_dm2p5ldoi = 1'b0
3318 // [9] reg_pd_dm2p5ldoq = 1'b0
3319 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h4f, 2'b11, 16'h0000);
3320 // wreg 4106 0x4f 0x0000
3321 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4f)*2 , 0x00);
3322 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4f)*2+1, 0x00);
3323
3324 // [0] reg_tst_ldo11_clk
3325 // [1] reg_tst_ldo26
3326 // [2] reg_tst_ldo11_cmp
3327 // [3] reg_pd_dm1p1ldo_clk = 1'b0
3328 // [4] reg_pd_dm1p1ldo_cmp = 1'b0
3329 // [6] reg_tst_ldo26_selfb
3330 // [7] reg_pd_dm2p6ldo = 1'b0
3331 // [9:8] reg_tst_ldo11_cmp_selfb
3332 // [11:10] reg_tst_ldo11_clk_selfb
3333 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h4e, 2'b11, 16'h0000);
3334 //wreg 4106 0x4e 0x0000
3335 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4e)*2 , 0x00);
3336 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x4e)*2+1, 0x00);
3337
3338
3339 // [1:0] reg_mpll_loop_div_first feedback divider 00:div by 1 01:div by 2 10:div by 4 11:div by 8
3340 // [15:8] reg_mpll_loop_div_second feedback divider, div by binary data number
3341 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h33, 2'b11, 16'h1201); // Loop divider ; VCO = 24*(2^2)*9 = 864
3342 // wreg 4106 0x33 0x1201
3343 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x33)*2 , 0x01);
3344 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x33)*2+1, 0x12);
3345
3346 // [2:0] reg_mpll_ictrl charge pump current control
3347 // [3] reg_mpll_in_sel 1.8V or 3.3V reference clock domain select (1'b0=0==>3.3 V reference clock domain)
3348 // [4] reg_mpll_xtal2adc_sel select the XTAL clock bypass to MPLL_ADC_CLK
3349 // [5] reg_mpll_xtal2next_pll_sel crystal clock bypass to next PLL select
3350 // [6] reg_mpll_vco_offset set VCO initial offset frequency
3351 // [7] reg_mpll_pd gated reference clock and power down PLL analog_3v: 1=power down
3352 // [8] reg_xtal_en XTAL enable register; 1: enable
3353 // [10:9] reg_xtal_sel XTAL driven strength select.
3354 // [11] reg_mpll_porst MPLL input power on reset, connect to reg as MPLL_RESET
3355 // [12] reg_mpll_reset PLL software reset; 1:reset
3356 // [13] reg_pd_dmpll_clk XTAL to MPLL clock reference power down
3357 // [14] reg_pd_3p3_1 XTAL to CLK_24M_3P3_1 power down
3358 // [15] reg_pd_3p3_2 XTAL to CLK_24M_3P3_2 power down
3359 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h35, 2'b11, 16'h1803); // MPLL reset
3360 //wreg 4106 0x35 0x1803
3361 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2 , 0x03);
3362 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2+1, 0x18);
3363
3364 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h35, 2'b11, 16'h0003); // release MPLl reset
3365 //wreg 4106 0x35 0x0003
3366 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2 , 0x03);
3367 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x35)*2+1, 0x00);
3368
3369 // [0] reg_mpll_clk_dp_pd dummy
3370 // [1] reg_adc_clk_pd ADC output clock power down
3371 // [2] reg_mpll_div2_pd MPLL_DIV2 power down
3372 // [3] reg_mpll_div3_pd MPLL_DIV3 power down
3373 // [4] reg_mpll_div4_pd MPLL_DIV4 power down
3374 // [5] reg_mpll_div8_pd MPLL_DIV8 power down
3375 // [6] reg_mpll_div10_pd MPLL_DIV10 power down
3376 // [13:8] reg_mpll_adc_div_sel select the ADC clock divide ratio,ADC clk=XTAL_IN
3377 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h30, 2'b11, 16'h1e00); // divide ADC clock to 28.8Mhz = 24*36/30
3378 //wreg 4106 0x30 0x1e00
3379 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x30)*2 , 0x00);
3380 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x30)*2+1, 0x1e);
3381
3382
3383 //$display("--------------------------------------");
3384 //$display("Initialize ADC I/Q");
3385 //$display("--------------------------------------");
3386
3387 // [0] Q channel ADC power down
3388 // [1] I channel ADC power down
3389 // [2] Q channel clamp enable. 0:enable, 1:disable
3390 // [3] I channel clamp enable. 0:enable, 1:disable
3391 // [6:4] I channel input mux control;
3392 // 3'b000=I channel ADC calibration mode input
3393 // 3'b001=VIF signal from VIFPGA
3394 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
3395 // all the other combination are only for test mode, don't use without understanding.
3396 // [10:8] Q channel input mux control;
3397 // 3'b000=Q channel ADC calibration mode input
3398 // 3'b001=VIF signal from VIFPGA 3'b010 = SSIF signal from PAD_SIFP(M)
3399 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
3400 // all the other combination are only for test mode, don't use without understanding.
3401 // [12] ADC I,Q swap enable; 1: swap
3402 // [13] ADC clock out select; 1: ADC_CLKQ
3403 // [14] ADC linear calibration bypass enable; 1:enable
3404 // [15] ADC internal 1.2v regulator control always 0 in T3
3405 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h01, 2'b11, 16'h0440); // Set IMUXS QMUXS
3406 //wreg 4106 0x01 0x0440
3407 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x01)*2 , 0x40);
3408 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x01)*2+1, 0x04);
3409
3410 // [2:0] reg_imuxs_s
3411 // [6:4] reg_qmuxs_s
3412 // [9:8] reg_iclpstr_s
3413 // [13:12] reg_qclpstr_s
3414 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h45, 2'b01, 16'h0000); // Set IMUXS QMUXS
3415 //wreg 4106 0x45 0x0000
3416 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x45)*2 , 0x00);
3417 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x45)*2+1, 0x00);
3418
3419
3420 // [0] Channel I ADC power down: 1=power dwon
3421 // [1] Channel Q ADC power down: 1=power dwon
3422 // [2] power down clamp buffer for test mode
3423 // [3] change ADC reference voltage for SSIF
3424 // [6:4] ADC source bias current control
3425 // [9:8] XTAL receiver amp gain
3426 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h0c, 2'b11, 16'h0000); // Set enable ADC clock
3427 // wreg 4106 0x0c 0x0000
3428 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0c)*2 , 0x00);
3429 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0c)*2+1, 0x00);
3430
3431
3432 // [0] reg_linear_cal_start_q 0 0 1
3433 // [1] reg_linear_cal_mode_q 0 0 1
3434 // [2] reg_linear_cal_en_q 0 0 1
3435 // [3] reg_linear_cal_code0_oren_q 0 0 1
3436 // [6:4] reg_linear_cal_status_sel_q 2 0 3
3437 // [7] reg_pwdn_vcalbuf 0 0 1
3438
3439 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h0f, 2'b01, 16'h0000); // Set reg_pwdn_vcalbuf = 1'b0
3440 // wreg 4106 0x0f 0x0000
3441 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0f)*2 , 0x00);
3442 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0f)*2+1, 0x00);
3443
3444
3445 // [3:0] clamp voltage control
3446 // 3'b000 = 0.7v
3447 // 3'b001 = 0.75v
3448 // 3'b010 = 0.5v
3449 // 3'b011 = 0.4v
3450 // 3'b100 = 0.8v
3451 // 3'b101 = 0.9v
3452 // 3'b110 = 0.65v
3453 // 3'b111 = 0.60v
3454 // [4] REFERENCE power down
3455 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h20, 2'b11, 16'h0000); // Disable PWDN_REF
3456 //wreg 4106 0x20 0x0000
3457 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x20)*2 , 0x00);
3458 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x20)*2+1, 0x00);
3459 // Set ADC gain is 1
3460 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h0b, 2'b11, 16'h0505);
3461 //wreg 4106 0x0b 0x0505
3462 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0b)*2 , 0x05);
3463 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x0b)*2+1, 0x05);
3464
3465 // Disable ADC Sign bit
3466 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h2e, 2'b11, 16'h0000);
3467 //wreg 4106 0x2e 0x0000
3468 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2e)*2 , 0x00);
3469 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2e)*2+1, 0x00);
3470
3471 // ADC I channel offset
3472 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h2a, 2'b11, 16'h0c00);
3473 //wreg 4106 0x2a 0x0c00
3474 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2a)*2 , 0x00);
3475 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2a)*2+1, 0x0c);
3476
3477 // ADC Q channel offset
3478 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h2b, 2'b11, 16'h0c00);
3479 //wreg 4106 0x2b 0x0c00
3480 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2b)*2 , 0x00);
3481 _MDrv_DMD_MSB201X_SetReg(devID, 0x100A00 + (0x2b)*2+1, 0x0c);
3482
3483
3484 // [5:0]reg_ckg_mcu
3485 // [6] reg_power_good_mask
3486 // [11:8]reg_ckg_inner
3487 // [15:12]reg_ckg_iicm1
3488 // `RIU_W((`RIUBASE_TOP>>1)+7'h0b, 2'b11, 16'h0430);
3489 //wreg 4105 0x0b 0x0030
3490 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2b)*2 , 0x30);
3491 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x2b)*2+1, 0x00);
3492
3493
3494 // [1:0]reg_chanout_sel
3495 // [2] reg_iq_filter_enable = 1
3496 // [3] reg_iq_filter_sel
3497 // [5:4]reg_adc_debug_clk_sel
3498 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h17, 2'b11, 16'h0004);
3499 //wreg 4106 0x17 0x0004
3500 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x17)*2 , 0x04);
3501 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x17)*2+1, 0x00);
3502
3503
3504
3505 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h51, 2'b01, 16'h0081); // 2 channel DVBC
3506 //wreg 4106 0x51 0x0081
3507 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2 , 0x81);
3508 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2+1, 0x00);
3509
3510
3511 // -------------------------------------------------------------------
3512 // Release clock gating
3513 // -------------------------------------------------------------------
3514 //$display("--------------------------------------");
3515 //$display("Release clock gating");
3516 //$display("--------------------------------------");
3517
3518 // [0] reg_xtal_en
3519 // [9:8] reg_clk_pd_iic
3520 // [10] reg_clk_pd_all
3521 // `RIU_W((`RIUBASE_TOP>>1)+7'h09, 2'b11, 16'h0101);
3522 //wreg 4105 0x09 0x0101
3523 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2 , 0x01);
3524 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2+1, 0x01);
3525
3526 // [3:0] reg_ckg_adcd
3527 // [7:4] reg_ckg_sadc
3528 // [11:8] reg_ckg_iicm
3529 // [13:12] reg_ckg_sbus
3530 // `RIU_W((`RIUBASE_TOP>>1)+7'h0a, 2'b11, 16'h0000);
3531 //wreg 4105 0x0a 0x0000
3532 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2 , 0x00);
3533 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2+1, 0x00);
3534
3535 // [5:0] reg_ckg_mcu
3536 // [6] reg_ckg_live
3537 // [11:8] reg_ckg_inner
3538 // `RIU_W((`RIUBASE_TOP>>1)+7'h0b, 2'b11, 16'h0030);
3539 // wreg 4105 0x0b 0x0030
3540 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0b)*2 , 0x00);
3541 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0b)*2+1, 0x00);
3542
3543
3544 // @0x0912
3545 // [3:0] reg_ckg_dvbtm_ts
3546 // [4] reg_dvbtm_ts_out_mode
3547 // [5] reg_dvbtm_ts_clk_pol
3548 // [15:8] reg_dvbtm_ts_clk_divnum
3549 // `RIU_W((`RIUBASE_TOP>>1)+7'h12, 2'b11, 16'h1418);
3550 //wreg 4105 0x12 0x1418
3551 //_MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 , 0x18);
3552 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2 , 0x10);
3553 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x12)*2+1, 0x14);
3554
3555 // @0x0913
3556 // [5:0] reg_ckg_spi
3557 // `RIU_W((`RIUBASE_TOP>>1)+7'h13, 2'b11, 16'h0020);
3558 //wreg 4105 0x13 0x0020
3559 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x13)*2 , 0x20);
3560 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x13)*2+1, 0x00);
3561
3562
3563 // @0x091b
3564 // [10:8] reg_ckg_syn_miu
3565 // [14:12] reg_ckg_syn_ts
3566 // `RIU_W((`RIUBASE_TOP>>1)+7'h1b, 2'b11, 16'h0000);
3567 // wreg 4105 0x1b 0x0000
3568 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1b)*2 , 0x00);
3569 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1b)*2+1, 0x00);
3570
3571
3572
3573 // @0x091c
3574 // [4:0] reg_ckg_bist
3575 // [11:8] reg_ckg_adcd_d2
3576 // `RIU_W((`RIUBASE_TOP>>1)+7'h1c, 2'b11, 16'h0000);
3577 //wreg 4105 0x1c 0x0000
3578
3579 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1c)*2 , 0x00);
3580 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x1c)*2+1, 0x00);
3581
3582
3583 // [1:0] reg_iicm_pad_sel
3584 // [4] reg_i2c_sbpm_en
3585 // [12:8] reg_i2c_sbpm_idle_num
3586 // `RIU_W((`RIUBASE_TOP>>1)+7'h08, 2'b01, 16'h0a01);
3587 //wreg 4105 0x08 0x0a01
3588
3589 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x08)*2 , 0x01);
3590 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x08)*2+1, 0x0a);
3591
3592 // [8] reg_turn_off_pad
3593 // `RIU_W((`RIUBASE_TOP>>1)+7'h28, 2'b10, 16'h0000);
3594 // wreg 4105 0x28 0x0000
3595 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x28)*2 , 0x00);
3596 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x28)*2+1, 0x00);
3597
3598
3599
3600
3601 //$display("--------------------------------------");
3602 //$display("Initialize Transport Stream synthesizer and APLL");
3603 //$display("--------------------------------------");
3604
3605 // ////////////////////////////////////////////////////
3606 //
3607 // According to analog APLL designer's suggest:
3608 // APLL_LOOP_DIV = 5'b00000
3609 // apll input frequency range 54MHz~106MHz synthesizer clock
3610 // so apll_1x_out = synthesizer_out * (apll_ts_mode + 1)
3611 //
3612 // => apll_1x_out should 40Mhz ~ 130Mhz
3613 //
3614 // Current setting:
3615 // apll_1x_out = (432/8.0) * (1+1) = 108MHz
3616 // choose reg_ckg_ts_apll_div[2:0] = 3'd4
3617 // ts_clk_apll_div = 108/(2^4) = 6.75MHz
3618 //
3619 // ////////////////////////////////////////////////////
3620
3621
3622 // [15:0] reg_synth_set[15: 0]
3623 // [ 7:0] reg_synth_set[23:16]
3624 // `RIU_W((`RIUBASE_TOP>>1)+7'h51, 2'b11, 16'h0000);
3625 //wreg 4105 0x51 0x0000
3626 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x51)*2 , 0x00);
3627 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x51)*2+1, 0x00);
3628 // `RIU_W((`RIUBASE_TOP>>1)+7'h52, 2'b11, 16'h0040);
3629 //wreg 4105 0x52 0x0040
3630 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x52)*2 , 0x40);
3631 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x52)*2+1, 0x00);
3632
3633
3634 // [0] reg_synth_reset
3635 // [1] reg_synth_ssc_en
3636 // [2] reg_synth_ssc_mode
3637 // [4] reg_synth_sld
3638 // `RIU_W((`RIUBASE_TOP>>1)+7'h50, 2'b01, 16'h0010);
3639 //wreg 4105 0x50 0x0010
3640
3641 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x50)*2 , 0x10);
3642 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x50)*2+1, 0x00);
3643
3644 // #10_000;
3645 //delay 0 ****
3646
3647
3648 // [1:0] reg_apll_loop_div_first
3649 // [15:8] reg_apll_loop_div_second
3650 // `RIU_W((`RIUBASE_TOP>>1)+7'h57, 2'b11, 16'h0000);
3651 //wreg 4105 0x57 0x0000
3652
3653 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x57)*2 , 0x00);
3654 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x57)*2+1, 0x00);
3655
3656
3657 // [0] reg_apll_pd
3658 // [1] reg_apll_reset
3659 // [2] reg_apll_porst
3660 // [3] reg_apll_vco_offset
3661 // [4] reg_apll_en_ts
3662 // [5] reg_apll_endcc
3663 // [6] reg_apll_clkin_sel
3664 // [8] reg_apll_ts_mode
3665 // `RIU_W((`RIUBASE_TOP>>1)+7'h55, 2'b11, 16'h0100);
3666 //wreg 4105 0x55 0x0100
3667 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2 , 0x00);
3668 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2+1, 0x01);
3669 // `RIU_W((`RIUBASE_TOP>>1)+7'h55, 2'b01, 16'h0110);
3670 //wreg 4105 0x55 0x0110
3671 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2 , 0x10);
3672 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x55)*2+1, 0x01);
3673
3674 // [16:0] reg_apll_test
3675 // `RIU_W((`RIUBASE_TOP>>1)+7'h59, 2'b11, 16'h0000);
3676 //wreg 4105 0x59 0x0000
3677 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x59)*2 , 0x00);
3678 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x59)*2+1, 0x00);
3679
3680 // 0x0920
3681 // [3:0] reg_ckg_ts_apll_div[2:0]
3682 // `RIU_W((`RIUBASE_TOP>>1)+7'h20, 2'b01, 16'h0004);
3683 //wreg 4105 0x20 0x0004
3684 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x20)*2 , 0x04);
3685 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x20)*2+1, 0x00);
3686
3687 // Following register control by reg_CLKGEN1
3688 // reg_ckg_atsc_dvb_div_sel, (clkgen0)
3689 // reg_ckg_atsc_dvbtc_ts_inv, (clkgen0)
3690 // reg_ckg_atsc_ts, (clkgen0)
3691 // reg_ckg_demod_test_in_en, (clkgen0, clkgen_dmd)
3692 // reg_ckg_dmdmcu, (clkgen0)
3693 // reg_ckg_dvbtc_adc, (clkgen0, clkgen_dmd)
3694 // reg_ckg_dvbtc_ts, (clkgen0)
3695 // reg_ckg_dvbtm_ts_divnum, (clkgen0)
3696 // reg_ckg_dvbtm_ts_out_mode, (clkgen0)
3697 // reg_ckg_vifdbb_dac, (clkgen0, clkgen_dmd)
3698 // reg_ckg_vifdbb_vdac, (clkgen0, clkgen_dmd)
3699
3700
3701
3702 //$display("Set register at TOP (clkgen) ......");
3703
3704 // { 1'b0, reg_ckg_adcd1[3:0], reg_clk_pd_all, 1'b0, reg_clk_pd_iic, 7'h0, reg_xtal_en }
3705 // `RIU_W((`RIUBASE_TOP>>1)+7'h09, 2'b10, 16'h0000);
3706 //wreg 4105 0x09 0x0000
3707 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2 , 0x00);
3708 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x09)*2+1, 0x00);
3709 // { 2'h0, reg_ckg_sbus[1:0], reg_ckg_iicm[3:0], reg_ckg_sadc[3:0], reg_ckg_adcd[3:0] }
3710 // `RIU_W((`RIUBASE_TOP>>1)+7'h0a, 2'b01, 16'h1110);
3711 // wreg 4105 0x0a 0x1110
3712 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2 , 0x10);
3713 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0a)*2+1, 0x11);
3714
3715 // { reg_ckg_demod_mpll[3:0], 4'h0, reg_ckg_dmdxtali[3:0], reg_ckg_dmdmcu[3:0] }
3716 // `RIU_W((`RIUBASE_TOP>>1)+7'h0d, 2'b10, 16'h0000);
3717 //wreg 4105 0x0d 0x0000
3718 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0d)*2 , 0x00);
3719 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x0d)*2+1, 0x00);
3720
3721 // DVBC : 24*36/30=28.8 MHz
3722 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h33, 2'b11, 16'h1201); // Set MPLL_LOOP_DIV_FIRST and SECOND
3723 //wreg 4106 0x33 0x1201
3724 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x33)*2 , 0x01);
3725 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x33)*2+1, 0x12);
3726 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h30, 2'b11, 16'h1e00+16'h1); // Set MPLL_ADC_DIV_SEL
3727
3728 // reg_ckg_ts_0 = 4'd0;
3729 // reg_ckg_ts_1 = 4'd0;
3730 // `RIU_W((`RIUBASE_TOP>>1)+7'h23, 2'b01, 16'h0000);
3731 //wreg 4105 0x23 0x0000
3732 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x23)*2 , 0x00);
3733 _MDrv_DMD_MSB201X_SetReg(devID, 0x100900 + (0x23)*2+1, 0x00);
3734
3735 //$display("=================================================");
3736 //$display("start demod atop ADC setting ......");
3737 //$display("=================================================");
3738
3739 // { 8'h0, reg_ana_setting_sel[3:0], 3'h0, reg_ana_setting_enable } )
3740 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h51, 2'b01, 16'h0081);
3741 //wreg 4106 0x51 0x0081
3742 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2 , 0x81);
3743 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x51)*2+1, 0x00);
3744
3745 //if agc enable
3746 //wreg 4106 0x18 0x0101
3747 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x18)*2 , 0x01);
3748 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x18)*2+1, 0x01);
3749
3750 //wreg 4106 0x30 0x1200
3751 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x30)*2 , 0x00);
3752 _MDrv_DMD_MSB201X_SetReg(devID, 0x100a00 + (0x30)*2+1, 0x12);
3753
3754
3755 free(pstDemod);
3756 pstDemod=NULL;
3757 return TRUE;
3758 }
3759
MDrv_DMD_MSB201X_GetRFLevel(MS_U8 devID,MS_U8 u8DemodIndex,float * fRFPowerDbmResult,float fRFPowerDbm)3760 MS_BOOL MDrv_DMD_MSB201X_GetRFLevel(MS_U8 devID, MS_U8 u8DemodIndex, float *fRFPowerDbmResult, float fRFPowerDbm)
3761 {
3762 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
3763
3764 DMD_LOCK();
3765
3766 _MDrv_DMD_MSB201X_GetRFLevel(devID, u8DemodIndex, fRFPowerDbmResult, fRFPowerDbm,
3767 pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].pIFAGC_SSI, pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].IFAGC_SSI_Length,
3768 pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].pIFAGC_ERR, pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].IFAGC_ERR_Length);
3769
3770 DMD_UNLOCK();
3771
3772 return TRUE;
3773 }
3774
_MDrv_DMD_MSB201X_GetLock(MS_U8 devID,MS_U8 u8DemodIndex,eDMD_MSB201X_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)3775 MS_BOOL _MDrv_DMD_MSB201X_GetLock(MS_U8 devID, MS_U8 u8DemodIndex, eDMD_MSB201X_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
3776 {
3777 MS_U16 u16Address = 0;
3778 MS_U8 cData = 0;
3779 MS_U8 cBitMask = 0;
3780 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
3781
3782 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
3783 _MSB201X_I2C_CH_Reset(devID, 5);
3784 #if 0
3785 if (fCurrRFPowerDbm < 100.0f)
3786 {
3787 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
3788 {
3789 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
3790 if (cData > 5)
3791 {
3792 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
3793 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
3794 }
3795 else
3796 {
3797 if ((fCurrRFPowerDbm<fNoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000))
3798 {
3799 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
3800 }
3801 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
3802 {
3803 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
3804 #ifdef MS_DEBUG
3805 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
3806 #endif
3807 return TRUE;
3808 }
3809 }
3810 #ifdef MS_DEBUG
3811 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%f Threshold:%f Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
3812 #endif
3813 }
3814 }
3815 #endif
3816
3817 {
3818 switch( eType )
3819 {
3820 case DMD_DVBC_GETLOCK_FEC_LOCK:
3821 _MDrv_DMD_MSB201X_GetReg(devID, FEC_REG_BASE + 0xE0, &cData);
3822
3823 printf(" @_MDrv_DMD_MSB201X_GetLock DevID = %d, Channel = %d, FSM 0x%x\n",devID, u8DemodIndex, cData);
3824 if (cData == 0x0C)
3825 {
3826 if(pDemod->DMD_Lock_Status[u8DemodIndex]== 0)
3827 {
3828 pDemod->DMD_Lock_Status[u8DemodIndex] = 1;
3829 printf("[Demod]lock++++\n");
3830
3831 }
3832 return TRUE;
3833 }
3834 else
3835 {
3836 if(pDemod->DMD_Lock_Status[u8DemodIndex] == 1)
3837 {
3838 pDemod->DMD_Lock_Status[u8DemodIndex] = 0;
3839 printf("[Demod]unlock----\n");
3840 }
3841 return FALSE;
3842 }
3843 break;
3844
3845 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
3846 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
3847 cBitMask = _BIT1;
3848 break;
3849
3850 case DMD_DVBC_GETLOCK_DCR_LOCK:
3851 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
3852 cBitMask = _BIT0;
3853 break;
3854
3855 case DMD_DVBC_GETLOCK_AGC_LOCK:
3856 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
3857 cBitMask = _BIT0;
3858 break;
3859
3860 case DMD_DVBC_GETLOCK_NO_CHANNEL:
3861 u16Address = TOP_REG_BASE + 0xC3; //no channel,
3862 cBitMask = _BIT2 | _BIT3 | _BIT4;
3863 break;
3864
3865 case DMD_DVBC_GETLOCK_ATV_DETECT:
3866 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
3867 cBitMask = _BIT1; // check atv
3868 break;
3869
3870 case DMD_DVBC_GETLOCK_TR_LOCK:
3871 #if 0 // 20111108 temporarily solution
3872 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
3873 cBitMask = _BIT4;
3874 break;
3875 #endif
3876 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
3877 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
3878 cBitMask = _BIT4;
3879 break;
3880
3881 default:
3882 return FALSE;
3883 }
3884
3885 if (_MDrv_DMD_MSB201X_GetReg(devID, u16Address, &cData) == FALSE)
3886 return FALSE;
3887
3888 if ((cData & cBitMask) != 0)
3889 {
3890 return TRUE;
3891 }
3892
3893 return FALSE;
3894 }
3895
3896 return FALSE;
3897 }
3898
MDrv_DMD_MSB201X_GetLock(MS_U8 devID,MS_U8 u8DemodIndex,eDMD_MSB201X_GETLOCK_TYPE eType,eDMD_MSB201X_LOCK_STATUS * eLockStatus)3899 MS_BOOL MDrv_DMD_MSB201X_GetLock(MS_U8 devID, MS_U8 u8DemodIndex, eDMD_MSB201X_GETLOCK_TYPE eType, eDMD_MSB201X_LOCK_STATUS *eLockStatus)
3900 {
3901 return MDrv_DMD_MSB201X_GetLockWithRFPower(devID, u8DemodIndex, eType, eLockStatus, 200.0f, -200.0f);
3902 }
3903
MDrv_DMD_MSB201X_GetLockWithRFPower(MS_U8 devID,MS_U8 u8DemodIndex,eDMD_MSB201X_GETLOCK_TYPE eType,eDMD_MSB201X_LOCK_STATUS * eLockStatus,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm)3904 MS_BOOL MDrv_DMD_MSB201X_GetLockWithRFPower(MS_U8 devID, MS_U8 u8DemodIndex, eDMD_MSB201X_GETLOCK_TYPE eType, eDMD_MSB201X_LOCK_STATUS *eLockStatus, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm)
3905 {
3906 MS_U32 u32CurrScanTime=0;
3907 MS_BOOL bRet=FALSE;
3908 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
3909
3910 DMD_LOCK();
3911 if ( eType == DMD_DVBC_GETLOCK ) // for channel scan
3912 {
3913 if (_MDrv_DMD_MSB201X_GetLock(devID, u8DemodIndex, DMD_DVBC_GETLOCK_FEC_LOCK, 200.0f, -200.0f, 0))
3914 {
3915 *eLockStatus = DMD_DVBC_LOCK;
3916 }
3917 else
3918 {
3919 MS_U32 u32Timeout = 10000;//(sDMD_DVBC_Info.u16SymbolRate) ? 5000 : 15000;
3920 if (pDemod->sDMD_MSB201X_Info[u8DemodIndex].u16SymbolRate == 0)
3921 {
3922 u32Timeout = u16DMD_DVBC_AutoSymbol_Timeout;
3923 }
3924 else
3925 {
3926 u32Timeout = (pDemod->sDMD_MSB201X_Info[u8DemodIndex].eQamMode == DMD_DVBC_QAMAUTO) ? u16DMD_DVBC_FixSymbol_AutoQam_Timeout : u16DMD_DVBC_FixSymbol_FixQam_Timeout;
3927 }
3928
3929 u32CurrScanTime=MsOS_GetSystemTime();
3930 if (u32CurrScanTime - pDemod->sDMD_MSB201X_Info[u8DemodIndex].u32ChkScanTimeStart < u32Timeout)
3931 {
3932 if (pDemod->u32DMD_DVBC_ScanCount[u8DemodIndex]==0)
3933 {
3934 pDemod->u32DMD_DVBC_PrevScanTime[u8DemodIndex]=u32CurrScanTime;
3935 pDemod->u32DMD_DVBC_ScanCount[u8DemodIndex]++;
3936 }
3937
3938 bRet=_MDrv_DMD_MSB201X_GetRFLevel(devID, u8DemodIndex, &fCurrRFPowerDbm, fCurrRFPowerDbm,
3939 pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].pIFAGC_SSI, pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].IFAGC_SSI_Length,
3940 pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].pIFAGC_ERR, pDemod->_sDMD_MSB201X_InitData.IFAGC_Data[u8DemodIndex].IFAGC_ERR_Length);
3941
3942 if (_MDrv_DMD_MSB201X_GetLock(devID, u8DemodIndex, DMD_DVBC_GETLOCK_NO_CHANNEL, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32CurrScanTime-pDemod->u32DMD_DVBC_PrevScanTime[u8DemodIndex]))
3943 {
3944 #ifdef MS_DEBUG
3945 printf("%s %ld UNLOCK:NO_CHANNEL\n", __FUNCTION__, u32CurrScanTime-pDemod->sDMD_MSB201X_Info[u8DemodIndex].u32ChkScanTimeStart);
3946 #endif
3947 *eLockStatus = DMD_DVBC_UNLOCK;
3948 }
3949 else if (_MDrv_DMD_MSB201X_GetLock(devID, u8DemodIndex, DMD_DVBC_GETLOCK_ATV_DETECT, 200.0f, -200.0f, 0))
3950 {
3951 #ifdef MS_DEBUG
3952 printf("%s %ld UNLOCK:ATV_DETECT\n", __FUNCTION__, u32CurrScanTime-pDemod->sDMD_MSB201X_Info[u8DemodIndex].u32ChkScanTimeStart);
3953 #endif
3954 *eLockStatus = DMD_DVBC_UNLOCK;
3955 }
3956 #ifdef NEW_TR_MODULE
3957 else if ((_MDrv_DMD_MSB201X_GetLock(devID, u8DemodIndex, DMD_DVBC_GETLOCK_TR_EVER_LOCK, 200.0f, -200.0f, 0) == FALSE) && ((u32CurrScanTime - pDemod->sDMD_MSB201X_Info[u8DemodIndex].u32ChkScanTimeStart) > 500))
3958 #else
3959 else if ((_MDrv_DMD_MSB201X_GetLock(devID, u8DemodIndex, DMD_DVBC_GETLOCK_TR_EVER_LOCK, 200.0f, -200.0f, 0) == FALSE) && ((u32CurrScanTime - pDemod->sDMD_MSB201X_Info[u8DemodIndex].u32ChkScanTimeStart) > 5000))
3960 #endif
3961 {
3962 #ifdef MS_DEBUG
3963 printf("%s %ld UNLOCK:TR\n", __FUNCTION__, u32CurrScanTime-pDemod->sDMD_MSB201X_Info[u8DemodIndex].u32ChkScanTimeStart);
3964 #endif
3965 *eLockStatus = DMD_DVBC_UNLOCK;
3966 }
3967 else
3968 {
3969 *eLockStatus = DMD_DVBC_CHECKING;
3970 }
3971 }
3972 else
3973 {
3974 #ifdef MS_DEBUG
3975 printf("%s %ld UNLOCK:TIMEOUT %ld\n", __FUNCTION__, MsOS_GetSystemTime(), u32Timeout);
3976 #endif
3977 *eLockStatus = DMD_DVBC_UNLOCK;
3978 }
3979 pDemod->u32DMD_DVBC_PrevScanTime[u8DemodIndex]=u32CurrScanTime;
3980 }
3981
3982 }
3983 else
3984 {
3985 if (_MDrv_DMD_MSB201X_GetLock(devID, u8DemodIndex, eType, 200.0f, -200.0f, 0) == TRUE)
3986 {
3987 *eLockStatus = DMD_DVBC_LOCK;
3988 }
3989 else
3990 {
3991 *eLockStatus = DMD_DVBC_UNLOCK;
3992 }
3993 }
3994 DMD_UNLOCK();
3995
3996 bRet=TRUE;
3997 return bRet;
3998 }
3999
MDrv_DMD_MSB201X_Demod_GetLock(MS_U8 devID,MS_U8 u8DemodIndex)4000 MS_BOOL MDrv_DMD_MSB201X_Demod_GetLock(MS_U8 devID, MS_U8 u8DemodIndex)
4001 {
4002 MS_U8 cData;
4003 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4004 DMD_LOCK();
4005
4006 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
4007
4008 printf(" MDrv_DMD_MSB201X_Demod_GetLock : devID = %d, Channel index = %d \n", (int)devID, (int)u8DemodIndex);
4009
4010 _MSB201X_I2C_CH_Reset(devID, 5);
4011
4012 // Only check demod lock or not!
4013 _MDrv_DMD_MSB201X_GetReg(devID, FEC_REG_BASE + 0xE0, &cData);
4014 printf(" MDrv_DMD_MSB201X_Demod_GetLock FSM 0x%x\n",cData);
4015 if(cData == 0x0C)
4016 {
4017 if(g_dvbc_lock[devID][u8DemodIndex] == 0)
4018 {
4019 g_dvbc_lock[devID][u8DemodIndex] = 1;
4020 printf(" MDrv_DMD_MSB201X_Demod_GetLock : Demod Lock! \n");
4021 }
4022 _MSB201X_I2C_CH_Reset(devID, 3);
4023 return TRUE;
4024 }
4025 else
4026 {
4027 if(g_dvbc_lock[devID][u8DemodIndex] == 1)
4028 {
4029 g_dvbc_lock[devID][u8DemodIndex] = 0;
4030 printf(" MDrv_DMD_MSB201X_Demod_GetLock : Demod Unlock! \n");
4031 }
4032 _MSB201X_I2C_CH_Reset(devID, 3);
4033 return FALSE;
4034 }
4035
4036 DMD_UNLOCK();
4037 return FALSE;
4038 }
4039
MDrv_DMD_MSB201X_Set_TSOut(MS_U8 devID,sDMD_MSB201X_TS_Param * pDMD_MSB201X_TS_Param)4040 MS_BOOL MDrv_DMD_MSB201X_Set_TSOut(MS_U8 devID, sDMD_MSB201X_TS_Param *pDMD_MSB201X_TS_Param)
4041 {
4042 tMSB201X_Demod_Data *pDemod=NULL;
4043 pDemod= DEMOD_GET_ACTIVE_NODE(devID);
4044 DMD_LOCK();
4045
4046 _MDrv_DMD_MSB201X_Set_TSOut(devID, pDMD_MSB201X_TS_Param);
4047
4048 DMD_UNLOCK();
4049 return TRUE;
4050 }
4051
MDrv_DMD_MSB201X_CfgExtHeader(MS_U8 devID,MS_U8 u8DemodIndex,sDMD_MSB201X_extHeader * pDMD_MSB201X_extHeader_Param)4052 MS_BOOL MDrv_DMD_MSB201X_CfgExtHeader(MS_U8 devID, MS_U8 u8DemodIndex, sDMD_MSB201X_extHeader *pDMD_MSB201X_extHeader_Param)
4053 {
4054 MS_BOOL bRet = TRUE;
4055 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4056 DMD_LOCK();
4057
4058 bRet = _MDrv_DMD_MSB201X_CfgExtHeader(devID, u8DemodIndex, pDMD_MSB201X_extHeader_Param);
4059
4060 DMD_UNLOCK();
4061 return bRet;
4062 }
4063
MDrv_DMD_MSB201X_CfgCIHeader(MS_U8 devID,MS_U8 u8DemodIndex,sDMD_MSB201X_CIHeader * pDMD_MSB201X_CIHeader_Param)4064 MS_BOOL MDrv_DMD_MSB201X_CfgCIHeader(MS_U8 devID, MS_U8 u8DemodIndex, sDMD_MSB201X_CIHeader *pDMD_MSB201X_CIHeader_Param)
4065 {
4066 MS_BOOL bRet = TRUE;
4067 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4068 DMD_LOCK();
4069
4070 bRet = _MDrv_DMD_MSB201X_CfgCIHeader(devID, u8DemodIndex, pDMD_MSB201X_CIHeader_Param);
4071
4072 DMD_UNLOCK();
4073 return bRet;
4074 }
4075
_MDrv_DMD_MSB201X_GetCurrentModulationType(MS_U8 devID,MS_U8 u8DemodIndex,eDMD_MSB201X_MODULATION_TYPE * pQAMMode)4076 MS_BOOL _MDrv_DMD_MSB201X_GetCurrentModulationType(MS_U8 devID, MS_U8 u8DemodIndex, eDMD_MSB201X_MODULATION_TYPE *pQAMMode)
4077 {
4078 MS_U8 u8Data=0;
4079
4080 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
4081 _MSB201X_I2C_CH_Reset(devID, 5);
4082
4083 _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x02, &u8Data);
4084
4085 switch(u8Data&0x07)
4086 {
4087 case 0:
4088 *pQAMMode = DMD_DVBC_QAM16;
4089 return TRUE;
4090 break;
4091 case 1:
4092 *pQAMMode = DMD_DVBC_QAM32;
4093 return TRUE;
4094 break;
4095 case 2:
4096 *pQAMMode = DMD_DVBC_QAM64;
4097 return TRUE;
4098 break;
4099 case 3:
4100 *pQAMMode = DMD_DVBC_QAM128;
4101 return TRUE;
4102 break;
4103 case 4:
4104 *pQAMMode = DMD_DVBC_QAM256;
4105 return TRUE;
4106 break;
4107 default:
4108 *pQAMMode = DMD_DVBC_QAMAUTO;
4109 return FALSE;
4110 }
4111 }
4112
_MDrv_DMD_MSB201X_GetCurrentSymbolRate(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 * u16SymbolRate)4113 MS_BOOL _MDrv_DMD_MSB201X_GetCurrentSymbolRate(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 *u16SymbolRate)
4114 {
4115 MS_U8 tmp = 0;
4116 MS_U16 u16SymbolRateTmp = 0;
4117
4118 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
4119 _MSB201X_I2C_CH_Reset(devID, 5);
4120
4121 // intp
4122 _MDrv_DMD_MSB201X_GetReg(devID, TOP_REG_BASE + 0xd2, &tmp);
4123 u16SymbolRateTmp = tmp;
4124 _MDrv_DMD_MSB201X_GetReg(devID, TOP_REG_BASE + 0xd1, &tmp);
4125 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
4126
4127 if (abs(u16SymbolRateTmp-6900)<2)
4128 {
4129 u16SymbolRateTmp=6900;
4130 }
4131
4132 if (abs(u16SymbolRateTmp-6875)<2)
4133 {
4134 u16SymbolRateTmp=6875;
4135 }
4136
4137 *u16SymbolRate = u16SymbolRateTmp;
4138
4139 return TRUE;
4140 }
4141
_MDrv_DMD_MSB201X_Get_FreqOffset(MS_U8 devID,MS_U8 u8DemodIndex,float * pFreqOff,MS_U8 u8BW)4142 MS_BOOL _MDrv_DMD_MSB201X_Get_FreqOffset(MS_U8 devID, MS_U8 u8DemodIndex, float *pFreqOff, MS_U8 u8BW)
4143 {
4144 MS_U16 FreqB, config_Fc=0;
4145 float FreqCfo_offset,f_Fc;
4146 MS_U32 RegCfo_offset, Reg_Fc_over_Fs;
4147 //MS_U8 reg_frz = 0, reg = 0;
4148 MS_U8 reg = 0;
4149 MS_BOOL status = TRUE;
4150
4151 // no use.
4152 u8BW = u8BW;
4153
4154 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
4155 _MSB201X_I2C_CH_Reset(devID, 5);
4156
4157 // bank 2c 0x3d [0] reg_bit_err_num_freeze
4158 status &= _MDrv_DMD_MSB201X_SetReg(devID, EQE_REG_BASE + 0x3A, 0x20);
4159 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x80);
4160
4161 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x43, ®);
4162 RegCfo_offset = reg;
4163 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x42, ®);
4164 RegCfo_offset = (RegCfo_offset<<8)|reg;
4165 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x41, ®);
4166 RegCfo_offset = (RegCfo_offset<<8)|reg;
4167 status &= _MDrv_DMD_MSB201X_GetReg(devID, EQE_REG_BASE + 0x40, ®);
4168 RegCfo_offset = (RegCfo_offset<<8)|reg;
4169
4170 // bank 2c 0x3d [0] reg_bit_err_num_freeze
4171 status &= _MDrv_DMD_MSB201X_SetReg(devID, EQE_REG_BASE + 0x3A, 0x00);
4172 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x00);
4173
4174 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x5b, ®);
4175 Reg_Fc_over_Fs = reg;
4176 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x5a, ®);
4177 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
4178 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x59, ®);
4179 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
4180 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x58, ®);
4181 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
4182
4183 status &= _MDrv_DMD_MSB201X_GetReg(devID, E_DMD_DVBC_CFG_FIF_H, ®);
4184 config_Fc = reg;
4185 status &= _MDrv_DMD_MSB201X_GetReg(devID, E_DMD_DVBC_CFG_FIF_L, ®);
4186 config_Fc = (config_Fc<<8)|reg;
4187
4188 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * ((float)DVBC_FS);
4189
4190 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
4191
4192 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
4193
4194 status &= _MDrv_DMD_MSB201X_GetCurrentSymbolRate(devID, u8DemodIndex, &FreqB);
4195
4196 FreqCfo_offset = FreqCfo_offset * FreqB + (f_Fc-(float)config_Fc);
4197
4198 *pFreqOff = FreqCfo_offset;
4199
4200 return status;
4201 }
4202
MDrv_DMD_MSB201X_GetStatus(MS_U8 devID,MS_U8 u8DemodIndex,eDMD_MSB201X_MODULATION_TYPE * pQAMMode,MS_U16 * u16SymbolRate,float * pFreqOff)4203 MS_BOOL MDrv_DMD_MSB201X_GetStatus(MS_U8 devID, MS_U8 u8DemodIndex, eDMD_MSB201X_MODULATION_TYPE *pQAMMode, MS_U16 *u16SymbolRate, float *pFreqOff)
4204 {
4205 MS_BOOL bRet=TRUE;
4206 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4207
4208 DMD_LOCK();
4209
4210 _MDrv_DMD_MSB201X_GetCurrentModulationType(devID, u8DemodIndex, pQAMMode);
4211 _MDrv_DMD_MSB201X_GetCurrentSymbolRate(devID, u8DemodIndex, u16SymbolRate);
4212 _MDrv_DMD_MSB201X_Get_FreqOffset(devID, u8DemodIndex, pFreqOff,8);
4213
4214 DMD_UNLOCK();
4215
4216 return bRet;
4217 }
4218
4219
MDrv_DMD_MSB201X_GetFWVer(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 * ver)4220 MS_BOOL MDrv_DMD_MSB201X_GetFWVer(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 *ver)
4221 {
4222
4223 MS_BOOL bRet;
4224 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4225
4226 DMD_LOCK();
4227 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
4228 bRet = _MDrv_DMD_MSB201X_Version(devID, u8DemodIndex, ver);
4229 //printf("MDrv_DMD_DVBC_GetFWVer %x\n", *ver);
4230 DMD_UNLOCK();
4231
4232 return bRet;
4233
4234 }
4235
4236
4237 #if 0
4238 MS_BOOL MDrv_DMD_MSB201X_Exit(MS_U8 devID)
4239 {
4240 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4241
4242 pDemod->bDMD_MSB201X_Power_init_en = FALSE;
4243 pDemod->u8DMD_MSB201X_PowerOnInitialization_Flow = 0;
4244 pDemod->u8DMD_MSB201X_Sram_Code = 0x0;
4245 pDemod->bDemodRest = TRUE;
4246
4247 return TRUE;
4248 }
4249 #endif
4250
_MDrv_DMD_MSB201X_Config(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 u16SymbolRate,eDMD_MSB201X_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv)4251 MS_BOOL _MDrv_DMD_MSB201X_Config(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 u16SymbolRate, eDMD_MSB201X_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv)
4252 {
4253
4254 MS_U8 status = true;
4255 MS_U8 reg_symrate_l, reg_symrate_h;
4256 //MS_U16 u16Fc = 0;
4257
4258 _MDrv_DMD_MSB201X_Select_Demod_RIU(devID, u8DemodIndex);
4259 printf(" @_MDrv_DMD_MSB201X_Config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d \n",u16SymbolRate,eQamMode,(long int)u32IFFreq,bSpecInv);
4260 printf(" @_MDrv_DMD_MSB201X_Config, t = %ld\n",(long int)MsOS_GetSystemTime());
4261 printf("set demod index=%d dev_id=%d\n",u8DemodIndex,devID);
4262
4263 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
4264 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
4265
4266 status &= _MDrv_DMD_MSB201X_Restart(devID, u8DemodIndex);
4267
4268
4269 if (eQamMode == DMD_DVBC_QAMAUTO)
4270 {
4271 #ifdef MS_DEBUG
4272 printf("DMD_DVBC_QAMAUTO\n");
4273 #endif
4274 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
4275 // give default value.
4276 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_CFG_QAM, QAM);
4277 }
4278 else
4279 {
4280 #ifdef MS_DEBUG
4281 printf("DMD_DVBC_QAM %d\n", eQamMode);
4282 #endif
4283 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
4284 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_CFG_QAM, eQamMode);
4285 }
4286 // auto symbol rate enable/disable
4287 #ifdef MS_DEBUG
4288 printf("u16SymbolRate %d\n", u16SymbolRate);
4289 #endif
4290 if (u16SymbolRate == 0)
4291 {
4292 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
4293 }
4294 else
4295 {
4296 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
4297 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
4298 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
4299 }
4300
4301
4302 // IQ Swap
4303 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
4304
4305 // Lif
4306 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
4307 // Fif
4308 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
4309 status &= _MDrv_DMD_MSB201X_SetDSPReg(devID, u8DemodIndex, E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
4310
4311 status &= _MDrv_DMD_MSB201X_Active(devID, u8DemodIndex, TRUE);
4312 return status;
4313 }
4314
MDrv_DMD_MSB201X_SetConfig(MS_U8 devID,MS_U8 u8DemodIndex,MS_U16 u16SymbolRate,eDMD_MSB201X_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv)4315 MS_BOOL MDrv_DMD_MSB201X_SetConfig(MS_U8 devID, MS_U8 u8DemodIndex, MS_U16 u16SymbolRate, eDMD_MSB201X_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv)
4316 {
4317 MS_BOOL bRet;
4318 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4319
4320 DMD_LOCK();
4321
4322 #if 0
4323 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
4324 {
4325 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=1)
4326 {
4327 u8TSClk = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[2];
4328 }
4329 else
4330 {
4331 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
4332 }
4333 }
4334 else
4335 {
4336 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
4337 }
4338 #endif
4339 bRet=_MDrv_DMD_MSB201X_Config(devID, u8DemodIndex, u16SymbolRate, eQamMode, u32IFFreq, bSpecInv);
4340 pDemod->sDMD_MSB201X_Info[u8DemodIndex].u16SymbolRate = u16SymbolRate;
4341 pDemod->sDMD_MSB201X_Info[u8DemodIndex].eQamMode = eQamMode;
4342 pDemod->sDMD_MSB201X_Info[u8DemodIndex].u32IFFreq = u32IFFreq;
4343 pDemod->sDMD_MSB201X_Info[u8DemodIndex].bSpecInv = bSpecInv;
4344 //pDemod->sDMD_MSB201X_Info.bSerialTS = bSerialTS;
4345
4346 DMD_UNLOCK();
4347
4348 return bRet;
4349 }
4350
4351
MDrv_DMD_MSB201X_Power_On_Initialization(MS_U8 devID,MS_U8 u8DemodIndex)4352 MS_BOOL MDrv_DMD_MSB201X_Power_On_Initialization(MS_U8 devID, MS_U8 u8DemodIndex)
4353 {
4354 //MS_U8 status = TRUE;
4355 tMSB201X_Demod_Data *pDemod = DEMOD_GET_ACTIVE_NODE(devID);
4356 DMD_LOCK();
4357
4358 #ifdef MS_DEBUG
4359 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
4360 #endif
4361
4362 //_MSB201X_I2C_CH_Reset(devID, 3);
4363
4364 //_MSB201X_I2C_CH_Reset(devID, 3);
4365
4366 //_MDrv_DMD_MSB201X_InitClkgen(devID);
4367
4368
4369 //_MDrv_DMD_MSB201X_TS_MUX_Serial(devID);
4370
4371 DMD_UNLOCK();
4372 return TRUE;
4373 }
4374
4375
4376
4377
4378