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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #include <math.h>
105 #include "MsCommon.h"
106 #include "MsIRQ.h"
107 #include "MsOS.h"
108 //#include "apiPWS.h"
109
110 #include "MsTypes.h"
111 #include "drvBDMA.h"
112 //#include "drvIIC.h"
113 //#include "msAPI_Tuner.h"
114 //#include "msAPI_MIU.h"
115 //#include "BinInfo.h"
116 //#include "halVif.h"
117 #include "drvDMD_INTERN_DVBC.h"
118 #include "halDMD_INTERN_DVBC.h"
119 #include "halDMD_INTERN_common.h"
120 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
121 #include "InfoBlock.h"
122 #endif
123 #include "drvMMIO.h"
124 //#include "TDAG4D01A_SSI_DVBT.c"
125 #include "drvDMD_VD_MBX.h"
126 #define TEST_EMBEDED_DEMOD 0
127 //U8 load_data_variable=1;
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
130
131 #define TDE_REG_BASE 0x2400UL
132 #define INNC_REG_BASE 0x2600UL
133 #define EQE_REG_BASE 0x2c00UL // P2= 1; 0x11c00 -> 0x1c00
134 #define EQE2_REG_BASE 0x9c00UL
135 #define MBX_REG_BASE 0x2F00UL
136
137 #ifdef MS_DEBUG
138 #define DBG_INTERN_DVBC(x) x
139 #define DBG_GET_SIGNAL_DVBC(x) x
140 #define DBG_INTERN_DVBC_TIME(x) x
141 #define DBG_INTERN_DVBC_LOCK(x) x
142 #define INTERN_DVBC_INTERNAL_DEBUG 0
143 #else
144 #define DBG_INTERN_DVBC(x) //x
145 #define DBG_GET_SIGNAL_DVBC(x) //x
146 #define DBG_INTERN_DVBC_TIME(x) //x
147 #define DBG_INTERN_DVBC_LOCK(x) //x
148 #define INTERN_DVBC_INTERNAL_DEBUG 0
149 #endif
150 #define DBG_DUMP_LOAD_DSP_TIME 0
151
152
153 #define SIGNAL_LEVEL_OFFSET 0.00f
154 #define TAKEOVERPOINT -60.0f
155 #define TAKEOVERRANGE 0.5f
156 #define LOG10_OFFSET -0.21f
157 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
158 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
159
160 #define TUNER_IF 36167
161
162 #define TS_SER_C 0x00 //0: parallel 1:serial
163
164 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
165 #define TS_INV_C 0x01
166 #else
167 #define TS_INV_C 0x00
168 #endif
169
170 #define DVBC_FS 45474 //24000
171 #define CFG_ZIF 0x00 //For ZIF ,FC=0
172 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
173 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
174 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
175 #define FS_L_C (DVBC_FS&0xFF)
176 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
177 #define IQ_SWAP_C 0x00
178 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
179 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
180 // Symbol Rate: 6875 = 0x1ADB
181 // Symbol Rate: 6900 = 0x1AF4
182 // Symbol Rate: 7000 = 0x1B58
183 // Symbol Rate: 4000 = 0x0FA0
184 // Symbol Rate: 6125 = 0x17ED
185 #define SR0_H 0x1A
186 #define SR0_L 0xF4 //6900
187 #define SR1_H 0x1B
188 #define SR1_L 0x58 //7000
189 #define SR2_H 0x17
190 #define SR2_L 0xED //6125
191 #define SR3_H 0x0F
192 #define SR3_L 0xA0 //4000
193 #define SR4_H 0x1B
194 #define SR4_L 0x26 //6950
195 #define SR5_H 0x1A //0xDB
196 #define SR5_L 0xDB //0x1A //6875
197 #define SR6_H 0x1C
198 #define SR6_L 0x20 //7200
199 #define SR7_H 0x1C
200 #define SR7_L 0x52 //7250
201 #define SR8_H 0x0B
202 #define SR8_L 0xB8 //3000
203 #define SR9_H 0x03
204 #define SR9_L 0xE8 //1000
205 #define SR10_H 0x07
206 #define SR10_L 0xD0 //2000
207 #define SR11_H 0x00
208 #define SR11_L 0x00 //0000
209
210
211 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
212
213 // SAR dependent
214 #define NO_SIGNAL_TH_A 0xA3
215 // Tuner dependent
216 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
217 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
218 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
219 #define NO_SIGNAL_TH_C_H 0xff //0x00
220 #define DAGC1_REF 0x70
221 #define DAGC2_REF 0x30
222 #define AGC_REF_L 0x00
223 #define AGC_REF_H 0x06
224
225 #define INTERN_AUTO_SR_C 1
226 #define INTERN_AUTO_QAM_C 1
227
228 #define ATV_DET_EN 1
229
230 #if 0
231 MS_U8 INTERN_DVBC_DSPREG[] =
232 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
233 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
234 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
235 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
236 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
237 };
238 #else
239 MS_U8 INTERN_DVBC_DSPREG[] =
240 {
241 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
242 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
243 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
244 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
245 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
246 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
247 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
248 };
249 #endif
250 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
251
252 //-----------------------------------------------------------------------
253 /****************************************************************
254 *Local Variables *
255 ****************************************************************/
256
257 //static MS_BOOL TPSLock = 0;
258 static MS_U32 u32ChkScanTimeStartDVBC = 0;
259 static MS_U8 g_dvbc_lock = 0;
260 static float intern_dvb_c_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
261
262 //Global Variables
263 S_CMDPKTREG gsCmdPacketDVBC;
264 //MS_U8 gCalIdacCh0, gCalIdacCh1;
265 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
266 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
267 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
268 MS_U8 INTERN_DVBC_table[] = {
269 #include "fwDMD_INTERN_DVBC.dat"
270 };
271
272 #endif
273
274 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
275 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
276 // MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
277 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
278 // MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff);
279 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
280 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
281 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
282
283 #if (INTERN_DVBC_INTERNAL_DEBUG)
284 void INTERN_DVBC_info(void);
285 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
286 #endif
287
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)288 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
289 {
290 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
291 MS_U8 status = TRUE;
292 MS_U16 u16DspAddr = 0;
293
294 DBG_INTERN_DVBC(printf("INTERN_DVBC_DSPReg_Init\n"));
295
296 #if 0//def MS_DEBUG
297 {
298 MS_U8 u8buffer[256];
299 printf("INTERN_DVBC_DSPReg_Init Reset\n");
300 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
301 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
302
303 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
304 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
305 printf("INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
306 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
307 printf("%x ", u8buffer[idx]);
308 printf("\n");
309
310 printf("INTERN_DVBC_DSPReg_Init Value\n");
311 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
312 printf("%x ", INTERN_DVBC_DSPREG[idx]);
313 printf("\n");
314 }
315 #endif
316
317 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
318 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
319
320 // readback to confirm.
321 #ifdef MS_DEBUG
322 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
323 {
324 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
325 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
326 {
327 printf("[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
328 }
329 }
330 #endif
331
332 if (u8DVBC_DSPReg != NULL)
333 {
334 if (1 == u8DVBC_DSPReg[0])
335 {
336 u8DVBC_DSPReg+=2;
337 for (idx = 0; idx<u8Size; idx++)
338 {
339 u16DspAddr = *u8DVBC_DSPReg;
340 u8DVBC_DSPReg++;
341 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
342 u8DVBC_DSPReg++;
343 u8Mask = *u8DVBC_DSPReg;
344 u8DVBC_DSPReg++;
345 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
346 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
347 u8DVBC_DSPReg++;
348 DBG_INTERN_DVBC(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
349 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
350 }
351 }
352 else
353 {
354 printf("FATAL: parameter version incorrect\n");
355 }
356 }
357
358 #if 0//def MS_DEBUG
359 {
360 MS_U8 u8buffer[256];
361 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
362 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
363 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
364 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
365 printf("%x ", u8buffer[idx]);
366 printf("\n");
367 }
368 #endif
369
370 #if 0//def MS_DEBUG
371 {
372 MS_U8 u8buffer[256];
373 for (idx = 0; idx<128; idx++)
374 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
375 printf("INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
376 for (idx = 0; idx<128; idx++)
377 {
378 printf("%x ", u8buffer[idx]);
379 if ((idx & 0xF) == 0xF) printf("\n");
380 }
381 printf("\n");
382 }
383 #endif
384 return status;
385 }
386
387 /***********************************************************************************
388 Subject: Command Packet Interface
389 Function: INTERN_DVBC_Cmd_Packet_Send
390 Parmeter:
391 Return: MS_BOOL
392 Remark:
393 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)394 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
395 {
396
397 return TRUE;
398
399 }
400
401
402 /***********************************************************************************
403 Subject: Command Packet Interface
404 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
405 Parmeter:
406 Return: MS_BOOL
407 Remark:
408 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)409 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
410 {
411 return TRUE;
412 }
413
414 /***********************************************************************************
415 Subject: SoftStop
416 Function: INTERN_DVBC_SoftStop
417 Parmeter:
418 Return: MS_BOOL
419 Remark:
420 ************************************************************************************/
421
INTERN_DVBC_SoftStop(void)422 MS_BOOL INTERN_DVBC_SoftStop ( void )
423 {
424 #if 1
425 MS_U16 u8WaitCnt=0;
426
427 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
428 {
429 printf(">> MB Busy!\n");
430 return FALSE;
431 }
432
433 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
434
435 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
436 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
437
438 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
439 {
440 #if TEST_EMBEDED_DEMOD
441 MsOS_DelayTask(1); // << Ken 20090629
442 #endif
443 if (u8WaitCnt++ >= 0x7FFF)
444 {
445 printf(">> DVBT SoftStop Fail!\n");
446 return FALSE;
447 }
448 }
449
450 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
451 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
452 #endif
453 return TRUE;
454 }
455
456
457 /***********************************************************************************
458 Subject: Reset
459 Function: INTERN_DVBC_Reset
460 Parmeter:
461 Return: MS_BOOL
462 Remark:
463 ************************************************************************************/
464 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)465 MS_BOOL INTERN_DVBC_Reset ( void )
466 {
467 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_reset\n"));
468
469 DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime()));
470
471 //INTERN_DVBC_SoftStop();
472
473 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset
474 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset DMD_MCU
475 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
476 MsOS_DelayTask(5);
477 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
478 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
479 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
480 MsOS_DelayTask(5);
481
482 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
483 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
484
485 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
486 g_dvbc_lock = 0;
487
488 return TRUE;
489 }
490
491 /***********************************************************************************
492 Subject: Exit
493 Function: INTERN_DVBC_Exit
494 Parmeter:
495 Return: MS_BOOL
496 Remark:
497 ************************************************************************************/
INTERN_DVBC_Exit(void)498 MS_BOOL INTERN_DVBC_Exit ( void )
499 {
500
501 INTERN_DVBC_SoftStop();
502
503 return TRUE;
504 }
505
506 /***********************************************************************************
507 Subject: Load DSP code to chip
508 Function: INTERN_DVBC_LoadDSPCode
509 Parmeter:
510 Return: MS_BOOL
511 Remark:
512 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)513 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
514 {
515 MS_U8 udata = 0x00;
516 MS_U16 i;
517 MS_U16 fail_cnt=0;
518
519 #if (DBG_DUMP_LOAD_DSP_TIME==1)
520 MS_U32 u32Time;
521 #endif
522
523
524 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
525 BININFO BinInfo;
526 MS_BOOL bResult;
527 MS_U32 u32GEAddr;
528 MS_U8 Data;
529 MS_S8 op;
530 MS_U32 srcaddr;
531 MS_U32 len;
532 MS_U32 SizeBy4K;
533 MS_U16 u16Counter=0;
534 MS_U8 *pU8Data;
535 #endif
536
537
538
539 // MDrv_Sys_DisableWatchDog();
540
541 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset
542 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset VD_MCU
543 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
544 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
545 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
546 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
547 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
548
549 //// Load code thru VDMCU_IF ////
550 DBG_INTERN_DVBC(printf(">Load Code.....\n"));
551 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
552 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
553 {
554 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
555 }
556 #else
557 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
558 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
559 if ( bResult != PASS )
560 {
561 return FALSE;
562 }
563 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
564
565 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
566 InfoBlock_Flash_2_Checking_Start(&BinInfo);
567 #endif
568
569 #if OBA2
570 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
571 #else
572 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
573 #endif
574
575 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
576 InfoBlock_Flash_2_Checking_End(&BinInfo);
577 #endif
578
579 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
580 SizeBy4K=BinInfo.B_Len/0x1000;
581 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
582
583 #if (DBG_DUMP_LOAD_DSP_TIME==1)
584 u32Time = msAPI_Timer_GetTime0();
585 #endif
586
587 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
588
589 for (i=0;i<=SizeBy4K;i++)
590 {
591 if(i==SizeBy4K)
592 len=BinInfo.B_Len%0x1000;
593 else
594 len=0x1000;
595
596 srcaddr = u32GEAddr+(0x1000*i);
597 //printf("\t i = %08X\n", i);
598 //printf("\t len = %08X\n", len);
599 op = 1;
600 u16Counter = 0 ;
601 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
602 while(len--)
603 {
604 u16Counter ++ ;
605 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
606 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
607 #if OBA2
608 pU8Data = (MS_U8 *)(srcaddr);
609 #else
610 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
611 #endif
612 Data = *pU8Data;
613
614 #if 0
615 if(u16Counter < 0x100)
616 printf("0x%bx,", Data);
617 #endif
618 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
619
620 srcaddr += op;
621 }
622 // printf("\n\n\n");
623 }
624
625 #if (DBG_DUMP_LOAD_DSP_TIME==1)
626 printf("------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
627 #endif
628
629 #endif
630
631 //// Content verification ////
632 DBG_INTERN_DVBC(printf(">Verify Code...\n"));
633
634 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
635 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
636
637 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
638 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
639 {
640 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
641 if (udata != INTERN_DVBC_table[i])
642 {
643 printf(">fail add = 0x%x\n", i);
644 printf(">code = 0x%x\n", INTERN_DVBC_table[i]);
645 printf(">data = 0x%x\n", udata);
646
647 if (fail_cnt > 10)
648 {
649 printf(">DVB-C DSP Loadcode fail!");
650 return false;
651 }
652 fail_cnt++;
653 }
654 }
655 #else
656 for (i=0;i<=SizeBy4K;i++)
657 {
658 if(i==SizeBy4K)
659 len=BinInfo.B_Len%0x1000;
660 else
661 len=0x1000;
662
663 srcaddr = u32GEAddr+(0x1000*i);
664 //printf("\t i = %08LX\n", i);
665 //printf("\t len = %08LX\n", len);
666 op = 1;
667 u16Counter = 0 ;
668 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
669 while(len--)
670 {
671 u16Counter ++ ;
672 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
673 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
674 #if OBA2
675 pU8Data = (MS_U8 *)(srcaddr);
676 #else
677 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
678 #endif
679 Data = *pU8Data;
680
681 #if 0
682 if(u16Counter < 0x100)
683 printf("0x%bx,", Data);
684 #endif
685 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
686 if (udata != Data)
687 {
688 printf(">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
689 printf(">code = 0x%x\n", Data);
690 printf(">data = 0x%x\n", udata);
691
692 if (fail_cnt++ > 10)
693 {
694 printf(">DVB-C DSP Loadcode fail!");
695 return false;
696 }
697 }
698
699 srcaddr += op;
700 }
701 // printf("\n\n\n");
702 }
703 #endif
704
705 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
706 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
707 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
708 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
709
710 DBG_INTERN_DVBC(printf(">DSP Loadcode done."));
711 //while(load_data_variable);
712
713
714
715 return TRUE;
716 }
717
718 /***********************************************************************************
719 Subject: DVB-T CLKGEN initialized function
720 Function: INTERN_DVBC_Power_On_Initialization
721 Parmeter:
722 Return: MS_BOOL
723 Remark:
724 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)725 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
726 {
727 // MS_U8 temp_val;
728
729 HAL_DMD_RIU_WriteByte(0x103c0e, 0x00); //mux from DMD MCU to HK.
730 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
731 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
732
733 // CLK_DMDMCU clock setting
734 // [0] disable clock
735 // [1] invert clock
736 // [4:2]
737 // 000:170 MHz(MPLL_DIV_BUf)
738 // 001:160MHz
739 // 010:144MHz
740 // 011:123MHz
741 // 100:108MHz
742 // 101:mem_clcok
743 // 110:mem_clock div 2
744 // 111:select XTAL
745 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
746
747 // set parallet ts clock
748 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
749 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
750 // wriu 0x103301 0x06
751 // wriu 0x103300 0x19
752
753
754 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
755 HAL_DMD_RIU_WriteByte(0x103301,0x07);
756 HAL_DMD_RIU_WriteByte(0x103300,0x13);
757
758 // enable atsc, DVBTC ts clock
759 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
760 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
761 // wriu 0x103309 0x00
762 // wriu 0x103308 0x00
763
764 HAL_DMD_RIU_WriteByte(0x103309,0x00);
765 HAL_DMD_RIU_WriteByte(0x103308,0x00);
766
767 // enable dvbc adc clock
768 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
769 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
770 // wriu 0x103315 0x00
771 // wriu 0x103314 0x00
772
773 HAL_DMD_RIU_WriteByte(0x103315,0x00);
774 HAL_DMD_RIU_WriteByte(0x103314,0x00);
775
776 // Reset TS divider
777 HAL_DMD_RIU_WriteByte(0x103302,0x01);
778 HAL_DMD_RIU_WriteByte(0x103302,0x00);
779
780 HAL_DMD_RIU_WriteByte(0x152929,0x00);
781 HAL_DMD_RIU_WriteByte(0x152928,0x04);
782
783 HAL_DMD_RIU_WriteByte(0x152903,0x04);
784 HAL_DMD_RIU_WriteByte(0x152902,0x04);
785
786 HAL_DMD_RIU_WriteByte(0x152905,0x00);
787 HAL_DMD_RIU_WriteByte(0x152904,0x00);
788
789 HAL_DMD_RIU_WriteByte(0x152907,0x04);
790 HAL_DMD_RIU_WriteByte(0x152906,0x00);
791
792 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
793 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
794
795
796 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
797 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
798
799 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
800 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
801
802 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
803 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
804
805 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
806 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
807
808 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
809 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
810
811 HAL_DMD_RIU_WriteByte(0x111f69,0x88);
812 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
813
814 HAL_DMD_RIU_WriteByte(0x111f4b,0x01);
815 HAL_DMD_RIU_WriteByte(0x111f4a,0x11);
816
817 HAL_DMD_RIU_WriteByte(0x152923,0x00);
818 HAL_DMD_RIU_WriteByte(0x152922,0x44);
819
820 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
821 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
822
823 HAL_DMD_RIU_WriteByte(0x15296d,0x00);
824 HAL_DMD_RIU_WriteByte(0x15296c,0x81);
825
826 HAL_DMD_RIU_WriteByte(0x152971,0x1c);
827 HAL_DMD_RIU_WriteByte(0x152970,0xc1);
828
829 HAL_DMD_RIU_WriteByte(0x152977,0x08);
830 HAL_DMD_RIU_WriteByte(0x152976,0x08);
831
832 HAL_DMD_RIU_WriteByte(0x152981,0x00);
833 HAL_DMD_RIU_WriteByte(0x152980,0x00);
834
835 HAL_DMD_RIU_WriteByte(0x152983,0x00);
836 HAL_DMD_RIU_WriteByte(0x152982,0x00);
837
838 HAL_DMD_RIU_WriteByte(0x152985,0x00);
839 HAL_DMD_RIU_WriteByte(0x152984,0x00);
840
841 HAL_DMD_RIU_WriteByte(0x152987,0x00);
842 HAL_DMD_RIU_WriteByte(0x152986,0x00);
843
844 HAL_DMD_RIU_WriteByte(0x111feb,0x18);
845 HAL_DMD_RIU_WriteByte(0x111fea,0x14);
846
847 HAL_DMD_RIU_WriteByte(0x111f74,0x10);
848
849 HAL_DMD_RIU_WriteByte(0x111f77,0x01);
850
851 HAL_DMD_RIU_WriteByte(0x111f79,0x41);
852 HAL_DMD_RIU_WriteByte(0x111f78,0x10);
853
854 HAL_DMD_RIU_WriteByte(0x111fe0,0x08);
855
856 HAL_DMD_RIU_WriteByte(0x111fe3,0x08);
857 HAL_DMD_RIU_WriteByte(0x111fe2,0x10);
858
859 HAL_DMD_RIU_WriteByte(0x111ff0,0x08);
860
861 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
862
863 // SRAM End Address
864 HAL_DMD_RIU_WriteByte(0x111707,0xff);
865 HAL_DMD_RIU_WriteByte(0x111706,0xff);
866
867 // DRAM Disable
868 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
869
870 HAL_DMD_RIU_WriteByte(0x101E39, 0x03); //mux from DMD MCU to HK.
871
872 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
873 }
874
875
876 /***********************************************************************************
877 Subject: Power on initialized function
878 Function: INTERN_DVBC_Power_On_Initialization
879 Parmeter:
880 Return: MS_BOOL
881 Remark:
882 ************************************************************************************/
883
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)884 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
885 {
886 MS_U8 status = true;
887 DBG_INTERN_DVBC(printf("INTERN_DVBC_Power_On_Initialization\n"));
888
889 #if defined(PWS_ENABLE)
890 Mapi_PWS_Stop_VDMCU();
891 #endif
892
893 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
894 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
895 //// Firmware download //////////
896 DBG_INTERN_DVBC(printf("INTERN_DVBC Load DSP...\n"));
897 //MsOS_DelayTask(100);
898
899
900 {
901 if (INTERN_DVBC_LoadDSPCode() == FALSE)
902 {
903 printf("DVB-C Load DSP Code Fail\n");
904 return FALSE;
905 }
906 else
907 {
908 DBG_INTERN_DVBC(printf("DVB-C Load DSP Code OK\n"));
909 }
910 }
911
912 status &= INTERN_DVBC_Reset();
913
914 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
915
916 return status;
917 }
918
919 /************************************************************************************************
920 Subject: Driving control
921 Function: INTERN_DVBC_Driving_Control
922 Parmeter: bInversionEnable : TRUE For High
923 Return: void
924 Remark:
925 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)926 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
927 {
928 MS_U8 u8Temp;
929
930 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
931
932 if (bEnable)
933 {
934 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
935 }
936 else
937 {
938 u8Temp = u8Temp & (~0x01);
939 }
940
941 DBG_INTERN_DVBC(printf("---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp));
942 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
943 }
944 /************************************************************************************************
945 Subject: Clk Inversion control
946 Function: INTERN_DVBC_Clk_Inversion_Control
947 Parmeter: bInversionEnable : TRUE For Inversion Action
948 Return: void
949 Remark:
950 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)951 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
952 {
953 MS_U8 u8Temp;
954
955 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
956
957 if (bInversionEnable)
958 {
959 u8Temp = u8Temp | 0x02; //bit 9: clk inv
960 }
961 else
962 {
963 u8Temp = u8Temp & (~0x02);
964 }
965
966 DBG_INTERN_DVBC(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
967 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
968 }
969 /************************************************************************************************
970 Subject: Transport stream serial/parallel control
971 Function: INTERN_DVBC_Serial_Control
972 Parmeter: bEnable : TRUE For serial
973 Return: MS_BOOL :
974 Remark:
975 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)976 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
977 {
978 MS_U8 status = true;
979 return status;
980
981
982 }
983
984 /************************************************************************************************
985 Subject: TS1 output control
986 Function: INTERN_DVBC_PAD_TS1_Enable
987 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
988 Return: void
989 Remark:
990 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)991 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
992 {
993 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_TS1_Enable... \n"));
994
995 if(flag) // PAD_TS1 Enable TS CLK PAD
996 {
997 //printf("=== TS1_Enable ===\n");
998 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
999 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1000 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1001 }
1002 else // PAD_TS1 Disable TS CLK PAD
1003 {
1004 //printf("=== TS1_Disable ===\n");
1005 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1006 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1007 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1008 }
1009 }
1010
1011 /************************************************************************************************
1012 Subject: channel change config
1013 Function: INTERN_DVBC_Config
1014 Parmeter: BW: bandwidth
1015 Return: MS_BOOL :
1016 Remark:
1017 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1018 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1019 {
1020
1021 MS_U8 status = true;
1022 MS_U8 reg_symrate_l, reg_symrate_h;
1023 //MS_U16 u16Fc = 0;
1024 // force
1025 // u16SymbolRate = 0;
1026 // eQamMode = DMD_DVBC_QAMAUTO;
1027
1028 pu16_symbol_rate_list = pu16_symbol_rate_list;
1029 u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1030
1031 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk));
1032 DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime()));
1033
1034 if (u8TSClk == 0xFF) u8TSClk=0x13;
1035
1036 /*
1037 switch(u32IFFreq)
1038 {
1039 case 36125:
1040 case 36167:
1041 case 36000:
1042 case 6000:
1043 case 4560:
1044 //u16Fc = DVBC_FS - u32IFFreq;
1045 DBG_INTERN_DVBC(printf("Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1046 break;
1047 case 44000:
1048 default:
1049 printf("IF frequency not supported\n");
1050 status = false;
1051 break;
1052 }
1053 */
1054
1055 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1056 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1057
1058 status &= INTERN_DVBC_Reset();
1059
1060 if (eQamMode == DMD_DVBC_QAMAUTO)
1061 {
1062 DBG_INTERN_DVBC(printf("DMD_DVBC_QAMAUTO\n"));
1063 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1064 // give default value.
1065 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1066 }
1067 else
1068 {
1069 DBG_INTERN_DVBC(printf("DMD_DVBC_QAM %d\n", eQamMode));
1070 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1071 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1072 }
1073 // auto symbol rate enable/disable
1074 if (u16SymbolRate == 0)
1075 {
1076 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1077 }
1078 else
1079 {
1080 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1081 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1082 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1083 }
1084 // TS mode
1085 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1086
1087 // IQ Swap
1088 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1089
1090 // Fc
1091 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1092 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1093 // Lif
1094 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1095 // Fif
1096 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1097 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1098
1099 //// INTERN_DVBC system init: DVB-C //////////
1100 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1101
1102 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1103 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1104
1105 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1106 INTERN_DVBC_Show_Demod_Version();
1107 #endif
1108
1109 return status;
1110 }
1111 /************************************************************************************************
1112 Subject: enable hw to lock channel
1113 Function: INTERN_DVBC_Active
1114 Parmeter: bEnable
1115 Return: MS_BOOL
1116 Remark:
1117 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1118 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1119 {
1120 MS_U8 status = true;
1121
1122 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_active\n"));
1123
1124 //// INTERN_DVBC Finite State Machine on/off //////////
1125 #if 0
1126 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1127
1128 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1129 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1130 #else
1131 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1132 #endif
1133
1134 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1135 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1136 return status;
1137 }
1138
1139 #ifdef SUPPORT_ADAPTIVE_TS_CLK
INTERN_DVBC_Adaptive_TS_CLK(void)1140 MS_BOOL INTERN_DVBC_Adaptive_TS_CLK(void)
1141 {
1142 MS_U8 u8_ts_clk=0x00;
1143 MS_U8 TS_Clock_Temp;
1144 MS_U8 CLK_source=0;
1145
1146 u8_ts_clk = HAL_DMD_RIU_ReadByte(0x112615);
1147 CLK_source=(u8_ts_clk>>6);
1148 u8_ts_clk=u8_ts_clk&0x1F;
1149
1150 //reg_atsc_dvb_div_reset =1 ; CLKGEN1
1151 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1152 TS_Clock_Temp=TS_Clock_Temp|0x01;
1153 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1154
1155 //set TS clock source div 5
1156 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1);
1157 if (CLK_source==0)
1158 TS_Clock_Temp &=(~0x01);
1159 else
1160 TS_Clock_Temp |= (0x01);
1161
1162 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp);
1163
1164 //set ts clk, REG_BASE[TOP_CKG_DVBTM_TS + 1] = TS_Clock_Set;
1165 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1166 TS_Clock_Temp=(TS_Clock_Temp&0xE0) |u8_ts_clk ;
1167 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp);
1168
1169
1170 //reg_atsc_dvb_div_reset =0
1171 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1172 TS_Clock_Temp=(TS_Clock_Temp&0xFE);
1173 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1174
1175 // set ts FIFO
1176 // reg_RS_BACKEND
1177 // 0x16 *2 [15:8] reg_dvbt_ts_packet_storage_num=0x15 (extend FIFO)
1178 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ;
1179
1180 // enable ts
1181 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ;
1182 TS_Clock_Temp=TS_Clock_Temp|0x01;
1183 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ;
1184
1185 //debug: re-check ts clock
1186 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1187 TS_Clock_Temp=(TS_Clock_Temp&0x1F) ;
1188
1189 return TRUE;
1190 }
1191
1192
1193
1194
1195
1196
1197
INTERN_DVBC_Locked_Task(void)1198 MS_BOOL INTERN_DVBC_Locked_Task(void)
1199 {
1200 INTERN_DVBC_Adaptive_TS_CLK();
1201
1202 //extension task
1203 {
1204
1205 }
1206
1207 return TRUE;
1208
1209 }
1210
1211 #endif
1212
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)1213 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1214 {
1215 MS_U16 u16Address = 0;
1216 MS_U8 cData = 0;
1217 MS_U8 cBitMask = 0;
1218 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1219 MS_U8 unlock_indicator=0;
1220 #endif
1221 if (fCurrRFPowerDbm < 100.0f)
1222 {
1223 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1224 {
1225 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1226 if (cData > 5)
1227 {
1228 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1229 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1230 }
1231 else
1232 {
1233 if ((fCurrRFPowerDbm<fNoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000))
1234 {
1235 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1236 }
1237 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1238 {
1239 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1240 #ifdef MS_DEBUG
1241 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1242 #endif
1243 return TRUE;
1244 }
1245 }
1246 #ifdef MS_DEBUG
1247 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%f Threshold:%f Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1248 #endif
1249 }
1250 }
1251
1252 {
1253 switch( eType )
1254 {
1255 case DMD_DVBC_GETLOCK_FEC_LOCK:
1256 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1257 #if (INTERN_DVBC_INTERNAL_DEBUG)
1258 INTERN_DVBC_info();
1259 #endif
1260 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_GetLock FSM 0x%x\n",cData));
1261 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1262 MDrv_SYS_DMD_VD_MBX_ReadReg(MBX_REG_BASE + 0x16, &unlock_indicator);
1263 #endif
1264 if (cData == 0x0C)
1265 {
1266
1267 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1268 if(g_dvbc_lock == 0 || unlock_indicator==0x01)
1269 #else
1270 if(g_dvbc_lock == 0)
1271 #endif
1272 {
1273
1274 g_dvbc_lock = 1;
1275 DBG_INTERN_DVBC(printf("[T12][DVBC]lock++++\n"));
1276
1277 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1278 printf("===================================================================\n");
1279 printf("Support adaptive TS CLK in polling mode! \n");
1280 printf("===================================================================\n");
1281 INTERN_DVBC_Locked_Task();
1282 MDrv_SYS_DMD_VD_MBX_WriteReg(MBX_REG_BASE + 0x16, 0x00);
1283 #endif
1284
1285 }
1286 return TRUE;
1287 }
1288 else
1289 {
1290 if(g_dvbc_lock == 1)
1291 {
1292 g_dvbc_lock = 0;
1293 DBG_INTERN_DVBC(printf("[T12][DVBC]unlock----\n"));
1294 }
1295 return FALSE;
1296 }
1297 break;
1298
1299 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1300 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1301 cBitMask = BIT(1);
1302 break;
1303
1304 case DMD_DVBC_GETLOCK_DCR_LOCK:
1305 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1306 cBitMask = BIT(0);
1307 break;
1308
1309 case DMD_DVBC_GETLOCK_AGC_LOCK:
1310 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1311 cBitMask = BIT(0);
1312 break;
1313
1314 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1315 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1316 cBitMask = BIT(2)|BIT(3)|BIT(4);
1317 #ifdef MS_DEBUG
1318 {
1319 MS_U8 reg_frz=0, FSM=0;
1320 MS_U16 u16Timer=0;
1321 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1322 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1323 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1324 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1325 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1326 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1327 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1328 u16Timer=(u16Timer<<8)+reg_frz;
1329 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1330 u16Timer=(u16Timer<<8)+reg_frz;
1331 printf("DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1332 }
1333 #endif
1334 break;
1335
1336 case DMD_DVBC_GETLOCK_ATV_DETECT:
1337 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1338 cBitMask = BIT(1); // check atv
1339 break;
1340
1341 case DMD_DVBC_GETLOCK_TR_LOCK:
1342 #if 0 // 20111108 temporarily solution
1343 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
1344 cBitMask = BIT(4);
1345 break;
1346 #endif
1347 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1348 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1349 cBitMask = BIT(4);
1350 break;
1351
1352 default:
1353 return FALSE;
1354 }
1355
1356 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1357 return FALSE;
1358
1359 if ((cData & cBitMask) != 0)
1360 {
1361 return TRUE;
1362 }
1363
1364 return FALSE;
1365 }
1366
1367 return FALSE;
1368 }
1369
1370
1371 /****************************************************************************
1372 Subject: To get the Post viterbi BER
1373 Function: INTERN_DVBC_GetPostViterbiBer
1374 Parmeter: Quility
1375 Return: E_RESULT_SUCCESS
1376 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1377 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1378 We will not read the Period, and have the "/256/8"
1379 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(float * ber)1380 MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber)
1381 {
1382 MS_BOOL status = true;
1383 MS_U8 reg = 0, reg_frz = 0;
1384 MS_U16 BitErrPeriod;
1385 MS_U32 BitErr;
1386 MS_U16 PktErr;
1387
1388 /////////// Post-Viterbi BER /////////////
1389
1390 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1391 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1392 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1393
1394 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1395 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1396 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1397 BitErrPeriod = reg;
1398
1399 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1400 BitErrPeriod = (BitErrPeriod << 8)|reg;
1401
1402 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1403 // 0x6b [15:8] reg_bit_err_num_15_8
1404 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1405 // 0x6d [15:8] reg_bit_err_num_31_24
1406 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1407 BitErr = reg;
1408
1409 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1410 BitErr = (BitErr << 8)|reg;
1411
1412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1413 BitErr = (BitErr << 8)|reg;
1414
1415 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1416 BitErr = (BitErr << 8)|reg;
1417
1418 INTERN_DVBC_GetPacketErr(&PktErr);
1419
1420 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1421 reg_frz=reg_frz&(~0x03);
1422 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1423
1424 if (BitErrPeriod == 0 ) //protect 0
1425 BitErrPeriod = 1;
1426
1427 if (BitErr <=0 )
1428 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1429 else
1430 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1431
1432 DBG_GET_SIGNAL_DVBC(printf("INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1433
1434 return status;
1435 }
1436
1437
1438 /****************************************************************************
1439 Subject: To get the Packet error
1440 Function: INTERN_DVBC_GetPacketErr
1441 Parmeter: pktErr
1442 Return: E_RESULT_SUCCESS
1443 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1444 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1445 We will not read the Period, and have the "/256/8"
1446 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1447 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1448 {
1449 MS_BOOL status = true;
1450 MS_U8 reg = 0, reg_frz = 0;
1451 MS_U16 PktErr;
1452
1453 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1456
1457 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1458 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1460 PktErr = reg;
1461
1462 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1463 PktErr = (PktErr << 8)|reg;
1464
1465 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1466 reg_frz=reg_frz&(~0x03);
1467 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1468
1469 DBG_GET_SIGNAL_DVBC(printf("INTERN_DVBC PktErr = %d \n ", (int)PktErr));
1470
1471 *pktErr = PktErr;
1472
1473 return status;
1474 }
1475
1476 /****************************************************************************
1477 Subject: Read the signal to noise ratio (SNR)
1478 Function: INTERN_DVBC_GetSNR
1479 Parmeter: None
1480 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1481 Remark:
1482 *****************************************************************************/
INTERN_DVBC_GetSNR(float * f_snr)1483 MS_BOOL INTERN_DVBC_GetSNR(float *f_snr)
1484 {
1485 MS_BOOL status = true;
1486 MS_U8 u8Data = 0, reg_frz = 0;
1487 // MS_U8 freeze = 0;
1488 MS_U16 noisepower = 0;
1489
1490 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1491 {
1492 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1493 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1494 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1495
1496 // read vk
1497 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data);
1498 noisepower = u8Data;
1499 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data);
1500 noisepower = (noisepower<<8)|u8Data;
1501
1502 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1503 reg_frz=reg_frz&(~0x01);
1504 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1505
1506 if(noisepower == 0x0000)
1507 noisepower = 0x0001;
1508
1509 #ifdef MSOS_TYPE_LINUX
1510 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1511 #else
1512 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1513 #endif
1514
1515 }
1516 else
1517 {
1518 *f_snr = 0.0f;
1519 }
1520 return status;
1521
1522
1523 }
1524
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1525 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1526 {
1527 MS_BOOL status = true;
1528 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1529 DMD_DVBC_MODULATION_TYPE Qam_mode;
1530
1531 DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi)));
1532
1533 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1534 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1535 /* Actually, it's more reasonable, that signal level depended on cable input power level
1536 * thougth the signal isn't dvb-t signal.
1537 */
1538 // use pointer of IFAGC table to identify
1539 // case 1: RFAGC from SAR, IFAGC controlled by demod
1540 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1541 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1542 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
1543 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1544 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1545 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
1546 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
1547
1548 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1549
1550 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
1551 {
1552 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
1553 }
1554 else
1555 {
1556 ch_power_db_rel = -100.0f;
1557 }
1558
1559 if(ch_power_db_rel <= -85.0f)
1560 {*strength = 0;}
1561 else if (ch_power_db_rel <= -80.0f)
1562 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
1563 else if (ch_power_db_rel <= -75.0f)
1564 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
1565 else if (ch_power_db_rel <= -70.0f)
1566 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
1567 else if (ch_power_db_rel <= -65.0f)
1568 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
1569 else if (ch_power_db_rel <= -55.0f)
1570 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
1571 else if (ch_power_db_rel <= -45.0f)
1572 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
1573 else
1574 {*strength = 100;}
1575
1576 DBG_GET_SIGNAL_DVBC(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
1577 DBG_GET_SIGNAL_DVBC(printf(">>> SSI = %d <<<\n", (int)*strength));
1578
1579 return status;
1580 }
1581
1582 /****************************************************************************
1583 Subject: To get the DVT Signal quility
1584 Function: INTERN_DVBC_GetSignalQuality
1585 Parmeter: Quility
1586 Return: E_RESULT_SUCCESS
1587 E_RESULT_FAILURE
1588 Remark: Here we have 4 level range
1589 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1590 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1591 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1592 <4>.4th Range => Quality <10
1593 *****************************************************************************/
INTERN_DVBC_GetSignalQuality(MS_U16 * quality,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1594 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1595 {
1596
1597 float fber;
1598 float log_ber;
1599 MS_BOOL status = true;
1600 DMD_DVBC_MODULATION_TYPE Qam_mode;
1601 float f_snr;
1602
1603 fRFPowerDbm = fRFPowerDbm;
1604 status &= INTERN_DVBC_GetSNR(&f_snr);
1605 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
1606 {
1607 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
1608 {
1609 DBG_INTERN_DVBC(printf("\nGetPostViterbiBer Fail!"));
1610 return FALSE;
1611 }
1612
1613 // log_ber = log10(fber)
1614 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
1615
1616 DBG_INTERN_DVBC(printf("\nLog(BER) = %f",log_ber));
1617 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1618 if (Qam_mode == DMD_DVBC_QAM16)
1619 {
1620 if(log_ber <= (-5.5f))
1621 *quality = 100;
1622 else if(log_ber <= (-5.1f))
1623 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
1624 else if(log_ber <= (-4.9f))
1625 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1626 else if(log_ber <= (-4.5f))
1627 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
1628 else if(log_ber <= (-3.7f))
1629 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
1630 else if(log_ber <= (-3.2f))
1631 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1632 else if(log_ber <= (-2.9f))
1633 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1634 else if(log_ber <= (-2.5f))
1635 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
1636 else if(log_ber <= (-2.2f))
1637 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
1638 else if(log_ber <= (-2.0f))
1639 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1640 else
1641 *quality = 0;
1642 }
1643 else if (Qam_mode == DMD_DVBC_QAM32)
1644 {
1645 if(log_ber <= (-5.0f))
1646 *quality = 100;
1647 else if(log_ber <= (-4.7f))
1648 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
1649 else if(log_ber <= (-4.5f))
1650 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
1651 else if(log_ber <= (-3.8f))
1652 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
1653 else if(log_ber <= (-3.5f))
1654 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
1655 else if(log_ber <= (-3.0f))
1656 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
1657 else if(log_ber <= (-2.7f))
1658 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
1659 else if(log_ber <= (-2.4f))
1660 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1661 else if(log_ber <= (-2.2f))
1662 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1663 else if(log_ber <= (-2.0f))
1664 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1665 else
1666 *quality = 0;
1667 }
1668 else if (Qam_mode == DMD_DVBC_QAM64)
1669 {
1670 if(log_ber <= (-5.4f))
1671 *quality = 100;
1672 else if(log_ber <= (-5.1f))
1673 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
1674 else if(log_ber <= (-4.9f))
1675 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1676 else if(log_ber <= (-4.3f))
1677 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
1678 else if(log_ber <= (-3.7f))
1679 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
1680 else if(log_ber <= (-3.2f))
1681 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1682 else if(log_ber <= (-2.9f))
1683 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1684 else if(log_ber <= (-2.4f))
1685 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
1686 else if(log_ber <= (-2.2f))
1687 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1688 else if(log_ber <= (-2.05f))
1689 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
1690 else
1691 *quality = 0;
1692 }
1693 else if (Qam_mode == DMD_DVBC_QAM128)
1694 {
1695 if(log_ber <= (-5.1f))
1696 *quality = 100;
1697 else if(log_ber <= (-4.9f))
1698 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1699 else if(log_ber <= (-4.7f))
1700 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
1701 else if(log_ber <= (-4.1f))
1702 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
1703 else if(log_ber <= (-3.5f))
1704 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
1705 else if(log_ber <= (-3.1f))
1706 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1707 else if(log_ber <= (-2.7f))
1708 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1709 else if(log_ber <= (-2.5f))
1710 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
1711 else if(log_ber <= (-2.06f))
1712 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
1713 //else if(log_ber <= (-2.05))
1714 else
1715 {
1716 if (f_snr >= 27.2f)
1717 *quality = 20;
1718 else if (f_snr >= 25.1f)
1719 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
1720 else
1721 *quality = 0;
1722 }
1723 }
1724 else //256QAM
1725 {
1726 if(log_ber <= (-4.8f))
1727 *quality = 100;
1728 else if(log_ber <= (-4.6f))
1729 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
1730 else if(log_ber <= (-4.4f))
1731 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
1732 else if(log_ber <= (-4.0f))
1733 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
1734 else if(log_ber <= (-3.5f))
1735 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
1736 else if(log_ber <= (-3.1f))
1737 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1738 else if(log_ber <= (-2.7f))
1739 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1740 else if(log_ber <= (-2.4f))
1741 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1742 else if(log_ber <= (-2.06f))
1743 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
1744 //else if(log_ber <= (-2.05))
1745 else
1746 {
1747 if (f_snr >= 29.6f)
1748 *quality = 20;
1749 else if (f_snr >= 27.3f)
1750 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
1751 else
1752 *quality = 0;
1753 }
1754 }
1755 }
1756 else
1757 {
1758 *quality = 0;
1759 }
1760
1761 //DBG_GET_SIGNAL_DVBC(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
1762 DBG_GET_SIGNAL_DVBC(printf("BER = %8.3e\n", fber));
1763 DBG_GET_SIGNAL_DVBC(printf("Signal Quility = %d\n", *quality));
1764 return TRUE;
1765 }
1766
1767 /****************************************************************************
1768 Subject: To get the Cell ID
1769 Function: INTERN_DVBC_Get_CELL_ID
1770 Parmeter: point to return parameter cell_id
1771
1772 Return: TRUE
1773 FALSE
1774 Remark:
1775 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)1776 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
1777 {
1778 MS_BOOL status = true;
1779 MS_U8 value1 = 0;
1780 MS_U8 value2 = 0;
1781
1782 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
1783 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
1784
1785 *cell_id = ((MS_U16)value1<<8)|value2;
1786 return status;
1787 }
1788
1789 /****************************************************************************
1790 Subject: To get the DVBC Carrier Freq Offset
1791 Function: INTERN_DVBC_Get_FreqOffset
1792 Parmeter: Frequency offset (in KHz), bandwidth
1793 Return: E_RESULT_SUCCESS
1794 E_RESULT_FAILURE
1795 Remark:
1796 *****************************************************************************/
INTERN_DVBC_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)1797 MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
1798 {
1799 MS_U16 FreqB, config_Fc=0;
1800 float FreqCfo_offset,f_Fc;
1801 MS_U32 RegCfo_offset, Reg_Fc_over_Fs;
1802 MS_U8 reg_frz = 0, reg = 0;
1803 MS_BOOL status = TRUE;
1804
1805 // no use.
1806 u8BW = u8BW;
1807
1808 DBG_INTERN_DVBC(printf("INTERN_DVBC_Get_FreqOffset\n"));
1809
1810 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1813
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, ®);
1815 RegCfo_offset = reg;
1816 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, ®);
1817 RegCfo_offset = (RegCfo_offset<<8)|reg;
1818 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, ®);
1819 RegCfo_offset = (RegCfo_offset<<8)|reg;
1820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, ®);
1821 RegCfo_offset = (RegCfo_offset<<8)|reg;
1822
1823 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1824 reg_frz=reg_frz&(~0x01);
1825 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1826
1827 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
1828 Reg_Fc_over_Fs = reg;
1829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
1830 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
1831 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
1832 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
1833 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
1834 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
1835
1836 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
1837 config_Fc = reg;
1838 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
1839 config_Fc = (config_Fc<<8)|reg;
1840
1841 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
1842
1843 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
1844
1845 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
1846
1847 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
1848
1849 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
1850 DBG_INTERN_DVBC_LOCK(printf("[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
1851 FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc));
1852
1853 *pFreqOff = FreqCfo_offset;
1854
1855 return status;
1856 }
1857
1858
1859
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)1860 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
1861 {
1862
1863 bPowerOn = bPowerOn;
1864 }
1865
INTERN_DVBC_Power_Save(void)1866 MS_BOOL INTERN_DVBC_Power_Save(void)
1867 {
1868
1869 return TRUE;
1870 }
1871
1872 /****************************************************************************
1873 Subject: To get the current modulation type at the DVB-C Demod
1874 Function: INTERN_DVBC_GetCurrentModulationType
1875 Parmeter: pointer for return QAM type
1876
1877 Return: TRUE
1878 FALSE
1879 Remark:
1880 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)1881 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
1882 {
1883 MS_U8 u8Data=0;
1884
1885 DBG_INTERN_DVBC(printf("INTERN_DVBC_GetCurrentModulationType\n"));
1886
1887
1888 MDrv_SYS_DMD_VD_MBX_ReadReg(0x9cc4, &u8Data);
1889
1890
1891 // printf("@@@@@@ 0x9cc4 pQAMMode = %d \n",u8Data&0x07);
1892
1893 switch(u8Data&0x07)
1894 {
1895 case 0:
1896 *pQAMMode = DMD_DVBC_QAM16;
1897 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=16\n"));
1898 return TRUE;
1899 break;
1900 case 1:
1901 *pQAMMode = DMD_DVBC_QAM32;
1902 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=32\n"));
1903 return TRUE;
1904 break;
1905 case 2:
1906 *pQAMMode = DMD_DVBC_QAM64;
1907 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=64\n"));
1908 return TRUE;
1909 break;
1910 case 3:
1911 *pQAMMode = DMD_DVBC_QAM128;
1912 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=128\n"));
1913 return TRUE;
1914 break;
1915 case 4:
1916 *pQAMMode = DMD_DVBC_QAM256;
1917 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=256\n"));
1918 return TRUE;
1919 break;
1920 default:
1921 *pQAMMode = DMD_DVBC_QAMAUTO;
1922 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=invalid\n"));
1923 return FALSE;
1924 }
1925 }
1926
1927 /****************************************************************************
1928 Subject: To get the current symbol rate at the DVB-C Demod
1929 Function: INTERN_DVBC_GetCurrentSymbolRate
1930 Parmeter: pointer pData for return Symbolrate
1931
1932 Return: TRUE
1933 FALSE
1934 Remark:
1935 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)1936 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
1937 {
1938 MS_U8 tmp = 0;
1939 MS_U16 u16SymbolRateTmp = 0;
1940
1941 // intp
1942 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d2, &tmp);
1943 u16SymbolRateTmp = tmp;
1944 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d1, &tmp);
1945 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
1946
1947 if (abs(u16SymbolRateTmp-6900)<2)
1948 {
1949 u16SymbolRateTmp=6900;
1950 }
1951
1952 if (abs(u16SymbolRateTmp-6875)<2)
1953 {
1954 u16SymbolRateTmp=6875;
1955 }
1956
1957 *u16SymbolRate = u16SymbolRateTmp;
1958
1959 DBG_INTERN_DVBC_LOCK(printf("[dvbc]SR=%d\n",*u16SymbolRate));
1960
1961 return TRUE;
1962 }
1963
1964
1965 /****************************************************************************
1966 Subject: To get the current symbol rate offset at the DVB-C Demod
1967 Function: INTERN_DVBC_GetCurrentSymbolRate
1968 Parmeter: pointer pData for return Symbolrate offset
1969
1970 Return: TRUE
1971 FALSE
1972 Remark:
1973 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 * pData)1974 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
1975 {
1976 MS_U8 u8Data = 0, reg_frz = 0;
1977 MS_U32 u32Data = 0;
1978 // MS_S32 s32Data = 0;
1979 MS_BOOL status = TRUE;
1980 MS_U16 u16SymbolRate = 0;
1981 float f_symb_offset = 0.0f;
1982
1983
1984
1985 // bank 26 0x03 [7] reg_bit_err_num_freeze
1986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
1987 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
1988
1989 // sel, SFO debug output.
1990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
1991 u32Data = u8Data;
1992 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
1993 u32Data = (u32Data<<8)|u8Data;
1994 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
1995 u32Data = (u32Data<<8)|u8Data;
1996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
1997 u32Data = (u32Data<<8)|u8Data;
1998
1999 // bank 26 0x03 [7] reg_bit_err_num_freeze
2000 reg_frz=reg_frz&(~0x80);
2001 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
2002 // s32Data = (MS_S32)(u32Data<<8);
2003
2004 printf("[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2005
2006 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2007
2008 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
2009 f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
2010
2011 *pData = (MS_U16)(f_symb_offset + 0.5f);
2012
2013 DBG_INTERN_DVBC_LOCK(printf("[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset));
2014
2015 return status;
2016 }
2017
INTERN_DVBC_Version(MS_U16 * ver)2018 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2019 {
2020
2021 MS_U8 status = true;
2022 MS_U8 tmp = 0;
2023 MS_U16 u16_INTERN_DVBC_Version;
2024
2025 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2026 u16_INTERN_DVBC_Version = tmp;
2027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2028 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2029 *ver = u16_INTERN_DVBC_Version;
2030
2031 return status;
2032 }
2033
2034
INTERN_DVBC_Show_Demod_Version(void)2035 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2036 {
2037
2038 MS_BOOL status = true;
2039 MS_U16 u16_INTERN_DVBC_Version;
2040
2041 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2042
2043 printf("[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2044
2045 return status;
2046 }
2047
2048
2049
2050 #if (INTERN_DVBC_INTERNAL_DEBUG)
2051
INTERN_DVBC_Show_AGC_Info(void)2052 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2053 {
2054 MS_U8 tmp = 0;
2055 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2056 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2057 MS_U16 if_agc_err = 0;
2058 MS_BOOL status = TRUE;
2059
2060 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2061 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2062 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2063 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2064 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2065 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2066
2067
2068 // select IF gain to read
2069 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2070 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2071
2072 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2073 if_agc_gain = tmp;
2074 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2075 if_agc_gain = (if_agc_gain<<8)|tmp;
2076
2077
2078 // select d1 gain to read.
2079 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2080 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2081
2082 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2083 d1_gain = tmp;
2084 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2085 d1_gain = (d1_gain<<8)|tmp;
2086
2087 // select d2 gain to read.
2088 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2089 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2090
2091 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2092 d2_gain = tmp;
2093 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2094 d2_gain = (d2_gain<<8)|tmp;
2095
2096 // select IF gain err to read
2097 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2098 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2099
2100 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2101 if_agc_err = tmp;
2102 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2103 if_agc_err = (if_agc_err<<8)|tmp;
2104
2105 printf("[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2106 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2107
2108 printf("[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2109
2110 return status;
2111 }
2112
INTERN_DVBC_info(void)2113 void INTERN_DVBC_info(void)
2114 {
2115 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2116 MS_U8 qam,tmp = 0;
2117 MS_U8 fft_u8 = 0;
2118 MS_U16 fft_u16bw = 0;
2119 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2120 float f_snr = 0,f_freq = 0;
2121 DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2122 MS_U16 f_start = 0,f_end = 0;
2123 MS_U8 s0_count = 0;
2124 MS_U8 sc4 = 0,sc3 = 0;
2125 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2126 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2127 MS_U16 count = 0;
2128 MS_U16 fb_i_1,fb_q_1;
2129 MS_U8 e0,e1,e2,e3;
2130 MS_S16 reg_freq;
2131 float freq,mag;
2132
2133
2134
2135 INTERN_DVBC_Version(&version);
2136
2137 // fb_fs
2138 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2139 fb_fs = tmp;
2140 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2141 fb_fs = (fb_fs<<8)|tmp;
2142 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2143 fb_fs = (fb_fs<<8)|tmp;
2144 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2145 fb_fs = (fb_fs<<8)|tmp;
2146 // fc_fs
2147 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2148 fc_fs = tmp;
2149 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2150 fc_fs = (fc_fs<<8)|tmp;
2151 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2152 fc_fs = (fc_fs<<8)|tmp;
2153 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2154 fc_fs = (fc_fs<<8)|tmp;
2155 // crv
2156 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2157 crv = tmp;
2158 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2159 crv = (crv<<8)|tmp;
2160 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2161 crv = (crv<<8)|tmp;
2162 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2163 crv = (crv<<8)|tmp;
2164 // tr_error
2165 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2166 tr_error = tmp;
2167 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2168 tr_error = (tr_error<<8)|tmp;
2169 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2170 tr_error = (tr_error<<8)|tmp;
2171
2172 // intp
2173 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2174 intp = tmp;
2175 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2176 intp = (intp<<8)|tmp;
2177 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2178 intp = (intp<<8)|tmp;
2179 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2180 intp = (intp<<8)|tmp;
2181
2182 // fft info
2183 // intp
2184 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2185 fft_u16bw = tmp;
2186 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2187 fft_u16bw = (fft_u16bw<<8)|tmp;
2188 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2189 fft_u8 = tmp;
2190
2191
2192 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2193 qam = tmp;
2194
2195 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2196 f_start = tmp;
2197 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2198 f_start = (f_start<<8)|tmp;
2199 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2200 f_end = tmp;
2201 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2202 f_end = (f_end<<8)|tmp;
2203 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2204 s0_count = tmp;
2205
2206 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2207 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2208
2209 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2210 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2211 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2212 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2213 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2214 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2215 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2216
2217
2218 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2219
2220 count = 0x400;
2221 while(count--);
2222
2223 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2224 aci_e0 = tmp&0x0f;
2225 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2226 aci_e0 = aci_e0<<8|tmp;
2227
2228 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2229
2230 count = 0x400;
2231 while(count--);
2232
2233
2234 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2235 aci_e1 = tmp&0x0f;
2236 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2237 aci_e1 = aci_e1<<8|tmp;
2238
2239 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2240
2241 count = 0x400;
2242 while(count--);
2243
2244 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2245 aci_e2 = tmp&0x0f;
2246 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2247 aci_e2 = aci_e2<<8|tmp;
2248
2249 // read aci coef
2250 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2251
2252 count = 0x400;
2253 while(count--);
2254
2255 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2256 aci_e3 = tmp&0x0f;
2257 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2258 aci_e3 = aci_e3<<8|tmp;
2259
2260 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2261 fb_i_1 = tmp;
2262 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2263 fb_i_1 = fb_i_1<<8|tmp;
2264
2265 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2266 fb_q_1 = tmp;
2267 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2268 fb_q_1 = fb_q_1<<8|tmp;
2269
2270
2271 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2272 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2273 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2274 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2275
2276 reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2277 freq = (float)reg_freq*45473.0/65536.0;
2278 mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2279
2280
2281 INTERN_DVBC_GetPacketErr(&packetErr);
2282 INTERN_DVBC_GetSNR(&f_snr);
2283 INTERN_DVBC_Show_AGC_Info();
2284 INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2285 INTERN_DVBC_Get_FreqOffset(&f_freq,8);
2286 INTERN_DVBC_GetCurrentSymbolRate(&symb_rate);
2287 INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2288 INTERN_DVBC_GetCurrentModulationType(&QAMMode);
2289
2290 printf("[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2291 printf("[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2292 printf("[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2293 printf("[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2294 printf("[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2295 printf("[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2296 return;
2297 }
2298
2299
2300 #endif
2301
2302 /***********************************************************************************
2303 Subject: read register
2304 Function: MDrv_1210_IIC_Bypass_Mode
2305 Parmeter:
2306 Return:
2307 Remark:
2308 ************************************************************************************/
2309 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2310 //{
2311 // UNUSED(enable);
2312 // if (enable)
2313 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2314 // else
2315 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2316 //}
2317