Home
last modified time | relevance | path

Searched refs:reg (Results 1 – 25 of 84) sorted by relevance

1234

/rockchip-linux_mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_vdpu2.c37 static MPP_RET jpegd_regs_init(JpegRegSet *reg) in jpegd_regs_init() argument
40 memset(reg, 0, sizeof(JpegRegSet)); in jpegd_regs_init()
41 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0; in jpegd_regs_init()
42 reg->reg50_dec_ctrl.sw_dec_scmd_dis = DEC_SCMD_DISABLE; in jpegd_regs_init()
43 reg->reg50_dec_ctrl.sw_dec_latency = DEC_LATENCY_COMPENSATION; in jpegd_regs_init()
45 reg->reg54_endian.sw_dec_in_endian = DEC_BIG_ENDIAN; in jpegd_regs_init()
46 reg->reg54_endian.sw_dec_out_endian = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
47 reg->reg54_endian.sw_dec_strendian_e = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
48 reg->reg54_endian.sw_dec_outswap32_e = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
49 reg->reg54_endian.sw_dec_inswap32_e = 1; in jpegd_regs_init()
[all …]
H A Dhal_jpegd_vdpu1.c44 JpegRegSet *reg = &info->regs; in jpegd_write_code_word_number() local
60 reg->reg16.sw_ac1_code1_cnt = ac_ptr0->bits[0]; in jpegd_write_code_word_number()
61 reg->reg16.sw_ac1_code2_cnt = ac_ptr0->bits[1]; in jpegd_write_code_word_number()
62 reg->reg16.sw_ac1_code3_cnt = ac_ptr0->bits[2]; in jpegd_write_code_word_number()
63 reg->reg16.sw_ac1_code4_cnt = ac_ptr0->bits[3]; in jpegd_write_code_word_number()
64 reg->reg16.sw_ac1_code5_cnt = ac_ptr0->bits[4]; in jpegd_write_code_word_number()
65 reg->reg16.sw_ac1_code6_cnt = ac_ptr0->bits[5]; in jpegd_write_code_word_number()
67 reg->reg17.sw_ac1_code7_cnt = ac_ptr0->bits[6]; in jpegd_write_code_word_number()
68 reg->reg17.sw_ac1_code8_cnt = ac_ptr0->bits[7]; in jpegd_write_code_word_number()
69 reg->reg17.sw_ac1_code9_cnt = ac_ptr0->bits[8]; in jpegd_write_code_word_number()
[all …]
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c221 static void vepu540_h265_set_l2_regs(H265eV54xL2RegSet *reg) in vepu540_h265_set_l2_regs() argument
223 reg->pre_intra_cla0_B0.pre_intra_cla0_m0 = 10; in vepu540_h265_set_l2_regs()
224 reg->pre_intra_cla0_B0.pre_intra_cla0_m1 = 11; in vepu540_h265_set_l2_regs()
225 reg->pre_intra_cla0_B0.pre_intra_cla0_m2 = 12; in vepu540_h265_set_l2_regs()
226 reg->pre_intra_cla0_B0.pre_intra_cla0_m3 = 13; in vepu540_h265_set_l2_regs()
227 reg->pre_intra_cla0_B0.pre_intra_cla0_m4 = 14; in vepu540_h265_set_l2_regs()
228 reg->pre_intra_cla0_B1.pre_intra_cla0_m5 = 9; in vepu540_h265_set_l2_regs()
229 reg->pre_intra_cla0_B1.pre_intra_cla0_m6 = 15; in vepu540_h265_set_l2_regs()
230 reg->pre_intra_cla0_B1.pre_intra_cla0_m7 = 8; in vepu540_h265_set_l2_regs()
231 reg->pre_intra_cla0_B1.pre_intra_cla0_m8 = 16; in vepu540_h265_set_l2_regs()
[all …]
H A Dhal_h265e_vepu510.c413 H265eVepu510Sqi *reg = reg_sqi; in vepu510_h265_set_atr_regs() local
416 reg->block_opt_cfg.block_en = 0; in vepu510_h265_set_atr_regs()
417 reg->cmplx_opt_cfg.cmplx_en = 0; in vepu510_h265_set_atr_regs()
418 reg->line_opt_cfg.line_en = 0; in vepu510_h265_set_atr_regs()
420 reg->block_opt_cfg.block_en = 0; in vepu510_h265_set_atr_regs()
421 reg->cmplx_opt_cfg.cmplx_en = 0; in vepu510_h265_set_atr_regs()
422 reg->line_opt_cfg.line_en = 1; in vepu510_h265_set_atr_regs()
426 reg->block_opt_cfg.block_thre_cst_best_mad = 1000; in vepu510_h265_set_atr_regs()
427 reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39; in vepu510_h265_set_atr_regs()
428 reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3; in vepu510_h265_set_atr_regs()
[all …]
H A Dhal_h265e_vepu580.c401 static void vepu580_h265_sobel_cfg(hevc_vepu580_wgt *reg) in vepu580_h265_sobel_cfg() argument
403 reg->pre_intra_cla0_B0.pre_intra_cla0_m0 = 10; in vepu580_h265_sobel_cfg()
404 reg->pre_intra_cla0_B0.pre_intra_cla0_m1 = 11; in vepu580_h265_sobel_cfg()
405 reg->pre_intra_cla0_B0.pre_intra_cla0_m2 = 12; in vepu580_h265_sobel_cfg()
406 reg->pre_intra_cla0_B0.pre_intra_cla0_m3 = 13; in vepu580_h265_sobel_cfg()
407 reg->pre_intra_cla0_B0.pre_intra_cla0_m4 = 14; in vepu580_h265_sobel_cfg()
409 reg->pre_intra_cla0_B1.pre_intra_cla0_m5 = 9; in vepu580_h265_sobel_cfg()
410 reg->pre_intra_cla0_B1.pre_intra_cla0_m6 = 15; in vepu580_h265_sobel_cfg()
411 reg->pre_intra_cla0_B1.pre_intra_cla0_m7 = 8; in vepu580_h265_sobel_cfg()
412 reg->pre_intra_cla0_B1.pre_intra_cla0_m8 = 16; in vepu580_h265_sobel_cfg()
[all …]
H A Dhal_h265e_vepu540c.c230 static void vepu540c_h265_rdo_cfg (vepu540c_rdo_cfg *reg) in vepu540c_h265_rdo_cfg() argument
236 reg->rdo_segment_cfg.rdo_segment_multi = 28; in vepu540c_h265_rdo_cfg()
237 reg->rdo_segment_cfg.rdo_segment_en = 1; in vepu540c_h265_rdo_cfg()
238 reg->rdo_smear_cfg_comb.rdo_smear_en = 0; in vepu540c_h265_rdo_cfg()
239 reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 9; in vepu540c_h265_rdo_cfg()
240 reg->rdo_segment_cfg.rdo_smear_lvl8_multi = 8; in vepu540c_h265_rdo_cfg()
241 reg->rdo_segment_cfg.rdo_smear_lvl4_multi = 8; in vepu540c_h265_rdo_cfg()
242 reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ; in vepu540c_h265_rdo_cfg()
243 reg->rdo_smear_cfg_comb.rdo_smear_order_state = 0; in vepu540c_h265_rdo_cfg()
244 reg->rdo_smear_cfg_comb.stated_mode = 0; in vepu540c_h265_rdo_cfg()
[all …]
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu511_common.c45 Vepu511OsdRegion *reg = &osd_reg->osd_regions[i]; in vepu511_set_osd() local
52 reg->cfg0.osd_en = region->enable; in vepu511_set_osd()
53 reg->cfg0.osd_range_trns_en = region->range_trns_en; in vepu511_set_osd()
54 reg->cfg0.osd_range_trns_sel = region->range_trns_sel; in vepu511_set_osd()
55 reg->cfg0.osd_fmt = fmt_cfg.format; in vepu511_set_osd()
56 reg->cfg0.osd_rbuv_swap = region->rbuv_swap; in vepu511_set_osd()
57 reg->cfg1.osd_lt_xcrd = region->lt_x; in vepu511_set_osd()
58 reg->cfg1.osd_lt_ycrd = region->lt_y; in vepu511_set_osd()
59 reg->cfg2.osd_rb_xcrd = region->rb_x; in vepu511_set_osd()
60 reg->cfg2.osd_rb_ycrd = region->rb_y; in vepu511_set_osd()
[all …]
H A Dvepu5xx_common.h30 #define SET_OSD_INV_THR(index, reg, region)\ argument
32 reg.osd_ithd_r##index = ENC_DEFAULT_OSD_INV_THR;
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu2_v2.c252 static RK_S32 setup_output_packet(HalH264eVepu2Ctx *ctx, RK_U32 *reg, MppBuffer buf, RK_U32 offset) in setup_output_packet() argument
268 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_STREAM, fd); in setup_output_packet()
276 H264E_HAL_SET_REG(reg, VEPU_REG_STR_BUF_LIMIT, limit); in setup_output_packet()
280 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_MSB, hdr_rem_msb); in setup_output_packet()
281 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_LSB, hdr_rem_lsb); in setup_output_packet()
293 RK_U32 *reg = ctx->regs_set.val; in setup_intra_refresh() local
328 H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val); in setup_intra_refresh()
349 RK_U32 *reg = ctx->regs_set.val; in hal_h264e_vepu2_gen_regs_v2() local
375 first_free_bit = setup_output_packet(ctx, reg, task->output, offset); in hal_h264e_vepu2_gen_regs_v2()
394 H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val); in hal_h264e_vepu2_gen_regs_v2()
[all …]
H A Dhal_h264e_vepu1_v2.c251 static RK_S32 setup_output_packet(HalH264eVepu1Ctx *ctx, RK_U32 *reg, MppBuffer buf, RK_U32 offset) in setup_output_packet() argument
267 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_STREAM, fd); in setup_output_packet()
275 H264E_HAL_SET_REG(reg, VEPU_REG_STR_BUF_LIMIT, limit); in setup_output_packet()
279 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_MSB, hdr_rem_msb); in setup_output_packet()
280 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_LSB, hdr_rem_lsb); in setup_output_packet()
299 RK_U32 *reg = ctx->regs_set.val; in hal_h264e_vepu1_gen_regs_v2() local
326 first_free_bit = setup_output_packet(ctx, reg, task->output, offset); in hal_h264e_vepu1_gen_regs_v2()
341 H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val); //FIXED in hal_h264e_vepu1_gen_regs_v2()
352 H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val); in hal_h264e_vepu1_gen_regs_v2()
356 H264E_HAL_SET_REG(reg, VEPU_REG_MAD_CTRL, val); in hal_h264e_vepu1_gen_regs_v2()
[all …]
H A Dhal_h264e_vepu_v2.h24 #define H264E_HAL_SET_REG(reg, addr, val) \ argument
26 reg[(addr)>>2] = (RK_U32)(val); \
/rockchip-linux_mpp/mpp/hal/rkdec/
H A Dvdpu383_com.c64 void vdpu383_setup_rcb(Vdpu383RegCommonAddr *reg, MppDev dev, in vdpu383_setup_rcb() argument
69 reg->reg140_rcb_strmd_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
70 reg->reg142_rcb_strmd_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
71 reg->reg144_rcb_inter_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
72 reg->reg146_rcb_inter_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
73 reg->reg148_rcb_intra_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
74 reg->reg150_rcb_intra_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
75 reg->reg152_rcb_filterd_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
76 reg->reg154_rcb_filterd_protect_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
77 reg->reg156_rcb_filterd_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu383_setup_rcb()
[all …]
H A Dvdpu34x_com.c43 static RK_S32 update_size_offset(Vdpu34xRcbInfo *info, RK_U32 reg, in update_size_offset() argument
49 info[idx].reg = reg; in update_size_offset()
75 void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info) in vdpu34x_setup_rcb() argument
79 reg->reg139_rcb_dblk_base = fd; in vdpu34x_setup_rcb()
80 reg->reg133_rcb_intra_base = fd; in vdpu34x_setup_rcb()
81 reg->reg134_rcb_transd_row_base = fd; in vdpu34x_setup_rcb()
82 reg->reg136_rcb_streamd_row_base = fd; in vdpu34x_setup_rcb()
83 reg->reg137_rcb_inter_row_base = fd; in vdpu34x_setup_rcb()
84 reg->reg140_rcb_sao_base = fd; in vdpu34x_setup_rcb()
85 reg->reg141_rcb_fbc_base = fd; in vdpu34x_setup_rcb()
[all …]
H A Dvdpu382_com.c43 static RK_S32 update_size_offset(Vdpu382RcbInfo *info, RK_U32 reg, in update_size_offset() argument
49 info[idx].reg = reg; in update_size_offset()
75 void vdpu382_setup_rcb(Vdpu382RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu382RcbInfo *info) in vdpu382_setup_rcb() argument
79 reg->reg139_rcb_dblk_base = fd; in vdpu382_setup_rcb()
80 reg->reg133_rcb_intra_base = fd; in vdpu382_setup_rcb()
81 reg->reg134_rcb_transd_row_base = fd; in vdpu382_setup_rcb()
82 reg->reg136_rcb_streamd_row_base = fd; in vdpu382_setup_rcb()
83 reg->reg137_rcb_inter_row_base = fd; in vdpu382_setup_rcb()
84 reg->reg140_rcb_sao_base = fd; in vdpu382_setup_rcb()
85 reg->reg141_rcb_fbc_base = fd; in vdpu382_setup_rcb()
[all …]
H A Dvdpu384a_com.c78 void vdpu384a_setup_rcb(Vdpu384aRegCommonAddr *reg, MppDev dev, in vdpu384a_setup_rcb() argument
83 reg->reg140_rcb_strmd_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
84 reg->reg142_rcb_strmd_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
85 reg->reg144_rcb_inter_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
86 reg->reg146_rcb_inter_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
87 reg->reg148_rcb_intra_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
88 reg->reg150_rcb_intra_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
89 reg->reg152_rcb_filterd_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
90 reg->reg156_rcb_filterd_tile_row_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
91 reg->reg158_rcb_filterd_tile_col_offset = mpp_buffer_get_fd(buf); in vdpu384a_setup_rcb()
[all …]
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu540c.c45 void *reg; member
783 static void setup_vepu540c_rdo_cfg(vepu540c_rdo_cfg *reg) in setup_vepu540c_rdo_cfg() argument
789 reg->rdo_smear_cfg_comb.rdo_smear_en = 0; in setup_vepu540c_rdo_cfg()
790 reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 9; in setup_vepu540c_rdo_cfg()
791 reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ; in setup_vepu540c_rdo_cfg()
792 reg->rdo_smear_cfg_comb.rdo_smear_order_state = 0; in setup_vepu540c_rdo_cfg()
793 reg->rdo_smear_cfg_comb.stated_mode = 0; in setup_vepu540c_rdo_cfg()
794 reg->rdo_smear_cfg_comb.online_en = 0; in setup_vepu540c_rdo_cfg()
795 reg->rdo_smear_cfg_comb.smear_stride = 0; in setup_vepu540c_rdo_cfg()
796 reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd0 = 0; in setup_vepu540c_rdo_cfg()
[all …]
H A Dhal_h264e_vepu510.c1953 H264eVepu510Sqi *reg = &regs->reg_sqi; in setup_vepu510_anti_flicker() local
1969 p_skip = &reg->rdo_b16_skip; in setup_vepu510_anti_flicker()
1980 p_no_skip = &reg->rdo_b16_inter; in setup_vepu510_anti_flicker()
1989 p_no_skip = &reg->rdo_b16_intra; in setup_vepu510_anti_flicker()
1998 reg->rdo_b16_intra_atf_cnt_thd.thd0 = 1; in setup_vepu510_anti_flicker()
1999 reg->rdo_b16_intra_atf_cnt_thd.thd1 = 4; in setup_vepu510_anti_flicker()
2000 reg->rdo_b16_intra_atf_cnt_thd.thd2 = 1; in setup_vepu510_anti_flicker()
2001 reg->rdo_b16_intra_atf_cnt_thd.thd3 = 4; in setup_vepu510_anti_flicker()
2003 reg->rdo_atf_resi_thd.big_th0 = 16; in setup_vepu510_anti_flicker()
2004 reg->rdo_atf_resi_thd.big_th1 = 16; in setup_vepu510_anti_flicker()
[all …]
H A Dhal_h264e_vepu511.c1915 H264eVepu511Sqi *reg = &regs->reg_sqi; in setup_vepu511_anti_flicker() local
1931 p_skip = &reg->rdo_b16_skip; in setup_vepu511_anti_flicker()
1942 p_no_skip = &reg->rdo_b16_inter; in setup_vepu511_anti_flicker()
1951 p_no_skip = &reg->rdo_b16_intra; in setup_vepu511_anti_flicker()
1960 reg->rdo_b16_intra_atf_cnt_thd.thd0 = 1; in setup_vepu511_anti_flicker()
1961 reg->rdo_b16_intra_atf_cnt_thd.thd1 = 4; in setup_vepu511_anti_flicker()
1962 reg->rdo_b16_intra_atf_cnt_thd.thd2 = 1; in setup_vepu511_anti_flicker()
1963 reg->rdo_b16_intra_atf_cnt_thd.thd3 = 4; in setup_vepu511_anti_flicker()
1965 reg->rdo_atf_resi_thd.big_th0 = 16; in setup_vepu511_anti_flicker()
1966 reg->rdo_atf_resi_thd.big_th1 = 16; in setup_vepu511_anti_flicker()
[all …]
/rockchip-linux_mpp/mpp/vproc/vdpp/
H A Dvdpp.c25 struct vdpp_reg *dst_reg = &ctx->reg; in vdpp_params_to_reg()
317 struct vdpp_reg *reg = NULL; in vdpp_start() local
333 reg = &ctx->reg; in vdpp_start()
338 memset(reg, 0, sizeof(*reg)); in vdpp_start()
398 mpp_req[req_cnt].size = sizeof(reg->common); in vdpp_start()
400 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common); in vdpp_start()
405 mpp_req[req_cnt].size = sizeof(reg->common); in vdpp_start()
407 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common); in vdpp_start()
445 struct vdpp_reg *reg = NULL; in vdpp_done() local
452 reg = &ctx->reg; in vdpp_done()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/vp8d/
H A Dhal_vp8d_vdpu1.c162 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs; in hal_vp8_init_hwcfg() local
165 memset(reg, 0, sizeof(VP8DRegSet_t)); in hal_vp8_init_hwcfg()
167 reg->reg1_interrupt.sw_dec_e = 1; in hal_vp8_init_hwcfg()
169 reg->reg2_dec_ctrl.sw_dec_out_tiled_e = 0; in hal_vp8_init_hwcfg()
170 reg->reg2_dec_ctrl.sw_dec_scmd_dis = 0; in hal_vp8_init_hwcfg()
171 reg->reg2_dec_ctrl.sw_dec_adv_pre_dis = 0; in hal_vp8_init_hwcfg()
172 reg->reg2_dec_ctrl.sw_dec_latency = 0; in hal_vp8_init_hwcfg()
174 reg->reg2_dec_ctrl.sw_dec_in_endian = 1; in hal_vp8_init_hwcfg()
175 reg->reg2_dec_ctrl.sw_dec_out_endian = 1; in hal_vp8_init_hwcfg()
176 reg->reg2_dec_ctrl.sw_dec_inswap32_e = 1; in hal_vp8_init_hwcfg()
[all …]
H A Dhal_vp8d_vdpu2.c164 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs; in hal_vp8_init_hwcfg() local
167 memset(reg, 0, sizeof(VP8DRegSet_t)); in hal_vp8_init_hwcfg()
168 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0; in hal_vp8_init_hwcfg()
169 reg->reg50_dec_ctrl.sw_dec_scmd_dis = 0; in hal_vp8_init_hwcfg()
170 reg->reg50_dec_ctrl.sw_dec_adv_pre_dis = 0; in hal_vp8_init_hwcfg()
171 reg->reg50_dec_ctrl.sw_dec_latency = 0; in hal_vp8_init_hwcfg()
173 reg->reg53_dec_mode = DEC_MODE_VP8; in hal_vp8_init_hwcfg()
175 reg->reg54_endian.sw_dec_in_endian = 1; in hal_vp8_init_hwcfg()
176 reg->reg54_endian.sw_dec_out_endian = 1; in hal_vp8_init_hwcfg()
177 reg->reg54_endian.sw_dec_inswap32_e = 1; in hal_vp8_init_hwcfg()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu2.c34 M2vdVdpu2Reg *reg = NULL; in hal_m2vd_vdpu2_init() local
38 reg = mpp_calloc(M2vdVdpu2Reg, 1); in hal_m2vd_vdpu2_init()
39 if (NULL == reg) { in hal_m2vd_vdpu2_init()
85 p->regs = (void*)reg; in hal_m2vd_vdpu2_init()
93 if (reg) { in hal_m2vd_vdpu2_init()
94 mpp_free(reg); in hal_m2vd_vdpu2_init()
95 reg = NULL; in hal_m2vd_vdpu2_init()
343 wr_cfg.reg = regs; in hal_m2vd_vdpu2_start()
353 rd_cfg.reg = regs; in hal_m2vd_vdpu2_start()
/rockchip-linux_mpp/osal/driver/
H A Dvcodec_service.c437 RK_U32 *reg = (RK_U32*)reg_set; in update_extra_info() local
443 reg[slot->reg_idx] |= (slot->offset << 10); in update_extra_info()
561 VcodecRegCfg *reg = &p->regs[i]; in vcodec_service_init() local
563 reg->reg_size = p->reg_size; in vcodec_service_init()
564 extra_info_init(&reg->extra_info); in vcodec_service_init()
587 send_cfg->reg_set = cfg->reg; in vcodec_service_reg_wr()
603 send_cfg->reg_get = cfg->reg; in vcodec_service_reg_rd()
/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu540c.c252 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_jpege_v540c_start()
262 cfg.reg = &hw_regs->jpeg_table; in hal_jpege_v540c_start()
272 cfg.reg = &hw_regs->reg_base; in hal_jpege_v540c_start()
282 cfg1.reg = &reg_out->hw_status; in hal_jpege_v540c_start()
292 cfg1.reg = &reg_out->st; in hal_jpege_v540c_start()
/rockchip-linux_mpp/osal/inc/
H A Dmpp_device.h48 void *reg; member
55 void *reg; member

1234