Lines Matching refs:reg
413 H265eVepu510Sqi *reg = reg_sqi; in vepu510_h265_set_atr_regs() local
416 reg->block_opt_cfg.block_en = 0; in vepu510_h265_set_atr_regs()
417 reg->cmplx_opt_cfg.cmplx_en = 0; in vepu510_h265_set_atr_regs()
418 reg->line_opt_cfg.line_en = 0; in vepu510_h265_set_atr_regs()
420 reg->block_opt_cfg.block_en = 0; in vepu510_h265_set_atr_regs()
421 reg->cmplx_opt_cfg.cmplx_en = 0; in vepu510_h265_set_atr_regs()
422 reg->line_opt_cfg.line_en = 1; in vepu510_h265_set_atr_regs()
426 reg->block_opt_cfg.block_thre_cst_best_mad = 1000; in vepu510_h265_set_atr_regs()
427 reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39; in vepu510_h265_set_atr_regs()
428 reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3; in vepu510_h265_set_atr_regs()
429 reg->block_opt_cfg.block_delta_qp_flag = 3; in vepu510_h265_set_atr_regs()
431 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000; in vepu510_h265_set_atr_regs()
432 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000; in vepu510_h265_set_atr_regs()
434 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200; in vepu510_h265_set_atr_regs()
435 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977; in vepu510_h265_set_atr_regs()
437 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0; in vepu510_h265_set_atr_regs()
438 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488; in vepu510_h265_set_atr_regs()
440 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 4; in vepu510_h265_set_atr_regs()
441 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 30;//20 in vepu510_h265_set_atr_regs()
442 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 30;//20 in vepu510_h265_set_atr_regs()
443 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;//7 in vepu510_h265_set_atr_regs()
444 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 6;//8 in vepu510_h265_set_atr_regs()
446 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1; in vepu510_h265_set_atr_regs()
447 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 50; in vepu510_h265_set_atr_regs()
448 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 50; in vepu510_h265_set_atr_regs()
450 reg->subj_opt_dqp0.line_thre_qp = 20; in vepu510_h265_set_atr_regs()
451 reg->subj_opt_dqp0.block_strength = 4; in vepu510_h265_set_atr_regs()
452 reg->subj_opt_dqp0.block_thre_qp = 30; in vepu510_h265_set_atr_regs()
453 reg->subj_opt_dqp0.cmplx_strength = 4; in vepu510_h265_set_atr_regs()
454 reg->subj_opt_dqp0.cmplx_thre_qp = 34; in vepu510_h265_set_atr_regs()
455 reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32; in vepu510_h265_set_atr_regs()
457 reg->block_opt_cfg.block_thre_cst_best_mad = 1000; in vepu510_h265_set_atr_regs()
458 reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39; in vepu510_h265_set_atr_regs()
459 reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3; in vepu510_h265_set_atr_regs()
460 reg->block_opt_cfg.block_delta_qp_flag = 3; in vepu510_h265_set_atr_regs()
462 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000; in vepu510_h265_set_atr_regs()
463 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000; in vepu510_h265_set_atr_regs()
465 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200; in vepu510_h265_set_atr_regs()
466 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977; in vepu510_h265_set_atr_regs()
468 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0; in vepu510_h265_set_atr_regs()
469 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488; in vepu510_h265_set_atr_regs()
471 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3; in vepu510_h265_set_atr_regs()
472 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20; in vepu510_h265_set_atr_regs()
473 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20; in vepu510_h265_set_atr_regs()
474 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7; in vepu510_h265_set_atr_regs()
475 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8; in vepu510_h265_set_atr_regs()
477 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1; in vepu510_h265_set_atr_regs()
478 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 60; in vepu510_h265_set_atr_regs()
479 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 60; in vepu510_h265_set_atr_regs()
481 reg->subj_opt_dqp0.line_thre_qp = 25; in vepu510_h265_set_atr_regs()
482 reg->subj_opt_dqp0.block_strength = 4; in vepu510_h265_set_atr_regs()
483 reg->subj_opt_dqp0.block_thre_qp = 30; in vepu510_h265_set_atr_regs()
484 reg->subj_opt_dqp0.cmplx_strength = 4; in vepu510_h265_set_atr_regs()
485 reg->subj_opt_dqp0.cmplx_thre_qp = 34; in vepu510_h265_set_atr_regs()
486 reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32; in vepu510_h265_set_atr_regs()
488 reg->block_opt_cfg.block_thre_cst_best_mad = 1000; in vepu510_h265_set_atr_regs()
489 reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39; in vepu510_h265_set_atr_regs()
490 reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3; in vepu510_h265_set_atr_regs()
491 reg->block_opt_cfg.block_delta_qp_flag = 3; in vepu510_h265_set_atr_regs()
493 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 6000; in vepu510_h265_set_atr_regs()
494 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000; in vepu510_h265_set_atr_regs()
496 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 300; in vepu510_h265_set_atr_regs()
497 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 1280; in vepu510_h265_set_atr_regs()
499 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0; in vepu510_h265_set_atr_regs()
500 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 512; in vepu510_h265_set_atr_regs()
502 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3; in vepu510_h265_set_atr_regs()
503 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20; in vepu510_h265_set_atr_regs()
504 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20; in vepu510_h265_set_atr_regs()
505 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7; in vepu510_h265_set_atr_regs()
506 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8; in vepu510_h265_set_atr_regs()
508 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1; in vepu510_h265_set_atr_regs()
509 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 70; in vepu510_h265_set_atr_regs()
510 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 70; in vepu510_h265_set_atr_regs()
512 reg->subj_opt_dqp0.line_thre_qp = 30; in vepu510_h265_set_atr_regs()
513 reg->subj_opt_dqp0.block_strength = 4; in vepu510_h265_set_atr_regs()
514 reg->subj_opt_dqp0.block_thre_qp = 30; in vepu510_h265_set_atr_regs()
515 reg->subj_opt_dqp0.cmplx_strength = 4; in vepu510_h265_set_atr_regs()
516 reg->subj_opt_dqp0.cmplx_thre_qp = 34; in vepu510_h265_set_atr_regs()
517 reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32; in vepu510_h265_set_atr_regs()
523 H265eVepu510Sqi *reg = reg_sqi; in vepu510_h265_set_anti_blur_regs() local
525 reg->subj_anti_blur_thd.anti_blur_en = 1; in vepu510_h265_set_anti_blur_regs()
527 reg->subj_anti_blur_thd.anti_blur_en = 0; in vepu510_h265_set_anti_blur_regs()
528 reg->subj_anti_blur_thd.blur_low_madi_thd = 5; in vepu510_h265_set_anti_blur_regs()
529 reg->subj_anti_blur_thd.blur_high_madi_thd = 27; in vepu510_h265_set_anti_blur_regs()
530 reg->subj_anti_blur_thd.blur_low_cnt_thd = 0; in vepu510_h265_set_anti_blur_regs()
531 reg->subj_anti_blur_thd.blur_hight_cnt_thd = 0; in vepu510_h265_set_anti_blur_regs()
532 reg->subj_anti_blur_thd.blur_sum_cnt_thd = 5; in vepu510_h265_set_anti_blur_regs()
534 reg->subj_anti_blur_sao.blur_motion_thd = 32; in vepu510_h265_set_anti_blur_regs()
535 reg->subj_anti_blur_sao.sao_ofst_thd_eo_luma = 2; in vepu510_h265_set_anti_blur_regs()
536 reg->subj_anti_blur_sao.sao_ofst_thd_bo_luma = 4; in vepu510_h265_set_anti_blur_regs()
537 reg->subj_anti_blur_sao.sao_ofst_thd_eo_chroma = 2; in vepu510_h265_set_anti_blur_regs()
538 reg->subj_anti_blur_sao.sao_ofst_thd_bo_chroma = 4; in vepu510_h265_set_anti_blur_regs()
621 static void vepu510_h265_rdo_cfg(H265eV510HalContext *ctx, H265eVepu510Sqi *reg, MppEncSceneMode sm) in vepu510_h265_rdo_cfg() argument
623 reg->subj_opt_cfg.subj_opt_en = 1; in vepu510_h265_rdo_cfg()
624 reg->subj_opt_cfg.subj_opt_strength = 3; in vepu510_h265_rdo_cfg()
625 reg->subj_opt_cfg.aq_subj_en = (sm == MPP_ENC_SCENE_MODE_IPC); in vepu510_h265_rdo_cfg()
626 reg->subj_opt_cfg.aq_subj_strength = 4; in vepu510_h265_rdo_cfg()
629 reg->skin_opt_cfg.skin_en = 0; in vepu510_h265_rdo_cfg()
630 reg->skin_opt_cfg.skin_strength = 3; in vepu510_h265_rdo_cfg()
631 reg->skin_opt_cfg.thre_uvsqr16_skin = 128; in vepu510_h265_rdo_cfg()
632 reg->skin_opt_cfg.skin_thre_cst_best_mad = 1000; in vepu510_h265_rdo_cfg()
633 reg->skin_opt_cfg.skin_thre_cst_best_grdn_blk = 98; in vepu510_h265_rdo_cfg()
634 reg->skin_opt_cfg.frame_skin_ratio = 3; in vepu510_h265_rdo_cfg()
635 reg->skin_chrm_thd.thre_sum_mad_intra = 3; in vepu510_h265_rdo_cfg()
636 reg->skin_chrm_thd.thre_sum_grdn_blk_intra = 3; in vepu510_h265_rdo_cfg()
637 reg->skin_chrm_thd.vld_thre_skin_v = 7; in vepu510_h265_rdo_cfg()
638 reg->skin_chrm_thd.thre_min_skin_u = 107; in vepu510_h265_rdo_cfg()
639 reg->skin_chrm_thd.thre_max_skin_u = 129; in vepu510_h265_rdo_cfg()
640 reg->skin_chrm_thd.thre_min_skin_v = 135; in vepu510_h265_rdo_cfg()
641 reg->subj_opt_dqp1.skin_thre_qp = 31; in vepu510_h265_rdo_cfg()
644 reg->cudecis_thd0.base_thre_rough_mad32_intra = 9; in vepu510_h265_rdo_cfg()
645 reg->cudecis_thd0.delta0_thre_rough_mad32_intra = 10; in vepu510_h265_rdo_cfg()
646 reg->cudecis_thd0.delta1_thre_rough_mad32_intra = 55; in vepu510_h265_rdo_cfg()
647 reg->cudecis_thd0.delta2_thre_rough_mad32_intra = 55; in vepu510_h265_rdo_cfg()
648 reg->cudecis_thd0.delta3_thre_rough_mad32_intra = 66; in vepu510_h265_rdo_cfg()
649 reg->cudecis_thd0.delta4_thre_rough_mad32_intra_low5 = 2; in vepu510_h265_rdo_cfg()
652 reg->cudecis_thd1.delta4_thre_rough_mad32_intra_high2 = 2; in vepu510_h265_rdo_cfg()
653 reg->cudecis_thd1.delta5_thre_rough_mad32_intra = 74; in vepu510_h265_rdo_cfg()
654 reg->cudecis_thd1.delta6_thre_rough_mad32_intra = 106; in vepu510_h265_rdo_cfg()
655 reg->cudecis_thd1.base_thre_fine_mad32_intra = 8; in vepu510_h265_rdo_cfg()
656 reg->cudecis_thd1.delta0_thre_fine_mad32_intra = 0; in vepu510_h265_rdo_cfg()
657 reg->cudecis_thd1.delta1_thre_fine_mad32_intra = 13; in vepu510_h265_rdo_cfg()
658 reg->cudecis_thd1.delta2_thre_fine_mad32_intra_low3 = 6; in vepu510_h265_rdo_cfg()
661 reg->cudecis_thd2.delta2_thre_fine_mad32_intra_high2 = 1; in vepu510_h265_rdo_cfg()
662 reg->cudecis_thd2.delta3_thre_fine_mad32_intra = 17; in vepu510_h265_rdo_cfg()
663 reg->cudecis_thd2.delta4_thre_fine_mad32_intra = 23; in vepu510_h265_rdo_cfg()
664 reg->cudecis_thd2.delta5_thre_fine_mad32_intra = 50; in vepu510_h265_rdo_cfg()
665 reg->cudecis_thd2.delta6_thre_fine_mad32_intra = 54; in vepu510_h265_rdo_cfg()
666 reg->cudecis_thd2.base_thre_str_edge_mad32_intra = 6; in vepu510_h265_rdo_cfg()
667 reg->cudecis_thd2.delta0_thre_str_edge_mad32_intra = 0; in vepu510_h265_rdo_cfg()
668 reg->cudecis_thd2.delta1_thre_str_edge_mad32_intra = 0; in vepu510_h265_rdo_cfg()
671 reg->cudecis_thd3.delta2_thre_str_edge_mad32_intra = 3; in vepu510_h265_rdo_cfg()
672 reg->cudecis_thd3.delta3_thre_str_edge_mad32_intra = 8; in vepu510_h265_rdo_cfg()
673 reg->cudecis_thd3.base_thre_str_edge_bgrad32_intra = 25; in vepu510_h265_rdo_cfg()
674 reg->cudecis_thd3.delta0_thre_str_edge_bgrad32_intra = 0; in vepu510_h265_rdo_cfg()
675 reg->cudecis_thd3.delta1_thre_str_edge_bgrad32_intra = 0; in vepu510_h265_rdo_cfg()
676 reg->cudecis_thd3.delta2_thre_str_edge_bgrad32_intra = 7; in vepu510_h265_rdo_cfg()
677 reg->cudecis_thd3.delta3_thre_str_edge_bgrad32_intra = 19; in vepu510_h265_rdo_cfg()
678 reg->cudecis_thd3.base_thre_mad16_intra = 6; in vepu510_h265_rdo_cfg()
679 reg->cudecis_thd3.delta0_thre_mad16_intra = 0; in vepu510_h265_rdo_cfg()
682 reg->cudecis_thd4.delta1_thre_mad16_intra = 3; in vepu510_h265_rdo_cfg()
683 reg->cudecis_thd4.delta2_thre_mad16_intra = 3; in vepu510_h265_rdo_cfg()
684 reg->cudecis_thd4.delta3_thre_mad16_intra = 24; in vepu510_h265_rdo_cfg()
685 reg->cudecis_thd4.delta4_thre_mad16_intra = 28; in vepu510_h265_rdo_cfg()
686 reg->cudecis_thd4.delta5_thre_mad16_intra = 40; in vepu510_h265_rdo_cfg()
687 reg->cudecis_thd4.delta6_thre_mad16_intra = 52; in vepu510_h265_rdo_cfg()
688 reg->cudecis_thd4.delta0_thre_mad16_ratio_intra = 7; in vepu510_h265_rdo_cfg()
691 reg->cudecis_thd5.delta1_thre_mad16_ratio_intra = 7; in vepu510_h265_rdo_cfg()
692 reg->cudecis_thd5.delta2_thre_mad16_ratio_intra = 2; in vepu510_h265_rdo_cfg()
693 reg->cudecis_thd5.delta3_thre_mad16_ratio_intra = 2; in vepu510_h265_rdo_cfg()
694 reg->cudecis_thd5.delta4_thre_mad16_ratio_intra = 0; in vepu510_h265_rdo_cfg()
695 reg->cudecis_thd5.delta5_thre_mad16_ratio_intra = 0; in vepu510_h265_rdo_cfg()
696 reg->cudecis_thd5.delta6_thre_mad16_ratio_intra = 0; in vepu510_h265_rdo_cfg()
697 reg->cudecis_thd5.delta7_thre_mad16_ratio_intra = 4; in vepu510_h265_rdo_cfg()
698 reg->cudecis_thd5.delta0_thre_rough_bgrad32_intra = 1; in vepu510_h265_rdo_cfg()
699 reg->cudecis_thd5.delta1_thre_rough_bgrad32_intra = 5; in vepu510_h265_rdo_cfg()
700 reg->cudecis_thd5.delta2_thre_rough_bgrad32_intra_low4 = 8; in vepu510_h265_rdo_cfg()
703 reg->cudecis_thd6.delta2_thre_rough_bgrad32_intra_high2 = 2; in vepu510_h265_rdo_cfg()
704 reg->cudecis_thd6.delta3_thre_rough_bgrad32_intra = 540; in vepu510_h265_rdo_cfg()
705 reg->cudecis_thd6.delta4_thre_rough_bgrad32_intra = 692; in vepu510_h265_rdo_cfg()
706 reg->cudecis_thd6.delta5_thre_rough_bgrad32_intra_low10 = 866; in vepu510_h265_rdo_cfg()
709 reg->cudecis_thd7.delta5_thre_rough_bgrad32_intra_high1 = 1; in vepu510_h265_rdo_cfg()
710 reg->cudecis_thd7.delta6_thre_rough_bgrad32_intra = 3286; in vepu510_h265_rdo_cfg()
711 reg->cudecis_thd7.delta7_thre_rough_bgrad32_intra = 6620; in vepu510_h265_rdo_cfg()
712 reg->cudecis_thd7.delta0_thre_bgrad16_ratio_intra = 8; in vepu510_h265_rdo_cfg()
713 reg->cudecis_thd7.delta1_thre_bgrad16_ratio_intra_low2 = 3; in vepu510_h265_rdo_cfg()
716 reg->cudecis_thdt8.delta1_thre_bgrad16_ratio_intra_high2 = 2; in vepu510_h265_rdo_cfg()
717 reg->cudecis_thdt8.delta2_thre_bgrad16_ratio_intra = 15; in vepu510_h265_rdo_cfg()
718 reg->cudecis_thdt8.delta3_thre_bgrad16_ratio_intra = 15; in vepu510_h265_rdo_cfg()
719 reg->cudecis_thdt8.delta4_thre_bgrad16_ratio_intra = 13; in vepu510_h265_rdo_cfg()
720 reg->cudecis_thdt8.delta5_thre_bgrad16_ratio_intra = 13; in vepu510_h265_rdo_cfg()
721 reg->cudecis_thdt8.delta6_thre_bgrad16_ratio_intra = 7; in vepu510_h265_rdo_cfg()
722 reg->cudecis_thdt8.delta7_thre_bgrad16_ratio_intra = 15; in vepu510_h265_rdo_cfg()
723 reg->cudecis_thdt8.delta0_thre_fme_ratio_inter = 4; in vepu510_h265_rdo_cfg()
724 reg->cudecis_thdt8.delta1_thre_fme_ratio_inter = 4; in vepu510_h265_rdo_cfg()
727 reg->cudecis_thd9.delta2_thre_fme_ratio_inter = 3; in vepu510_h265_rdo_cfg()
728 reg->cudecis_thd9.delta3_thre_fme_ratio_inter = 2; in vepu510_h265_rdo_cfg()
729 reg->cudecis_thd9.delta4_thre_fme_ratio_inter = 0; in vepu510_h265_rdo_cfg()
730 reg->cudecis_thd9.delta5_thre_fme_ratio_inter = 0; in vepu510_h265_rdo_cfg()
731 reg->cudecis_thd9.delta6_thre_fme_ratio_inter = 0; in vepu510_h265_rdo_cfg()
732 reg->cudecis_thd9.delta7_thre_fme_ratio_inter = 0; in vepu510_h265_rdo_cfg()
733 reg->cudecis_thd9.base_thre_fme32_inter = 4; in vepu510_h265_rdo_cfg()
734 reg->cudecis_thd9.delta0_thre_fme32_inter = 2; in vepu510_h265_rdo_cfg()
735 reg->cudecis_thd9.delta1_thre_fme32_inter = 7; in vepu510_h265_rdo_cfg()
736 reg->cudecis_thd9.delta2_thre_fme32_inter = 12; in vepu510_h265_rdo_cfg()
739 reg->cudecis_thd10.delta3_thre_fme32_inter = 23; in vepu510_h265_rdo_cfg()
740 reg->cudecis_thd10.delta4_thre_fme32_inter = 41; in vepu510_h265_rdo_cfg()
741 reg->cudecis_thd10.delta5_thre_fme32_inter = 71; in vepu510_h265_rdo_cfg()
742 reg->cudecis_thd10.delta6_thre_fme32_inter = 123; in vepu510_h265_rdo_cfg()
743 reg->cudecis_thd10.thre_cme32_inter = 48; in vepu510_h265_rdo_cfg()
746 reg->cudecis_thd11.delta0_thre_mad_fme_ratio_inter = 0; in vepu510_h265_rdo_cfg()
747 reg->cudecis_thd11.delta1_thre_mad_fme_ratio_inter = 7; in vepu510_h265_rdo_cfg()
748 reg->cudecis_thd11.delta2_thre_mad_fme_ratio_inter = 7; in vepu510_h265_rdo_cfg()
749 reg->cudecis_thd11.delta3_thre_mad_fme_ratio_inter = 6; in vepu510_h265_rdo_cfg()
750 reg->cudecis_thd11.delta4_thre_mad_fme_ratio_inter = 5; in vepu510_h265_rdo_cfg()
751 reg->cudecis_thd11.delta5_thre_mad_fme_ratio_inter = 4; in vepu510_h265_rdo_cfg()
752 reg->cudecis_thd11.delta6_thre_mad_fme_ratio_inter = 4; in vepu510_h265_rdo_cfg()
753 reg->cudecis_thd11.delta7_thre_mad_fme_ratio_inter = 4; in vepu510_h265_rdo_cfg()
755 vepu510_h265_set_anti_stripe_regs(reg, ctx->cfg->tune.atl_str); in vepu510_h265_rdo_cfg()
757 vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_i); in vepu510_h265_rdo_cfg()
759 vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_p); in vepu510_h265_rdo_cfg()
762 vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_i); in vepu510_h265_rdo_cfg()
764 vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_p); in vepu510_h265_rdo_cfg()
767 static void vepu510_h265_atf_cfg(H265eVepu510Sqi *reg, RK_S32 atf_str) in vepu510_h265_atf_cfg() argument
772 p_rdo_skip = ®->rdo_b32_skip; in vepu510_h265_atf_cfg()
782 p_rdo_noskip = ®->rdo_b32_inter; in vepu510_h265_atf_cfg()
790 p_rdo_noskip = ®->rdo_b32_intra; in vepu510_h265_atf_cfg()
798 p_rdo_skip = ®->rdo_b16_skip; in vepu510_h265_atf_cfg()
809 p_rdo_noskip = ®->rdo_b16_inter; in vepu510_h265_atf_cfg()
818 p_rdo_noskip = ®->rdo_b16_intra; in vepu510_h265_atf_cfg()
828 static void vepu510_h265_smear_cfg(H265eVepu510Sqi *reg, H265eV510HalContext *ctx) in vepu510_h265_smear_cfg() argument
854 reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep0 = 64; in vepu510_h265_smear_cfg()
855 reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep1 = 32; in vepu510_h265_smear_cfg()
856 reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep2 = 16; in vepu510_h265_smear_cfg()
857 …reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep0 = smear_common_intra_r_dep0[deblur_str… in vepu510_h265_smear_cfg()
858 …reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep1 = smear_common_intra_r_dep1[deblur_str… in vepu510_h265_smear_cfg()
861 reg->smear_opt_cfg0.anti_smear_en = 1; in vepu510_h265_smear_cfg()
863 reg->smear_opt_cfg0.anti_smear_en = 0; in vepu510_h265_smear_cfg()
864 …reg->smear_opt_cfg0.smear_strength = smear_strength[deblur_str] + smear_flag_bndry_wg… in vepu510_h265_smear_cfg()
865 reg->smear_opt_cfg0.thre_mv_inconfor_cime = 8; in vepu510_h265_smear_cfg()
866 reg->smear_opt_cfg0.thre_mv_confor_cime = 2; in vepu510_h265_smear_cfg()
867 reg->smear_opt_cfg0.thre_mv_inconfor_cime_gmv = 8; in vepu510_h265_smear_cfg()
868 reg->smear_opt_cfg0.thre_mv_confor_cime_gmv = 2; in vepu510_h265_smear_cfg()
869 reg->smear_opt_cfg0.thre_num_mv_confor_cime = 3; in vepu510_h265_smear_cfg()
870 reg->smear_opt_cfg0.thre_num_mv_confor_cime_gmv = 2; in vepu510_h265_smear_cfg()
871 reg->smear_opt_cfg0.frm_static = 1; in vepu510_h265_smear_cfg()
873 …if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % fram… in vepu510_h265_smear_cfg()
874 reg->smear_opt_cfg0.smear_load_en = 0; in vepu510_h265_smear_cfg()
876 reg->smear_opt_cfg0.smear_load_en = 1; in vepu510_h265_smear_cfg()
879 …if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % fram… in vepu510_h265_smear_cfg()
880 reg->smear_opt_cfg0.smear_stor_en = 0; in vepu510_h265_smear_cfg()
882 reg->smear_opt_cfg0.smear_stor_en = 1; in vepu510_h265_smear_cfg()
885 reg->smear_opt_cfg1.dist0_frm_avg = 0; in vepu510_h265_smear_cfg()
886 reg->smear_opt_cfg1.thre_dsp_static = 10; in vepu510_h265_smear_cfg()
887 reg->smear_opt_cfg1.thre_dsp_mov = 15; in vepu510_h265_smear_cfg()
888 reg->smear_opt_cfg1.thre_dist_mv_confor_cime = 32; in vepu510_h265_smear_cfg()
890 reg->smear_madp_thd.thre_madp_stc_dep0 = 10; in vepu510_h265_smear_cfg()
891 reg->smear_madp_thd.thre_madp_stc_dep1 = 8; in vepu510_h265_smear_cfg()
892 reg->smear_madp_thd.thre_madp_stc_dep2 = 8; in vepu510_h265_smear_cfg()
893 reg->smear_madp_thd.thre_madp_mov_dep0 = 16; in vepu510_h265_smear_cfg()
894 reg->smear_madp_thd.thre_madp_mov_dep1 = 18; in vepu510_h265_smear_cfg()
895 reg->smear_madp_thd.thre_madp_mov_dep2 = 20; in vepu510_h265_smear_cfg()
897 reg->smear_stat_thd.thre_num_pt_stc_dep0 = 47; in vepu510_h265_smear_cfg()
898 reg->smear_stat_thd.thre_num_pt_stc_dep1 = 11; in vepu510_h265_smear_cfg()
899 reg->smear_stat_thd.thre_num_pt_stc_dep2 = 3; in vepu510_h265_smear_cfg()
900 reg->smear_stat_thd.thre_num_pt_mov_dep0 = 47; in vepu510_h265_smear_cfg()
901 reg->smear_stat_thd.thre_num_pt_mov_dep1 = 11; in vepu510_h265_smear_cfg()
902 reg->smear_stat_thd.thre_num_pt_mov_dep2 = 3; in vepu510_h265_smear_cfg()
904 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv0 = 21; in vepu510_h265_smear_cfg()
905 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv1 = 16; in vepu510_h265_smear_cfg()
906 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv0 = 48; in vepu510_h265_smear_cfg()
907 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv1 = 34; in vepu510_h265_smear_cfg()
909 reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv2 = 32; in vepu510_h265_smear_cfg()
910 reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv3 = 29; in vepu510_h265_smear_cfg()
911 reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv4 = 27; in vepu510_h265_smear_cfg()
913 reg->smear_min_bndry_gmv.thre_min_num_confor_csu0_bndry_cime_gmv = 0; in vepu510_h265_smear_cfg()
914 reg->smear_min_bndry_gmv.thre_max_num_confor_csu0_bndry_cime_gmv = 3; in vepu510_h265_smear_cfg()
915 reg->smear_min_bndry_gmv.thre_min_num_inconfor_csu0_bndry_cime_gmv = 0; in vepu510_h265_smear_cfg()
916 reg->smear_min_bndry_gmv.thre_max_num_inconfor_csu0_bndry_cime_gmv = 3; in vepu510_h265_smear_cfg()
917 reg->smear_min_bndry_gmv.thre_split_dep0 = 2; in vepu510_h265_smear_cfg()
918 reg->smear_min_bndry_gmv.thre_zero_srgn = 8; in vepu510_h265_smear_cfg()
919 reg->smear_min_bndry_gmv.madi_thre_dep0 = 22; in vepu510_h265_smear_cfg()
920 reg->smear_min_bndry_gmv.madi_thre_dep1 = 18; in vepu510_h265_smear_cfg()
922 reg->smear_madp_cov_thd.thre_madp_stc_cover0 = smear_thre_madp_stc_cover0[deblur_str]; in vepu510_h265_smear_cfg()
923 reg->smear_madp_cov_thd.thre_madp_stc_cover1 = smear_thre_madp_stc_cover1[deblur_str]; in vepu510_h265_smear_cfg()
924 reg->smear_madp_cov_thd.thre_madp_mov_cover0 = smear_thre_madp_mov_cover0[deblur_str]; in vepu510_h265_smear_cfg()
925 reg->smear_madp_cov_thd.thre_madp_mov_cover1 = smear_thre_madp_mov_cover1[deblur_str]; in vepu510_h265_smear_cfg()
926 …reg->smear_madp_cov_thd.smear_qp_strength = smear_qp_strength[deblur_str] + smear_flag_cover… in vepu510_h265_smear_cfg()
927 reg->smear_madp_cov_thd.smear_thre_qp = 30; in vepu510_h265_smear_cfg()
929 …reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep0 = smear_bndry_intra_r_dep0[deblur_str] + smear… in vepu510_h265_smear_cfg()
930 …reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep1 = smear_bndry_intra_r_dep1[deblur_str] + smear… in vepu510_h265_smear_cfg()
2096 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v510_start()
2113 cfg.reg = &hw_regs->reg_frm; in hal_h265e_v510_start()
2133 cfg.reg = &hw_regs->reg_rc_roi; in hal_h265e_v510_start()
2150 cfg.reg = &hw_regs->reg_param; in hal_h265e_v510_start()
2167 cfg.reg = &hw_regs->reg_sqi; in hal_h265e_v510_start()
2177 cfg.reg = &hw_regs->reg_scl; in hal_h265e_v510_start()
2193 cfg1.reg = ®_out->hw_status; in hal_h265e_v510_start()
2203 cfg1.reg = ®_out->st; in hal_h265e_v510_start()