252 static RK_S32 setup_output_packet(HalH264eVepu2Ctx *ctx, RK_U32 *reg, MppBuffer buf, RK_U32 offset)  in setup_output_packet()  argument
268     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_STREAM, fd);  in setup_output_packet()
276     H264E_HAL_SET_REG(reg, VEPU_REG_STR_BUF_LIMIT, limit);  in setup_output_packet()
280     H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_MSB, hdr_rem_msb);  in setup_output_packet()
281     H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_LSB, hdr_rem_lsb);  in setup_output_packet()
293     RK_U32 *reg = ctx->regs_set.val;  in setup_intra_refresh()  local
328     H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val);  in setup_intra_refresh()
349     RK_U32 *reg = ctx->regs_set.val;  in hal_h264e_vepu2_gen_regs_v2()  local
375     first_free_bit = setup_output_packet(ctx, reg, task->output, offset);  in hal_h264e_vepu2_gen_regs_v2()
394     H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val);  in hal_h264e_vepu2_gen_regs_v2()
396     H264E_HAL_SET_REG(reg, VEPU_QP_ADJUST_MAD_DELTA_ROI,  in hal_h264e_vepu2_gen_regs_v2()
411     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL0, val);  in hal_h264e_vepu2_gen_regs_v2()
427     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET, val);  in hal_h264e_vepu2_gen_regs_v2()
434     H264E_HAL_SET_REG(reg, VEPU_REG_INPUT_LUMA_INFO, val);  in hal_h264e_vepu2_gen_regs_v2()
438     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val);  in hal_h264e_vepu2_gen_regs_v2()
442     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val);  in hal_h264e_vepu2_gen_regs_v2()
446     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val);  in hal_h264e_vepu2_gen_regs_v2()
450     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val);  in hal_h264e_vepu2_gen_regs_v2()
454     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val);  in hal_h264e_vepu2_gen_regs_v2()
458     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(0), val);  in hal_h264e_vepu2_gen_regs_v2()
462     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(1), val);  in hal_h264e_vepu2_gen_regs_v2()
466     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(2), val);  in hal_h264e_vepu2_gen_regs_v2()
475     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_DELTA_QP, val);  in hal_h264e_vepu2_gen_regs_v2()
481     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL1, val);  in hal_h264e_vepu2_gen_regs_v2()
485     H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_INTER_MODE, val);  in hal_h264e_vepu2_gen_regs_v2()
498     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL2, val);  in hal_h264e_vepu2_gen_regs_v2()
500     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_NEXT_PIC, 0);  in hal_h264e_vepu2_gen_regs_v2()
501     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_MV_OUT, 0);  in hal_h264e_vepu2_gen_regs_v2()
506     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_CABAC_TBL, cabac_table_fd);  in hal_h264e_vepu2_gen_regs_v2()
512     H264E_HAL_SET_REG(reg, VEPU_REG_ROI1, val);  in hal_h264e_vepu2_gen_regs_v2()
518     H264E_HAL_SET_REG(reg, VEPU_REG_ROI2, val);  in hal_h264e_vepu2_gen_regs_v2()
519     H264E_HAL_SET_REG(reg, VEPU_REG_STABLILIZATION_OUTPUT, 0);  in hal_h264e_vepu2_gen_regs_v2()
523     H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF1, val);  in hal_h264e_vepu2_gen_regs_v2()
527     H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF2, val);  in hal_h264e_vepu2_gen_regs_v2()
530     H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF3, val);  in hal_h264e_vepu2_gen_regs_v2()
535     H264E_HAL_SET_REG(reg, VEPU_REG_RGB_MASK_MSB, val); //FIXED  in hal_h264e_vepu2_gen_regs_v2()
549     H264E_HAL_SET_REG(reg, VEPU_REG_MV_PENALTY, val);  in hal_h264e_vepu2_gen_regs_v2()
555     H264E_HAL_SET_REG(reg, VEPU_REG_QP_VAL, val);  in hal_h264e_vepu2_gen_regs_v2()
558     H264E_HAL_SET_REG(reg, VEPU_REG_MVC_RELATE, val);  in hal_h264e_vepu2_gen_regs_v2()
566     H264E_HAL_SET_REG(reg, VEPU_REG_DATA_ENDIAN, val);  in hal_h264e_vepu2_gen_regs_v2()
571     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL3, val);  in hal_h264e_vepu2_gen_regs_v2()
574     H264E_HAL_SET_REG(reg, VEPU_REG_INTERRUPT, val);  in hal_h264e_vepu2_gen_regs_v2()
590             H264E_HAL_SET_REG(reg, VEPU_REG_DMV_PENALTY_TBL(i / 4), val);  in hal_h264e_vepu2_gen_regs_v2()
600             H264E_HAL_SET_REG(reg, VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i / 4), val);  in hal_h264e_vepu2_gen_regs_v2()
605     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_LUMA, hw_addr->orig[0]);  in hal_h264e_vepu2_gen_regs_v2()
609     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CB, hw_addr->orig[1]);  in hal_h264e_vepu2_gen_regs_v2()
613     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CR, hw_addr->orig[2]);  in hal_h264e_vepu2_gen_regs_v2()
621     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_CTRL, nal_size_table_fd);  in hal_h264e_vepu2_gen_regs_v2()
623     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_LUMA,   hw_addr->recn[0]);  in hal_h264e_vepu2_gen_regs_v2()
624     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_CHROMA, hw_addr->recn[1]);  in hal_h264e_vepu2_gen_regs_v2()
626     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_LUMA,   hw_addr->refr[0]);  in hal_h264e_vepu2_gen_regs_v2()
627     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_CHROMA, hw_addr->refr[1]);  in hal_h264e_vepu2_gen_regs_v2()
636     H264E_HAL_SET_REG(reg, VEPU_REG_ENCODE_START, val);  in hal_h264e_vepu2_gen_regs_v2()
658             wr_cfg.reg = &ctx->regs_set;  in hal_h264e_vepu2_start_v2()
668             rd_cfg.reg = &ctx->regs_get;  in hal_h264e_vepu2_start_v2()
692 static void h264e_vepu2_get_mbrc(HalH264eVepuMbRc *mb_rc, H264eVpu2RegSet *reg)  in h264e_vepu2_get_mbrc()  argument
698     RK_U32 *reg_val = reg->val;  in h264e_vepu2_get_mbrc()