164     VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs;  in hal_vp8_init_hwcfg()  local
167     memset(reg, 0, sizeof(VP8DRegSet_t));  in hal_vp8_init_hwcfg()
168     reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0;  in hal_vp8_init_hwcfg()
169     reg->reg50_dec_ctrl.sw_dec_scmd_dis    = 0;  in hal_vp8_init_hwcfg()
170     reg->reg50_dec_ctrl.sw_dec_adv_pre_dis = 0;  in hal_vp8_init_hwcfg()
171     reg->reg50_dec_ctrl.sw_dec_latency     = 0;  in hal_vp8_init_hwcfg()
173     reg->reg53_dec_mode =  DEC_MODE_VP8;  in hal_vp8_init_hwcfg()
175     reg->reg54_endian.sw_dec_in_endian     = 1;  in hal_vp8_init_hwcfg()
176     reg->reg54_endian.sw_dec_out_endian    = 1;  in hal_vp8_init_hwcfg()
177     reg->reg54_endian.sw_dec_inswap32_e    = 1;  in hal_vp8_init_hwcfg()
178     reg->reg54_endian.sw_dec_outswap32_e   = 1;  in hal_vp8_init_hwcfg()
179     reg->reg54_endian.sw_dec_strswap32_e   = 1;  in hal_vp8_init_hwcfg()
180     reg->reg54_endian.sw_dec_strendian_e   = 1;  in hal_vp8_init_hwcfg()
182     reg->reg55_Interrupt.sw_dec_irq = 0;  in hal_vp8_init_hwcfg()
184     reg->reg56_axi_ctrl.sw_dec_axi_rn_id     = 0;  in hal_vp8_init_hwcfg()
185     reg->reg56_axi_ctrl.sw_dec_axi_wr_id     = 0;  in hal_vp8_init_hwcfg()
187     reg->reg56_axi_ctrl.sw_dec_data_disc_e   = 0;  in hal_vp8_init_hwcfg()
188     reg->reg56_axi_ctrl.sw_dec_max_burst     = 16;  in hal_vp8_init_hwcfg()
189     reg->reg57_enable_ctrl.sw_dec_timeout_e  = 1;  in hal_vp8_init_hwcfg()
190     reg->reg57_enable_ctrl.sw_dec_clk_gate_e = 1;  in hal_vp8_init_hwcfg()
191     reg->reg57_enable_ctrl.sw_dec_out_dis = 0;  in hal_vp8_init_hwcfg()
193     reg->reg149_segment_map_base = mpp_buffer_get_fd(ctx->seg_map);  in hal_vp8_init_hwcfg()
194     reg->reg61_qtable_base = mpp_buffer_get_fd(ctx->probe_table);  in hal_vp8_init_hwcfg()
655         wr_cfg.reg = regs;  in hal_vp8d_vdpu2_start()
665         rd_cfg.reg = regs;  in hal_vp8d_vdpu2_start()