251 static RK_S32 setup_output_packet(HalH264eVepu1Ctx *ctx, RK_U32 *reg, MppBuffer buf, RK_U32 offset)  in setup_output_packet()  argument
267     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_STREAM, fd);  in setup_output_packet()
275     H264E_HAL_SET_REG(reg, VEPU_REG_STR_BUF_LIMIT, limit);  in setup_output_packet()
279     H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_MSB, hdr_rem_msb);  in setup_output_packet()
280     H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_LSB, hdr_rem_lsb);  in setup_output_packet()
299     RK_U32 *reg = ctx->regs_set.val;  in hal_h264e_vepu1_gen_regs_v2()  local
326     first_free_bit = setup_output_packet(ctx, reg, task->output, offset);  in hal_h264e_vepu1_gen_regs_v2()
341     H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val); //FIXED  in hal_h264e_vepu1_gen_regs_v2()
352     H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val);  in hal_h264e_vepu1_gen_regs_v2()
356     H264E_HAL_SET_REG(reg, VEPU_REG_MAD_CTRL, val);  in hal_h264e_vepu1_gen_regs_v2()
372     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL2, val);  in hal_h264e_vepu1_gen_regs_v2()
383     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL_4, val);  in hal_h264e_vepu1_gen_regs_v2()
386     H264E_HAL_SET_REG(reg, VEPU_REG_RLC_CTRL, val);  in hal_h264e_vepu1_gen_regs_v2()
397     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_INPUT_IMAGE_CTRL, val);  in hal_h264e_vepu1_gen_regs_v2()
401     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val);  in hal_h264e_vepu1_gen_regs_v2()
405     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val);  in hal_h264e_vepu1_gen_regs_v2()
409     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val);  in hal_h264e_vepu1_gen_regs_v2()
413     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val);  in hal_h264e_vepu1_gen_regs_v2()
417     H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val);  in hal_h264e_vepu1_gen_regs_v2()
421     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(0), val);  in hal_h264e_vepu1_gen_regs_v2()
425     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(1), val);  in hal_h264e_vepu1_gen_regs_v2()
429     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(2), val);  in hal_h264e_vepu1_gen_regs_v2()
438     H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_DELTA_QP, val);  in hal_h264e_vepu1_gen_regs_v2()
448     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL0, val);  in hal_h264e_vepu1_gen_regs_v2()
450     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_NEXT_PIC, 0);  in hal_h264e_vepu1_gen_regs_v2()
451     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_MV_OUT, 0);  in hal_h264e_vepu1_gen_regs_v2()
456     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_CABAC_TBL, cabac_table_fd);  in hal_h264e_vepu1_gen_regs_v2()
462     H264E_HAL_SET_REG(reg, VEPU_REG_ROI1, val);  in hal_h264e_vepu1_gen_regs_v2()
468     H264E_HAL_SET_REG(reg, VEPU_REG_ROI2, val);  in hal_h264e_vepu1_gen_regs_v2()
469     H264E_HAL_SET_REG(reg, VEPU_REG_STABLILIZATION_OUTPUT, 0);  in hal_h264e_vepu1_gen_regs_v2()
473     H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF1, val);  in hal_h264e_vepu1_gen_regs_v2()
477     H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF2, val);  in hal_h264e_vepu1_gen_regs_v2()
483     H264E_HAL_SET_REG(reg, VEPU_REG_RGB_MASK_MSB, val);  in hal_h264e_vepu1_gen_regs_v2()
497     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL3, val);  in hal_h264e_vepu1_gen_regs_v2()
503     H264E_HAL_SET_REG(reg, VEPU_REG_QP_VAL, val);  in hal_h264e_vepu1_gen_regs_v2()
506     H264E_HAL_SET_REG(reg, VEPU_REG_MVC_RELATE, val);  in hal_h264e_vepu1_gen_regs_v2()
511     H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL1, val);  in hal_h264e_vepu1_gen_regs_v2()
527             H264E_HAL_SET_REG(reg, VEPU_REG_DMV_PENALTY_TBL(i / 4), val);  in hal_h264e_vepu1_gen_regs_v2()
533             H264E_HAL_SET_REG(reg, VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i / 4), val);  in hal_h264e_vepu1_gen_regs_v2()
538     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_LUMA, hw_addr->orig[0]);  in hal_h264e_vepu1_gen_regs_v2()
542     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CB, hw_addr->orig[1]);  in hal_h264e_vepu1_gen_regs_v2()
546     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CR, hw_addr->orig[2]);  in hal_h264e_vepu1_gen_regs_v2()
554     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_CTRL, nal_size_table_fd);  in hal_h264e_vepu1_gen_regs_v2()
556     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_LUMA,   hw_addr->recn[0]);  in hal_h264e_vepu1_gen_regs_v2()
557     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_CHROMA, hw_addr->recn[1]);  in hal_h264e_vepu1_gen_regs_v2()
559     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_LUMA,   hw_addr->refr[0]);  in hal_h264e_vepu1_gen_regs_v2()
560     H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_CHROMA, hw_addr->refr[1]);  in hal_h264e_vepu1_gen_regs_v2()
571     H264E_HAL_SET_REG(reg, VEPU_REG_ENCODE_CTRL, val);  in hal_h264e_vepu1_gen_regs_v2()
593             wr_cfg.reg = &ctx->regs_set;  in hal_h264e_vepu1_start_v2()
603             rd_cfg.reg = &ctx->regs_get;  in hal_h264e_vepu1_start_v2()
627 static void h264e_vepu1_get_mbrc(HalH264eVepuMbRc *mb_rc, H264eVpu1RegSet *reg)  in h264e_vepu1_get_mbrc()  argument
633     RK_U32 *reg_val = reg->val;  in h264e_vepu1_get_mbrc()