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Searched refs:p_regs (Results 1 – 17 of 17) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_plus.c41 AvsdPlusRegs_t *p_regs = (AvsdPlusRegs_t *)p_hal->p_regs; in set_defalut_parameters() local
43 p_regs->sw02.dec_out_endian = 1; in set_defalut_parameters()
44 p_regs->sw02.dec_in_endian = 0; in set_defalut_parameters()
45 p_regs->sw02.dec_strendian_e = 1; in set_defalut_parameters()
46 p_regs->sw02.dec_max_burst = 16; in set_defalut_parameters()
47 p_regs->sw02.dec_scmd_dis = 0; in set_defalut_parameters()
49 p_regs->sw02.dec_adv_pre_dis = 0; in set_defalut_parameters()
50 p_regs->sw55.apf_threshold = 8; in set_defalut_parameters()
52 p_regs->sw02.dec_latency = 0; in set_defalut_parameters()
53 p_regs->sw02.dec_data_disc_e = 0; in set_defalut_parameters()
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H A Dhal_avsd_vdpu1.c33 AvsdVdpu1Regs_t *p_regs = (AvsdVdpu1Regs_t *)p_hal->p_regs; in set_defalut_parameters() local
35 p_regs->sw02.dec_out_endian = 1; in set_defalut_parameters()
36 p_regs->sw02.dec_in_endian = 0; in set_defalut_parameters()
37 p_regs->sw02.dec_strendian_e = 1; in set_defalut_parameters()
38 p_regs->sw02.dec_max_burst = 16; in set_defalut_parameters()
39 p_regs->sw02.dec_scmd_dis = 0; in set_defalut_parameters()
41 p_regs->sw02.dec_adv_pre_dis = 0; in set_defalut_parameters()
42 p_regs->sw55.apf_threshold = 8; in set_defalut_parameters()
43 p_regs->sw02.dec_latency = 0; in set_defalut_parameters()
45 p_regs->sw02.dec_data_disc_e = 0; in set_defalut_parameters()
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H A Dhal_avsd_vdpu2.c33 AvsdVdpu2Regs_t *p_regs = (AvsdVdpu2Regs_t *)p_hal->p_regs; in set_defalut_parameters() local
35 p_regs->sw54.dec_out_endian = 1; in set_defalut_parameters()
36 p_regs->sw54.dec_in_endian = 0; in set_defalut_parameters()
37 p_regs->sw54.dec_strendian_e = 1; in set_defalut_parameters()
38 p_regs->sw56.dec_max_burlen = 16; in set_defalut_parameters()
39 p_regs->sw50.dec_ascmd0_dis = 0; in set_defalut_parameters()
41 p_regs->sw50.adv_pref_dis = 0; in set_defalut_parameters()
42 p_regs->sw52.adv_pref_thrd = 8; in set_defalut_parameters()
43 p_regs->sw50.adtion_latency = 0; in set_defalut_parameters()
45 p_regs->sw56.dec_data_discd_en = 0; in set_defalut_parameters()
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H A Dhal_avsd_base.h113 RK_U32 *p_regs; member
/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu1.c116 M2vdVdpu1Reg_t *p_regs = (M2vdVdpu1Reg_t *)ctx->regs; in hal_m2vd_vdpu1_init_hwcfg() local
118 memset(p_regs, 0, sizeof(M2vdVdpu1Reg_t)); in hal_m2vd_vdpu1_init_hwcfg()
119 p_regs->sw02.dec_axi_rn_id = 0; in hal_m2vd_vdpu1_init_hwcfg()
120 p_regs->sw02.dec_timeout_e = 1; in hal_m2vd_vdpu1_init_hwcfg()
121 p_regs->sw02.dec_strswap32_e = 1; in hal_m2vd_vdpu1_init_hwcfg()
122 p_regs->sw02.dec_strendian_e = 1; in hal_m2vd_vdpu1_init_hwcfg()
123 p_regs->sw02.dec_inswap32_e = 1; in hal_m2vd_vdpu1_init_hwcfg()
124 p_regs->sw02.dec_outswap32_e = 1; in hal_m2vd_vdpu1_init_hwcfg()
126 p_regs->sw02.dec_clk_gate_e = 1; in hal_m2vd_vdpu1_init_hwcfg()
127 p_regs->sw02.dec_in_endian = 1; in hal_m2vd_vdpu1_init_hwcfg()
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H A Dhal_m2vd_vdpu2.c156 M2vdVdpu2Reg *p_regs = (M2vdVdpu2Reg *)ctx->regs; in hal_m2vd_vdpu2_init_hwcfg() local
158 memset(p_regs, 0, sizeof(M2vdVdpu2Reg)); in hal_m2vd_vdpu2_init_hwcfg()
160 p_regs->sw56.dec_axi_rn_id = 0; in hal_m2vd_vdpu2_init_hwcfg()
161 p_regs->sw57.dec_timeout_e = 1; in hal_m2vd_vdpu2_init_hwcfg()
162 p_regs->sw54.dec_strswap32_e = 1; //change in hal_m2vd_vdpu2_init_hwcfg()
163 p_regs->sw54.dec_strendian_e = DEC_LITTLE_ENDIAN; in hal_m2vd_vdpu2_init_hwcfg()
164 p_regs->sw54.dec_inswap32_e = 1; //change in hal_m2vd_vdpu2_init_hwcfg()
165 p_regs->sw54.dec_outswap32_e = 1; //change in hal_m2vd_vdpu2_init_hwcfg()
168 p_regs->sw57.dec_clk_gate_e = 1; //change in hal_m2vd_vdpu2_init_hwcfg()
169 p_regs->sw54.dec_in_endian = DEC_LITTLE_ENDIAN; //change in hal_m2vd_vdpu2_init_hwcfg()
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/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu1.c42 static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i, in vdpu1_set_refer_pic_idx() argument
47 p_regs->SwReg30.sw_refer0_nbr = val; in vdpu1_set_refer_pic_idx()
50 p_regs->SwReg30.sw_refer1_nbr = val; in vdpu1_set_refer_pic_idx()
53 p_regs->SwReg31.sw_refer2_nbr = val; in vdpu1_set_refer_pic_idx()
56 p_regs->SwReg31.sw_refer3_nbr = val; in vdpu1_set_refer_pic_idx()
59 p_regs->SwReg32.sw_refer4_nbr = val; in vdpu1_set_refer_pic_idx()
62 p_regs->SwReg32.sw_refer5_nbr = val; in vdpu1_set_refer_pic_idx()
65 p_regs->SwReg33.sw_refer6_nbr = val; in vdpu1_set_refer_pic_idx()
68 p_regs->SwReg33.sw_refer7_nbr = val; in vdpu1_set_refer_pic_idx()
71 p_regs->SwReg34.sw_refer8_nbr = val; in vdpu1_set_refer_pic_idx()
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H A Dhal_h264d_vdpu2.c87 static MPP_RET set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) in set_refer_pic_idx() argument
91 p_regs->sw76.num_ref_idx0 = val; in set_refer_pic_idx()
94 p_regs->sw76.num_ref_idx1 = val; in set_refer_pic_idx()
97 p_regs->sw77.num_ref_idx2 = val; in set_refer_pic_idx()
100 p_regs->sw77.num_ref_idx3 = val; in set_refer_pic_idx()
103 p_regs->sw78.num_ref_idx4 = val; in set_refer_pic_idx()
106 p_regs->sw78.num_ref_idx5 = val; in set_refer_pic_idx()
109 p_regs->sw79.num_ref_idx6 = val; in set_refer_pic_idx()
112 p_regs->sw79.num_ref_idx7 = val; in set_refer_pic_idx()
115 p_regs->sw80.num_ref_idx8 = val; in set_refer_pic_idx()
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H A Dhal_h264d_rkv_reg.c429 static MPP_RET set_registers(H264dHalCtx_t *p_hal, H264dRkvRegs_t *p_regs, HalTaskInfo *task) in set_registers() argument
433 memset(p_regs, 0, sizeof(H264dRkvRegs_t)); in set_registers()
436 p_regs->sw02.dec_mode = 1; //!< h264 in set_registers()
437 if (p_regs->sw02.rlc_mode == 1) { in set_registers()
438 p_regs->sw05.stream_len = 0; in set_registers()
440 p_regs->sw05.stream_len = p_hal->strm_len; in set_registers()
442 if (p_regs->sw02.rps_mode) { // rps_mode == 1 in set_registers()
443 p_regs->sw43.rps_base += 0x8; in set_registers()
445 p_regs->sw03.slice_num_lowbits = 0x7ff; in set_registers()
446 p_regs->sw03.slice_num_highbit = 1; in set_registers()
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H A Dhal_h264d_vdpu384a.c955 Vdpu384aH264dRegSet *p_regs = p_hal->fast_mode ? in vdpu384a_h264d_wait() local
973 param.regs = (RK_U32 *)p_regs; in vdpu384a_h264d_wait()
975 if ((!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) || in vdpu384a_h264d_wait()
976 p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta || in vdpu384a_h264d_wait()
977 p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta || in vdpu384a_h264d_wait()
978 p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta || in vdpu384a_h264d_wait()
979 p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta || in vdpu384a_h264d_wait()
980 p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta || in vdpu384a_h264d_wait()
981 p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) in vdpu384a_h264d_wait()
988 memset(&p_regs->ctrl_regs.reg19, 0, sizeof(RK_U32)); in vdpu384a_h264d_wait()
H A Dhal_h264d_vdpu383.c1009 Vdpu383H264dRegSet *p_regs = p_hal->fast_mode ? in vdpu383_h264d_wait() local
1027 param.regs = (RK_U32 *)p_regs; in vdpu383_h264d_wait()
1029 if ((!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) || in vdpu383_h264d_wait()
1030 p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta || in vdpu383_h264d_wait()
1031 p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta || in vdpu383_h264d_wait()
1032 p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta || in vdpu383_h264d_wait()
1033 p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta || in vdpu383_h264d_wait()
1034 p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta || in vdpu383_h264d_wait()
1035 p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) in vdpu383_h264d_wait()
1042 memset(&p_regs->ctrl_regs.reg19, 0, sizeof(RK_U32)); in vdpu383_h264d_wait()
H A Dhal_h264d_vdpu34x.c1118 Vdpu34xH264dRegSet *p_regs = p_hal->fast_mode ? in vdpu34x_h264d_wait() local
1136 param.regs = (RK_U32 *)p_regs; in vdpu34x_h264d_wait()
1138 if (p_regs->irq_status.reg224.dec_error_sta || in vdpu34x_h264d_wait()
1139 (!p_regs->irq_status.reg224.dec_rdy_sta) || in vdpu34x_h264d_wait()
1140 p_regs->irq_status.reg224.buf_empty_sta || in vdpu34x_h264d_wait()
1141 p_regs->irq_status.reg226.strmd_error_status || in vdpu34x_h264d_wait()
1142 p_regs->irq_status.reg227.colmv_error_ref_picidx || in vdpu34x_h264d_wait()
1143 p_regs->irq_status.reg225.strmd_detect_error_flag) in vdpu34x_h264d_wait()
1150 memset(&p_regs->irq_status.reg224, 0, sizeof(RK_U32)); in vdpu34x_h264d_wait()
H A Dhal_h264d_vdpu382.c1176 Vdpu382H264dRegSet *p_regs = p_hal->fast_mode ? in vdpu382_h264_get_ref_used() local
1182 memcpy(&hw_ref_used, &p_regs->statistic.reg265, sizeof(RK_U32)); in vdpu382_h264_get_ref_used()
1233 Vdpu382H264dRegSet *p_regs = p_hal->fast_mode ? in vdpu382_h264d_wait() local
1246 hw_err = p_regs->irq_status.reg224.dec_error_sta || in vdpu382_h264d_wait()
1247 (!p_regs->irq_status.reg224.dec_rdy_sta) || in vdpu382_h264d_wait()
1248 p_regs->irq_status.reg224.buf_empty_sta || in vdpu382_h264d_wait()
1249 p_regs->irq_status.reg226.strmd_error_status || in vdpu382_h264d_wait()
1250 p_regs->irq_status.reg227.colmv_error_ref_picidx || in vdpu382_h264d_wait()
1251 p_regs->irq_status.reg226.strmd_detect_error_flag; in vdpu382_h264d_wait()
1263 param.regs = (RK_U32 *)p_regs; in vdpu382_h264d_wait()
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_vdpu382.c384 static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu382Avs2dRegSet *p_regs, HalTaskInfo *task) in fill_registers() argument
393 Vdpu382RegCommon *common = &p_regs->common; in fill_registers()
431 p_regs->avs2d_param.reg65_cur_top_poc = mpp_frame_get_poc(mframe); in fill_registers()
432 p_regs->avs2d_param.reg66_cur_bot_poc = 0; in fill_registers()
435 p_regs->common_addr.reg130_decout_base = fd; in fill_registers()
437 p_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); in fill_registers()
438 …AVS2D_HAL_TRACE("cur frame index %d, fd %d, colmv fd %d", task_dec->output, fd, p_regs->common_add… in fill_registers()
445 RK_U32 *ref_low = (RK_U32 *)&p_regs->avs2d_param.reg99; in fill_registers()
446 RK_U32 *ref_hight = (RK_U32 *)&p_regs->avs2d_param.reg100; in fill_registers()
483 p_regs->avs2d_addr.ref_base[i] = get_frame_fd(p_hal, slot_idx); in fill_registers()
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H A Dhal_avs2d_rkv.c328 static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu34xAvs2dRegSet *p_regs, HalTaskInfo *task) in fill_registers() argument
337 Vdpu34xRegCommon *common = &p_regs->common; in fill_registers()
375 p_regs->avs2d_param.reg65_cur_top_poc = mpp_frame_get_poc(mframe); in fill_registers()
376 p_regs->avs2d_param.reg66_cur_bot_poc = 0; in fill_registers()
379 p_regs->common_addr.reg130_decout_base = fd; in fill_registers()
381 p_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); in fill_registers()
382 …AVS2D_HAL_TRACE("cur frame index %d, fd %d, colmv fd %d", task_dec->output, fd, p_regs->common_add… in fill_registers()
389 RK_U32 *ref_low = (RK_U32 *)&p_regs->avs2d_param.reg99; in fill_registers()
390 RK_U32 *ref_hight = (RK_U32 *)&p_regs->avs2d_param.reg100; in fill_registers()
427 p_regs->avs2d_addr.ref_base[i] = get_frame_fd(p_hal, slot_idx); in fill_registers()
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/rockchip-linux_mpp/mpp/hal/rkdec/av1d/
H A Dhal_av1d_vdpu383.c2566 Vdpu383Av1dRegSet *p_regs = p_hal->fast_mode ? in vdpu383_av1d_wait() local
2621 (!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) || in vdpu383_av1d_wait()
2622 p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta || in vdpu383_av1d_wait()
2623 p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta || in vdpu383_av1d_wait()
2624 p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta || in vdpu383_av1d_wait()
2625 p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta || in vdpu383_av1d_wait()
2626 p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta || in vdpu383_av1d_wait()
2627 p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) { in vdpu383_av1d_wait()
/rockchip-linux_mpp/mpp/hal/vpu/av1d/
H A Dhal_av1d_vdpu.c2310 VdpuAv1dRegSet *p_regs = p_hal->fast_mode ? in vdpu_av1d_wait() local
2327 RK_U32 *p = (RK_U32*)p_regs; in vdpu_av1d_wait()
2332 for (i = 0; i < sizeof(*p_regs) / 4; i++, p++) in vdpu_av1d_wait()
2348 if (!p_regs->swreg1.sw_dec_rdy_int/* decode err */) in vdpu_av1d_wait()