Lines Matching refs:p_regs
42 static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i, in vdpu1_set_refer_pic_idx() argument
47 p_regs->SwReg30.sw_refer0_nbr = val; in vdpu1_set_refer_pic_idx()
50 p_regs->SwReg30.sw_refer1_nbr = val; in vdpu1_set_refer_pic_idx()
53 p_regs->SwReg31.sw_refer2_nbr = val; in vdpu1_set_refer_pic_idx()
56 p_regs->SwReg31.sw_refer3_nbr = val; in vdpu1_set_refer_pic_idx()
59 p_regs->SwReg32.sw_refer4_nbr = val; in vdpu1_set_refer_pic_idx()
62 p_regs->SwReg32.sw_refer5_nbr = val; in vdpu1_set_refer_pic_idx()
65 p_regs->SwReg33.sw_refer6_nbr = val; in vdpu1_set_refer_pic_idx()
68 p_regs->SwReg33.sw_refer7_nbr = val; in vdpu1_set_refer_pic_idx()
71 p_regs->SwReg34.sw_refer8_nbr = val; in vdpu1_set_refer_pic_idx()
74 p_regs->SwReg34.sw_refer9_nbr = val; in vdpu1_set_refer_pic_idx()
77 p_regs->SwReg35.sw_refer10_nbr = val; in vdpu1_set_refer_pic_idx()
80 p_regs->SwReg35.sw_refer11_nbr = val; in vdpu1_set_refer_pic_idx()
83 p_regs->SwReg36.sw_refer12_nbr = val; in vdpu1_set_refer_pic_idx()
86 p_regs->SwReg36.sw_refer13_nbr = val; in vdpu1_set_refer_pic_idx()
89 p_regs->SwReg37.sw_refer14_nbr = val; in vdpu1_set_refer_pic_idx()
92 p_regs->SwReg37.sw_refer15_nbr = val; in vdpu1_set_refer_pic_idx()
101 static MPP_RET vdpu1_set_refer_pic_list_p(H264dVdpu1Regs_t *p_regs, RK_U32 i, in vdpu1_set_refer_pic_list_p() argument
106 p_regs->SwReg47.sw_pinit_rlist_f0 = val; in vdpu1_set_refer_pic_list_p()
109 p_regs->SwReg47.sw_pinit_rlist_f1 = val; in vdpu1_set_refer_pic_list_p()
112 p_regs->SwReg47.sw_pinit_rlist_f2 = val; in vdpu1_set_refer_pic_list_p()
115 p_regs->SwReg47.sw_pinit_rlist_f3 = val; in vdpu1_set_refer_pic_list_p()
118 p_regs->SwReg10.sw_pinit_rlist_f4 = val; in vdpu1_set_refer_pic_list_p()
121 p_regs->SwReg10.sw_pinit_rlist_f5 = val; in vdpu1_set_refer_pic_list_p()
124 p_regs->SwReg10.sw_pinit_rlist_f6 = val; in vdpu1_set_refer_pic_list_p()
127 p_regs->SwReg10.sw_pinit_rlist_f7 = val; in vdpu1_set_refer_pic_list_p()
130 p_regs->SwReg10.sw_pinit_rlist_f8 = val; in vdpu1_set_refer_pic_list_p()
133 p_regs->SwReg10.sw_pinit_rlist_f9 = val; in vdpu1_set_refer_pic_list_p()
136 p_regs->SwReg11.sw_pinit_rlist_f10 = val; in vdpu1_set_refer_pic_list_p()
139 p_regs->SwReg11.sw_pinit_rlist_f11 = val; in vdpu1_set_refer_pic_list_p()
142 p_regs->SwReg11.sw_pinit_rlist_f12 = val; in vdpu1_set_refer_pic_list_p()
145 p_regs->SwReg11.sw_pinit_rlist_f13 = val; in vdpu1_set_refer_pic_list_p()
148 p_regs->SwReg11.sw_pinit_rlist_f14 = val; in vdpu1_set_refer_pic_list_p()
151 p_regs->SwReg11.sw_pinit_rlist_f15 = val; in vdpu1_set_refer_pic_list_p()
160 static MPP_RET vdpu1_set_refer_pic_list_b0(H264dVdpu1Regs_t *p_regs, RK_U32 i, in vdpu1_set_refer_pic_list_b0() argument
165 p_regs->SwReg42.sw_binit_rlist_f0 = val; in vdpu1_set_refer_pic_list_b0()
168 p_regs->SwReg42.sw_binit_rlist_f1 = val; in vdpu1_set_refer_pic_list_b0()
171 p_regs->SwReg42.sw_binit_rlist_f2 = val; in vdpu1_set_refer_pic_list_b0()
174 p_regs->SwReg43.sw_binit_rlist_f3 = val; in vdpu1_set_refer_pic_list_b0()
177 p_regs->SwReg43.sw_binit_rlist_f4 = val; in vdpu1_set_refer_pic_list_b0()
180 p_regs->SwReg43.sw_binit_rlist_f5 = val; in vdpu1_set_refer_pic_list_b0()
183 p_regs->SwReg44.sw_binit_rlist_f6 = val; in vdpu1_set_refer_pic_list_b0()
186 p_regs->SwReg44.sw_binit_rlist_f7 = val; in vdpu1_set_refer_pic_list_b0()
189 p_regs->SwReg44.sw_binit_rlist_f8 = val; in vdpu1_set_refer_pic_list_b0()
192 p_regs->SwReg45.sw_binit_rlist_f9 = val; in vdpu1_set_refer_pic_list_b0()
195 p_regs->SwReg45.sw_binit_rlist_f10 = val; in vdpu1_set_refer_pic_list_b0()
198 p_regs->SwReg45.sw_binit_rlist_f11 = val; in vdpu1_set_refer_pic_list_b0()
201 p_regs->SwReg46.sw_binit_rlist_f12 = val; in vdpu1_set_refer_pic_list_b0()
204 p_regs->SwReg46.sw_binit_rlist_f13 = val; in vdpu1_set_refer_pic_list_b0()
207 p_regs->SwReg46.sw_binit_rlist_f14 = val; in vdpu1_set_refer_pic_list_b0()
210 p_regs->SwReg47.sw_binit_rlist_f15 = val; in vdpu1_set_refer_pic_list_b0()
219 static MPP_RET vdpu1_set_refer_pic_list_b1(H264dVdpu1Regs_t *p_regs, RK_U32 i, in vdpu1_set_refer_pic_list_b1() argument
224 p_regs->SwReg42.sw_binit_rlist_b0 = val; in vdpu1_set_refer_pic_list_b1()
227 p_regs->SwReg42.sw_binit_rlist_b1 = val; in vdpu1_set_refer_pic_list_b1()
230 p_regs->SwReg42.sw_binit_rlist_b2 = val; in vdpu1_set_refer_pic_list_b1()
233 p_regs->SwReg43.sw_binit_rlist_b3 = val; in vdpu1_set_refer_pic_list_b1()
236 p_regs->SwReg43.sw_binit_rlist_b4 = val; in vdpu1_set_refer_pic_list_b1()
239 p_regs->SwReg43.sw_binit_rlist_b5 = val; in vdpu1_set_refer_pic_list_b1()
242 p_regs->SwReg44.sw_binit_rlist_b6 = val; in vdpu1_set_refer_pic_list_b1()
245 p_regs->SwReg44.sw_binit_rlist_b7 = val; in vdpu1_set_refer_pic_list_b1()
248 p_regs->SwReg44.sw_binit_rlist_b8 = val; in vdpu1_set_refer_pic_list_b1()
251 p_regs->SwReg45.sw_binit_rlist_b9 = val; in vdpu1_set_refer_pic_list_b1()
254 p_regs->SwReg45.sw_binit_rlist_b10 = val; in vdpu1_set_refer_pic_list_b1()
257 p_regs->SwReg45.sw_binit_rlist_b11 = val; in vdpu1_set_refer_pic_list_b1()
260 p_regs->SwReg46.sw_binit_rlist_b12 = val; in vdpu1_set_refer_pic_list_b1()
263 p_regs->SwReg46.sw_binit_rlist_b13 = val; in vdpu1_set_refer_pic_list_b1()
266 p_regs->SwReg46.sw_binit_rlist_b14 = val; in vdpu1_set_refer_pic_list_b1()
269 p_regs->SwReg47.sw_binit_rlist_b15 = val; in vdpu1_set_refer_pic_list_b1()
278 static MPP_RET vdpu1_set_refer_pic_base_addr(H264dVdpu1Regs_t *p_regs, RK_U32 i, in vdpu1_set_refer_pic_base_addr() argument
283 p_regs->SwReg14.sw_refer0_base = val; in vdpu1_set_refer_pic_base_addr()
286 p_regs->SwReg15.sw_refer1_base = val; in vdpu1_set_refer_pic_base_addr()
289 p_regs->SwReg16.sw_refer2_base = val; in vdpu1_set_refer_pic_base_addr()
292 p_regs->SwReg17.sw_refer3_base = val; in vdpu1_set_refer_pic_base_addr()
295 p_regs->SwReg18.sw_refer4_base = val; in vdpu1_set_refer_pic_base_addr()
298 p_regs->SwReg19.sw_refer5_base = val; in vdpu1_set_refer_pic_base_addr()
301 p_regs->SwReg20.sw_refer6_base = val; in vdpu1_set_refer_pic_base_addr()
304 p_regs->SwReg21.sw_refer7_base = val; in vdpu1_set_refer_pic_base_addr()
307 p_regs->SwReg22.sw_refer8_base = val; in vdpu1_set_refer_pic_base_addr()
310 p_regs->SwReg23.sw_refer9_base = val; in vdpu1_set_refer_pic_base_addr()
313 p_regs->SwReg24.sw_refer10_base = val; in vdpu1_set_refer_pic_base_addr()
316 p_regs->SwReg25.sw_refer11_base = val; in vdpu1_set_refer_pic_base_addr()
319 p_regs->SwReg26.sw_refer12_base = val; in vdpu1_set_refer_pic_base_addr()
322 p_regs->SwReg27.sw_refer13_base = val; in vdpu1_set_refer_pic_base_addr()
325 p_regs->SwReg28.sw_refer14_base = val; in vdpu1_set_refer_pic_base_addr()
328 p_regs->SwReg29.sw_refer15_base = val; in vdpu1_set_refer_pic_base_addr()
337 H264dVdpu1Regs_t *p_regs) in vdpu1_set_pic_regs() argument
341 p_regs->SwReg04.sw_pic_mb_width = p_hal->pp->wFrameWidthInMbsMinus1 + 1; in vdpu1_set_pic_regs()
342 p_regs->SwReg04.sw_pic_mb_height_p = (2 - p_hal->pp->frame_mbs_only_flag) in vdpu1_set_pic_regs()
349 H264dVdpu1Regs_t *p_regs) in vdpu1_set_vlc_regs() argument
355 p_regs->SwReg03.sw_dec_out_dis = 0; in vdpu1_set_vlc_regs()
356 p_regs->SwReg03.sw_rlc_mode_e = 0; in vdpu1_set_vlc_regs()
357 p_regs->SwReg06.sw_init_qp = pp->pic_init_qp_minus26 + 26; in vdpu1_set_vlc_regs()
358 p_regs->SwReg09.sw_refidx0_active = pp->num_ref_idx_l0_active_minus1 + 1; in vdpu1_set_vlc_regs()
359 p_regs->SwReg04.sw_ref_frames = pp->num_ref_frames; in vdpu1_set_vlc_regs()
361 p_regs->SwReg07.sw_framenum_len = pp->log2_max_frame_num_minus4 + 4; in vdpu1_set_vlc_regs()
362 p_regs->SwReg07.sw_framenum = pp->frame_num; in vdpu1_set_vlc_regs()
364 p_regs->SwReg08.sw_const_intra_e = pp->constrained_intra_pred_flag; in vdpu1_set_vlc_regs()
365 p_regs->SwReg08.sw_filt_ctrl_pres = in vdpu1_set_vlc_regs()
367 p_regs->SwReg08.sw_rdpic_cnt_pres = pp->redundant_pic_cnt_present_flag; in vdpu1_set_vlc_regs()
368 p_regs->SwReg08.sw_refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen; in vdpu1_set_vlc_regs()
369 p_regs->SwReg08.sw_idr_pic_e = p_hal->slice_long[0].idr_flag; in vdpu1_set_vlc_regs()
370 p_regs->SwReg08.sw_idr_pic_id = p_hal->slice_long[0].idr_pic_id; in vdpu1_set_vlc_regs()
372 p_regs->SwReg09.sw_pps_id = p_hal->slice_long[0].active_pps_id; in vdpu1_set_vlc_regs()
373 p_regs->SwReg09.sw_poc_length = p_hal->slice_long[0].poc_used_bitlen; in vdpu1_set_vlc_regs()
391 p_regs->SwReg38.refpic_term_flag = longTermflags; in vdpu1_set_vlc_regs()
392 p_regs->SwReg39.refpic_valid_flag = validFlags; in vdpu1_set_vlc_regs()
407 p_regs->SwReg38.refpic_term_flag = (longTermflags << 16); in vdpu1_set_vlc_regs()
408 p_regs->SwReg39.refpic_valid_flag = (validFlags << 16); in vdpu1_set_vlc_regs()
414 vdpu1_set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num in vdpu1_set_vlc_regs()
416 vdpu1_set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num in vdpu1_set_vlc_regs()
420 p_regs->SwReg03.sw_picord_count_e = 1; in vdpu1_set_vlc_regs()
447 p_regs->SwReg07.sw_cabac_e = pp->entropy_coding_mode_flag; in vdpu1_set_vlc_regs()
452 p_regs->SwReg06.sw_start_code_e = 1; in vdpu1_set_vlc_regs()
457 p_regs->SwReg05.sw_strm_start_bit = 0; /* sodb stream start bit */ in vdpu1_set_vlc_regs()
458 p_regs->SwReg12.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf); in vdpu1_set_vlc_regs()
460 p_regs->SwReg06.sw_stream_len = p_hal->strm_len; in vdpu1_set_vlc_regs()
467 H264dVdpu1Regs_t *p_regs) in vdpu1_set_ref_regs() argument
530 vdpu1_set_refer_pic_list_p(p_regs, i, m_lists[0][i].idx); in vdpu1_set_ref_regs()
531 vdpu1_set_refer_pic_list_b0(p_regs, i, m_lists[1][i].idx); in vdpu1_set_ref_regs()
532 vdpu1_set_refer_pic_list_b1(p_regs, i, m_lists[2][i].idx); in vdpu1_set_ref_regs()
539 H264dVdpu1Regs_t *p_regs) in vdpu1_set_asic_regs() argument
582 vdpu1_set_refer_pic_base_addr(p_regs, i, mpp_buffer_get_fd(frame_buf)); in vdpu1_set_asic_regs()
592 … p_regs->SwReg29.sw_refer15_base = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15 in vdpu1_set_asic_regs()
593 p_regs->SwReg39.refpic_valid_flag |= in vdpu1_set_asic_regs()
598 p_regs->SwReg03.sw_pic_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E in vdpu1_set_asic_regs()
599 p_regs->SwReg03.sw_filtering_dis = 0; in vdpu1_set_asic_regs()
608 p_regs->SwReg13.dec_out_st_adr = outPhyAddr; //!< outPhyAddr, pp->CurrPic.Index7Bits in vdpu1_set_asic_regs()
610 p_regs->SwReg05.sw_ch_qp_offset = pp->chroma_qp_index_offset; in vdpu1_set_asic_regs()
611 p_regs->SwReg05.sw_ch_qp_offset2 = pp->second_chroma_qp_index_offset; in vdpu1_set_asic_regs()
629 p_regs->SwReg41.dmmv_st_adr = mpp_buffer_get_fd(frame_buf); in vdpu1_set_asic_regs()
632 p_regs->SwReg03.sw_write_mvs_e = (p_long->nal_ref_idc != 0) ? 1 : 0; /* defalut set 1 */ in vdpu1_set_asic_regs()
633 p_regs->SwReg07.sw_dir_8x8_infer_e = pp->direct_8x8_inference_flag; in vdpu1_set_asic_regs()
634 p_regs->SwReg07.sw_weight_pred_e = pp->weighted_pred_flag; in vdpu1_set_asic_regs()
635 p_regs->SwReg07.sw_weight_bipr_idc = pp->weighted_bipred_idc; in vdpu1_set_asic_regs()
636 p_regs->SwReg09.sw_refidx1_active = (pp->num_ref_idx_l1_active_minus1 + 1); in vdpu1_set_asic_regs()
637 p_regs->SwReg05.sw_fieldpic_flag_e = (!pp->frame_mbs_only_flag) ? 1 : 0; in vdpu1_set_asic_regs()
639 p_regs->SwReg03.sw_pic_interlace_e = in vdpu1_set_asic_regs()
642 p_regs->SwReg03.sw_pic_fieldmode_e = pp->field_pic_flag; in vdpu1_set_asic_regs()
643 p_regs->SwReg03.sw_pic_topfield_e = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; /* bottomFieldFlag */ in vdpu1_set_asic_regs()
644 p_regs->SwReg03.sw_seq_mbaff_e = pp->MbaffFrameFlag; in vdpu1_set_asic_regs()
645 p_regs->SwReg08.sw_8x8trans_flag_e = pp->transform_8x8_mode_flag; in vdpu1_set_asic_regs()
646 p_regs->SwReg07.sw_blackwhite_e = (p_long->profileIdc >= 100 in vdpu1_set_asic_regs()
648 p_regs->SwReg05.sw_type1_quant_e = pp->scaleing_list_enable_flag; in vdpu1_set_asic_regs()
676 p_regs->SwReg40.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf); in vdpu1_set_asic_regs()
679 p_regs->SwReg03.sw_dec_out_dis = 0; /* set defalut 0 */ in vdpu1_set_asic_regs()
680 p_regs->SwReg06.sw_ch_8pix_ileav_e = 0; in vdpu1_set_asic_regs()
681 p_regs->SwReg01.sw_dec_en = 1; in vdpu1_set_asic_regs()
878 H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ? in vdpu1_h264d_start() local
887 p_regs->SwReg57.sw_cache_en = 1; in vdpu1_h264d_start()
888 p_regs->SwReg57.sw_pref_sigchan = 1; in vdpu1_h264d_start()
889 p_regs->SwReg57.sw_intra_dbl3t = 1; in vdpu1_h264d_start()
890 p_regs->SwReg57.sw_inter_dblspeed = 1; in vdpu1_h264d_start()
891 p_regs->SwReg57.sw_intra_dblspeed = 1; in vdpu1_h264d_start()
892 p_regs->SwReg57.sw_paral_bus = 1; in vdpu1_h264d_start()
943 H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ? in vdpu1_h264d_wait() local
962 param.hard_err = !p_regs->SwReg01.sw_dec_rdy_int; in vdpu1_h264d_wait()
966 memset(&p_regs->SwReg01, 0, sizeof(RK_U32)); in vdpu1_h264d_wait()