Lines Matching refs:p_regs
87 static MPP_RET set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) in set_refer_pic_idx() argument
91 p_regs->sw76.num_ref_idx0 = val; in set_refer_pic_idx()
94 p_regs->sw76.num_ref_idx1 = val; in set_refer_pic_idx()
97 p_regs->sw77.num_ref_idx2 = val; in set_refer_pic_idx()
100 p_regs->sw77.num_ref_idx3 = val; in set_refer_pic_idx()
103 p_regs->sw78.num_ref_idx4 = val; in set_refer_pic_idx()
106 p_regs->sw78.num_ref_idx5 = val; in set_refer_pic_idx()
109 p_regs->sw79.num_ref_idx6 = val; in set_refer_pic_idx()
112 p_regs->sw79.num_ref_idx7 = val; in set_refer_pic_idx()
115 p_regs->sw80.num_ref_idx8 = val; in set_refer_pic_idx()
118 p_regs->sw80.num_ref_idx9 = val; in set_refer_pic_idx()
121 p_regs->sw81.num_ref_idx10 = val; in set_refer_pic_idx()
124 p_regs->sw81.num_ref_idx11 = val; in set_refer_pic_idx()
127 p_regs->sw82.num_ref_idx12 = val; in set_refer_pic_idx()
130 p_regs->sw82.num_ref_idx13 = val; in set_refer_pic_idx()
133 p_regs->sw83.num_ref_idx14 = val; in set_refer_pic_idx()
136 p_regs->sw83.num_ref_idx15 = val; in set_refer_pic_idx()
145 static MPP_RET set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, in set_refer_pic_list_p() argument
150 p_regs->sw106.init_reflist_pf0 = val; in set_refer_pic_list_p()
153 p_regs->sw106.init_reflist_pf1 = val; in set_refer_pic_list_p()
156 p_regs->sw106.init_reflist_pf2 = val; in set_refer_pic_list_p()
159 p_regs->sw106.init_reflist_pf3 = val; in set_refer_pic_list_p()
162 p_regs->sw74.init_reflist_pf4 = val; in set_refer_pic_list_p()
165 p_regs->sw74.init_reflist_pf5 = val; in set_refer_pic_list_p()
168 p_regs->sw74.init_reflist_pf6 = val; in set_refer_pic_list_p()
171 p_regs->sw74.init_reflist_pf7 = val; in set_refer_pic_list_p()
174 p_regs->sw74.init_reflist_pf8 = val; in set_refer_pic_list_p()
177 p_regs->sw74.init_reflist_pf9 = val; in set_refer_pic_list_p()
180 p_regs->sw75.init_reflist_pf10 = val; in set_refer_pic_list_p()
183 p_regs->sw75.init_reflist_pf11 = val; in set_refer_pic_list_p()
186 p_regs->sw75.init_reflist_pf12 = val; in set_refer_pic_list_p()
189 p_regs->sw75.init_reflist_pf13 = val; in set_refer_pic_list_p()
192 p_regs->sw75.init_reflist_pf14 = val; in set_refer_pic_list_p()
195 p_regs->sw75.init_reflist_pf15 = val; in set_refer_pic_list_p()
204 static MPP_RET set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, in set_refer_pic_list_b0() argument
209 p_regs->sw100.init_reflist_df0 = val; in set_refer_pic_list_b0()
212 p_regs->sw100.init_reflist_df1 = val; in set_refer_pic_list_b0()
215 p_regs->sw100.init_reflist_df2 = val; in set_refer_pic_list_b0()
218 p_regs->sw100.init_reflist_df3 = val; in set_refer_pic_list_b0()
221 p_regs->sw100.init_reflist_df4 = val; in set_refer_pic_list_b0()
224 p_regs->sw100.init_reflist_df5 = val; in set_refer_pic_list_b0()
227 p_regs->sw101.init_reflist_df6 = val; in set_refer_pic_list_b0()
230 p_regs->sw101.init_reflist_df7 = val; in set_refer_pic_list_b0()
233 p_regs->sw101.init_reflist_df8 = val; in set_refer_pic_list_b0()
236 p_regs->sw101.init_reflist_df9 = val; in set_refer_pic_list_b0()
239 p_regs->sw101.init_reflist_df10 = val; in set_refer_pic_list_b0()
242 p_regs->sw101.init_reflist_df11 = val; in set_refer_pic_list_b0()
245 p_regs->sw102.init_reflist_df12 = val; in set_refer_pic_list_b0()
248 p_regs->sw102.init_reflist_df13 = val; in set_refer_pic_list_b0()
251 p_regs->sw102.init_reflist_df14 = val; in set_refer_pic_list_b0()
254 p_regs->sw102.init_reflist_df15 = val; in set_refer_pic_list_b0()
263 static MPP_RET set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, in set_refer_pic_list_b1() argument
268 p_regs->sw103.init_reflist_db0 = val; in set_refer_pic_list_b1()
271 p_regs->sw103.init_reflist_db1 = val; in set_refer_pic_list_b1()
274 p_regs->sw103.init_reflist_db2 = val; in set_refer_pic_list_b1()
277 p_regs->sw103.init_reflist_db3 = val; in set_refer_pic_list_b1()
280 p_regs->sw103.init_reflist_db4 = val; in set_refer_pic_list_b1()
283 p_regs->sw103.init_reflist_db5 = val; in set_refer_pic_list_b1()
286 p_regs->sw104.init_reflist_db6 = val; in set_refer_pic_list_b1()
289 p_regs->sw104.init_reflist_db7 = val; in set_refer_pic_list_b1()
292 p_regs->sw104.init_reflist_db8 = val; in set_refer_pic_list_b1()
295 p_regs->sw104.init_reflist_db9 = val; in set_refer_pic_list_b1()
298 p_regs->sw104.init_reflist_db10 = val; in set_refer_pic_list_b1()
301 p_regs->sw104.init_reflist_db11 = val; in set_refer_pic_list_b1()
304 p_regs->sw105.init_reflist_db12 = val; in set_refer_pic_list_b1()
307 p_regs->sw105.init_reflist_db13 = val; in set_refer_pic_list_b1()
310 p_regs->sw105.init_reflist_db14 = val; in set_refer_pic_list_b1()
313 p_regs->sw105.init_reflist_db15 = val; in set_refer_pic_list_b1()
322 static MPP_RET set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i, in set_refer_pic_base_addr() argument
327 p_regs->sw84.ref0_st_addr = val; in set_refer_pic_base_addr()
330 p_regs->sw85.ref1_st_addr = val; in set_refer_pic_base_addr()
333 p_regs->sw86.ref2_st_addr = val; in set_refer_pic_base_addr()
336 p_regs->sw87.ref3_st_addr = val; in set_refer_pic_base_addr()
339 p_regs->sw88.ref4_st_addr = val; in set_refer_pic_base_addr()
342 p_regs->sw89.ref5_st_addr = val; in set_refer_pic_base_addr()
345 p_regs->sw90.ref6_st_addr = val; in set_refer_pic_base_addr()
348 p_regs->sw91.ref7_st_addr = val; in set_refer_pic_base_addr()
351 p_regs->sw92.ref8_st_addr = val; in set_refer_pic_base_addr()
354 p_regs->sw93.ref9_st_addr = val; in set_refer_pic_base_addr()
357 p_regs->sw94.ref10_st_addr = val; in set_refer_pic_base_addr()
360 p_regs->sw95.ref11_st_addr = val; in set_refer_pic_base_addr()
363 p_regs->sw96.ref12_st_addr = val; in set_refer_pic_base_addr()
366 p_regs->sw97.ref13_st_addr = val; in set_refer_pic_base_addr()
369 p_regs->sw98.ref14_st_addr = val; in set_refer_pic_base_addr()
372 p_regs->sw99.ref15_st_addr = val; in set_refer_pic_base_addr()
380 static MPP_RET set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_pic_regs() argument
384 p_regs->sw110.pic_mb_w = p_hal->pp->wFrameWidthInMbsMinus1 + 1; in set_pic_regs()
385 p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag) in set_pic_regs()
391 static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_vlc_regs() argument
399 p_regs->sw57.dec_wr_extmen_dis = 0; in set_vlc_regs()
400 p_regs->sw57.rlc_mode_en = 0; in set_vlc_regs()
401 p_regs->sw51.qp_init_val = pp->pic_init_qp_minus26 + 26; in set_vlc_regs()
402 p_regs->sw114.max_refidx0 = pp->num_ref_idx_l0_active_minus1 + 1; in set_vlc_regs()
403 p_regs->sw111.max_refnum = pp->num_ref_frames; in set_vlc_regs()
404 p_regs->sw112.cur_frm_len = pp->log2_max_frame_num_minus4 + 4; in set_vlc_regs()
405 p_regs->sw112.curfrm_num = pp->frame_num; in set_vlc_regs()
406 p_regs->sw115.const_intra_en = pp->constrained_intra_pred_flag; in set_vlc_regs()
407 p_regs->sw112.dblk_ctrl_flag = pp->deblocking_filter_control_present_flag; in set_vlc_regs()
408 p_regs->sw112.rpcp_flag = pp->redundant_pic_cnt_present_flag; in set_vlc_regs()
409 p_regs->sw113.refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen; in set_vlc_regs()
410 p_regs->sw115.idr_pic_flag = p_hal->slice_long[0].idr_flag; in set_vlc_regs()
411 p_regs->sw113.idr_pic_id = p_hal->slice_long[0].idr_pic_id; in set_vlc_regs()
412 p_regs->sw114.pps_id = p_hal->slice_long[0].active_pps_id; in set_vlc_regs()
413 p_regs->sw114.poc_field_len = p_hal->slice_long[0].poc_used_bitlen; in set_vlc_regs()
428 p_regs->sw107.refpic_term_flag = longTermflags; in set_vlc_regs()
429 p_regs->sw108.refpic_valid_flag = validFlags; in set_vlc_regs()
443 p_regs->sw107.refpic_term_flag = (longTermflags << 16); in set_vlc_regs()
444 p_regs->sw108.refpic_valid_flag = (validFlags << 16); in set_vlc_regs()
450 set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num in set_vlc_regs()
452 set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num in set_vlc_regs()
456 p_regs->sw57.rd_cnt_tab_en = 1; in set_vlc_regs()
485 RK_U32 *ref_reg = &p_regs->sw76; in set_vlc_regs()
507 p_regs->sw115.cabac_en = pp->entropy_coding_mode_flag; in set_vlc_regs()
511 p_regs->sw57.st_code_exit = 1; in set_vlc_regs()
515 p_regs->sw109.strm_start_bit = 0; //!< sodb stream start bit in set_vlc_regs()
516 p_regs->sw64.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf); in set_vlc_regs()
517 p_regs->sw51.stream_len = p_hal->strm_len; in set_vlc_regs()
523 static MPP_RET set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_ref_regs() argument
592 set_refer_pic_list_p(p_regs, i, m_lists[0][i].idx); in set_ref_regs()
593 set_refer_pic_list_b0(p_regs, i, m_lists[1][i].idx); in set_ref_regs()
594 set_refer_pic_list_b1(p_regs, i, m_lists[2][i].idx); in set_ref_regs()
631 static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_asic_regs() argument
694 set_refer_pic_base_addr(p_regs, i, mpp_buffer_get_fd(frame_buf)); in set_asic_regs()
709 p_regs->sw99.ref15_st_addr = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15 in set_asic_regs()
710 p_regs->sw108.refpic_valid_flag |= (pp->field_pic_flag in set_asic_regs()
714 p_regs->sw50.dec_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E in set_asic_regs()
715 p_regs->sw50.dblk_flt_dis = 0; //!< filterDisable = 0; in set_asic_regs()
723 p_regs->sw63.dec_out_st_adr = outPhyAddr; //!< outPhyAddr, pp->CurrPic.Index7Bits in set_asic_regs()
724 p_regs->sw110.flt_offset_cb_qp = pp->chroma_qp_index_offset; in set_asic_regs()
725 p_regs->sw110.flt_offset_cr_qp = pp->second_chroma_qp_index_offset; in set_asic_regs()
742 p_regs->sw62.dmmv_st_adr = mpp_buffer_get_fd(frame_buf); in set_asic_regs()
744 p_regs->sw57.dmmv_wr_en = (p_long->nal_ref_idc != 0) ? 1 : 0; //!< defalut set 1 in set_asic_regs()
745 p_regs->sw115.dlmv_method_en = pp->direct_8x8_inference_flag; in set_asic_regs()
746 p_regs->sw115.weight_pred_en = pp->weighted_pred_flag; in set_asic_regs()
747 p_regs->sw111.wp_bslice_sel = pp->weighted_bipred_idc; in set_asic_regs()
748 p_regs->sw114.max_refidx1 = (pp->num_ref_idx_l1_active_minus1 + 1); in set_asic_regs()
749 p_regs->sw115.fieldpic_flag_exist = (!pp->frame_mbs_only_flag) ? 1 : 0; in set_asic_regs()
750 p_regs->sw57.curpic_code_sel = (!pp->frame_mbs_only_flag in set_asic_regs()
752 p_regs->sw57.curpic_stru_sel = pp->field_pic_flag; in set_asic_regs()
753 p_regs->sw57.pic_decfield_sel = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; //!< bottomFieldFlag in set_asic_regs()
754 p_regs->sw57.sequ_mbaff_en = pp->MbaffFrameFlag; in set_asic_regs()
755 p_regs->sw115.tranf_8x8_flag_en = pp->transform_8x8_mode_flag; in set_asic_regs()
756 p_regs->sw115.monochr_en = (p_long->profileIdc >= 100 in set_asic_regs()
758 p_regs->sw115.scl_matrix_en = pp->scaleing_list_enable_flag; in set_asic_regs()
784 p_regs->sw61.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf); in set_asic_regs()
786 p_regs->sw57.dec_wr_extmen_dis = 0; //!< set defalut 0 in set_asic_regs()
787 p_regs->sw57.addit_ch_fmt_wen = 0; in set_asic_regs()
788 p_regs->sw57.dec_st_work = 1; in set_asic_regs()
937 H264dVdpuRegs_t *p_regs = p_hal->fast_mode ? in vdpu2_h264d_start() local
940 RK_U32 w = p_regs->sw110.pic_mb_w * 16; in vdpu2_h264d_start()
941 RK_U32 h = p_regs->sw110.pic_mb_h * 16; in vdpu2_h264d_start()
955 p_regs->sw57.cache_en = cache_en; in vdpu2_h264d_start()
956 p_regs->sw57.pref_sigchan = 1; in vdpu2_h264d_start()
957 p_regs->sw56.bus_pos_sel = 1; in vdpu2_h264d_start()
958 p_regs->sw57.intra_dbl3t = 1; in vdpu2_h264d_start()
959 p_regs->sw57.inter_dblspeed = 1; in vdpu2_h264d_start()
960 p_regs->sw57.intra_dblspeed = 1; in vdpu2_h264d_start()
1031 H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)(p_hal->fast_mode ? in vdpu2_h264d_wait() local
1050 param.hard_err = !p_regs->sw55.dec_rdy_sts; in vdpu2_h264d_wait()
1054 memset(&p_regs->sw55, 0, sizeof(RK_U32)); in vdpu2_h264d_wait()