Lines Matching refs:p_regs
33 AvsdVdpu1Regs_t *p_regs = (AvsdVdpu1Regs_t *)p_hal->p_regs; in set_defalut_parameters() local
35 p_regs->sw02.dec_out_endian = 1; in set_defalut_parameters()
36 p_regs->sw02.dec_in_endian = 0; in set_defalut_parameters()
37 p_regs->sw02.dec_strendian_e = 1; in set_defalut_parameters()
38 p_regs->sw02.dec_max_burst = 16; in set_defalut_parameters()
39 p_regs->sw02.dec_scmd_dis = 0; in set_defalut_parameters()
41 p_regs->sw02.dec_adv_pre_dis = 0; in set_defalut_parameters()
42 p_regs->sw55.apf_threshold = 8; in set_defalut_parameters()
43 p_regs->sw02.dec_latency = 0; in set_defalut_parameters()
45 p_regs->sw02.dec_data_disc_e = 0; in set_defalut_parameters()
46 p_regs->sw02.dec_outswap32_e = 1; in set_defalut_parameters()
47 p_regs->sw02.dec_inswap32_e = 1; in set_defalut_parameters()
48 p_regs->sw02.dec_strswap32_e = 1; in set_defalut_parameters()
50 p_regs->sw02.dec_timeout_e = 0; in set_defalut_parameters()
51 p_regs->sw02.dec_clk_gate_e = 1; in set_defalut_parameters()
52 p_regs->sw01.dec_irq_dis = 0; in set_defalut_parameters()
54 p_regs->sw02.dec_axi_rd_id = 0xFF; in set_defalut_parameters()
55 p_regs->sw03.dec_axi_wr_id = 0; in set_defalut_parameters()
57 p_regs->sw49.pred_bc_tap_0_0 = 0x3FF; in set_defalut_parameters()
58 p_regs->sw49.pred_bc_tap_0_1 = 5; in set_defalut_parameters()
59 p_regs->sw49.pred_bc_tap_0_2 = 5; in set_defalut_parameters()
60 p_regs->sw34.pred_bc_tap_0_3 = 0x3FF; in set_defalut_parameters()
61 p_regs->sw34.pred_bc_tap_1_0 = 1; in set_defalut_parameters()
62 p_regs->sw34.pred_bc_tap_1_1 = 7; in set_defalut_parameters()
63 p_regs->sw35.pred_bc_tap_1_2 = 7; in set_defalut_parameters()
64 p_regs->sw35.pred_bc_tap_1_3 = 1; in set_defalut_parameters()
66 p_regs->sw02.tiled_mode_lsb = 0; in set_defalut_parameters()
76 AvsdVdpu1Regs_t *p_regs = (AvsdVdpu1Regs_t *)p_hal->p_regs; in set_regs_parameters() local
80 p_regs->sw02.dec_timeout_e = 1; in set_regs_parameters()
81 p_regs->sw02.dec_clk_gate_e = 1; in set_regs_parameters()
82 p_regs->sw01.dec_irq_dis = 0; in set_regs_parameters()
83 p_regs->sw03.rlc_mode_e = 0; in set_regs_parameters()
102 p_regs->sw04.pic_mb_width = (p_syn->pp.horizontalSize + 15) >> 4; in set_regs_parameters()
103 p_regs->sw03.dec_mode = 11; //!< DEC_MODE_AVS in set_regs_parameters()
106 p_regs->sw03.pic_interlace_e = 0; in set_regs_parameters()
107 p_regs->sw03.pic_fieldmode_e = 0; in set_regs_parameters()
108 p_regs->sw03.pic_topfiled_e = 0; in set_regs_parameters()
110 p_regs->sw03.pic_interlace_e = 1; in set_regs_parameters()
111 p_regs->sw03.pic_fieldmode_e = 1; in set_regs_parameters()
112 p_regs->sw03.pic_topfiled_e = p_hal->first_field; in set_regs_parameters()
115 p_regs->sw04.pic_mb_height_p = (p_syn->pp.verticalSize + 15) >> 4; in set_regs_parameters()
119 p_regs->sw03.pic_b_e = 1; in set_regs_parameters()
121 p_regs->sw03.pic_b_e = 0; in set_regs_parameters()
123 p_regs->sw03.pic_inter_e = (p_syn->pp.picCodingType != IFRAME) ? 1 : 0; in set_regs_parameters()
126 p_regs->sw05.strm_start_bit = 8 * (p_hal->data_offset & 0x7); in set_regs_parameters()
128 p_regs->sw12.rlc_vlc_base = get_packet_fd(p_hal, task->input); in set_regs_parameters()
130 p_regs->sw06.stream_len = p_syn->bitstream_size - p_hal->data_offset; in set_regs_parameters()
131 p_regs->sw03.pic_fixed_quant = p_syn->pp.fixedPictureQp; in set_regs_parameters()
132 p_regs->sw06.init_qp = p_syn->pp.pictureQp; in set_regs_parameters()
134 p_regs->sw13.dec_out_base = get_frame_fd(p_hal, task->output); in set_regs_parameters()
152 p_regs->sw14.refer0_base = get_frame_fd(p_hal, task->output); in set_regs_parameters()
153 p_regs->sw15.refer1_base = get_frame_fd(p_hal, refer0); in set_regs_parameters()
154 p_regs->sw16.refer2_base = get_frame_fd(p_hal, refer0); in set_regs_parameters()
155 p_regs->sw17.refer3_base = get_frame_fd(p_hal, refer1); in set_regs_parameters()
157 p_regs->sw14.refer0_base = get_frame_fd(p_hal, refer0); in set_regs_parameters()
158 p_regs->sw15.refer1_base = get_frame_fd(p_hal, refer0); in set_regs_parameters()
159 p_regs->sw16.refer2_base = get_frame_fd(p_hal, refer1); in set_regs_parameters()
160 p_regs->sw17.refer3_base = get_frame_fd(p_hal, refer1); in set_regs_parameters()
174 p_regs->sw31.ref_dist_cur_2 = tmp; in set_regs_parameters()
175 p_regs->sw31.ref_dist_cur_3 = tmp; in set_regs_parameters()
176 p_regs->sw29.ref_invd_cur_2 = 512 / tmp; in set_regs_parameters()
177 p_regs->sw29.ref_invd_cur_3 = 512 / tmp; in set_regs_parameters()
185 p_regs->sw30.ref_dist_cur_0 = tmp; in set_regs_parameters()
186 p_regs->sw30.ref_dist_cur_1 = tmp; in set_regs_parameters()
187 p_regs->sw28.ref_invd_cur_0 = 512 / tmp; in set_regs_parameters()
188 p_regs->sw28.ref_invd_cur_1 = 512 / tmp; in set_regs_parameters()
196 p_regs->sw32.ref_invd_col_0 = tmp; in set_regs_parameters()
197 p_regs->sw32.ref_invd_col_1 = tmp; in set_regs_parameters()
201 p_regs->sw33.ref_invd_col_2 = tmp; in set_regs_parameters()
202 p_regs->sw33.ref_invd_col_3 = tmp; in set_regs_parameters()
211 p_regs->sw30.ref_dist_cur_0 = tmp; in set_regs_parameters()
212 p_regs->sw30.ref_dist_cur_1 = tmp; in set_regs_parameters()
213 p_regs->sw28.ref_invd_cur_0 = 512 / tmp; in set_regs_parameters()
214 p_regs->sw28.ref_invd_cur_1 = 512 / tmp; in set_regs_parameters()
224 p_regs->sw31.ref_dist_cur_2 = tmp; in set_regs_parameters()
225 p_regs->sw31.ref_dist_cur_3 = tmp; in set_regs_parameters()
226 p_regs->sw29.ref_invd_cur_2 = 512 / tmp; in set_regs_parameters()
227 p_regs->sw29.ref_invd_cur_3 = 512 / tmp; in set_regs_parameters()
229 p_regs->sw32.ref_invd_col_0 = 0; in set_regs_parameters()
230 p_regs->sw32.ref_invd_col_1 = 0; in set_regs_parameters()
231 p_regs->sw33.ref_invd_col_2 = 0; in set_regs_parameters()
232 p_regs->sw33.ref_invd_col_3 = 0; in set_regs_parameters()
247 p_regs->sw31.ref_dist_cur_2 = tmp; in set_regs_parameters()
248 p_regs->sw31.ref_dist_cur_3 = tmp + 1; in set_regs_parameters()
249 p_regs->sw29.ref_invd_cur_2 = 512 / tmp; in set_regs_parameters()
250 p_regs->sw29.ref_invd_cur_3 = 512 / (tmp + 1); in set_regs_parameters()
252 p_regs->sw31.ref_dist_cur_2 = tmp - 1; in set_regs_parameters()
253 p_regs->sw31.ref_dist_cur_3 = tmp; in set_regs_parameters()
254 p_regs->sw29.ref_invd_cur_2 = 512 / (tmp - 1); in set_regs_parameters()
255 p_regs->sw29.ref_invd_cur_3 = 512 / tmp; in set_regs_parameters()
264 p_regs->sw30.ref_dist_cur_0 = (tmp - 1); in set_regs_parameters()
265 p_regs->sw30.ref_dist_cur_1 = tmp; in set_regs_parameters()
266 p_regs->sw28.ref_invd_cur_0 = 512 / (tmp - 1); in set_regs_parameters()
267 p_regs->sw28.ref_invd_cur_1 = 512 / tmp; in set_regs_parameters()
269 p_regs->sw30.ref_dist_cur_0 = tmp; in set_regs_parameters()
270 p_regs->sw30.ref_dist_cur_1 = tmp + 1; in set_regs_parameters()
271 p_regs->sw28.ref_invd_cur_0 = 512 / tmp; in set_regs_parameters()
272 p_regs->sw28.ref_invd_cur_1 = 512 / (tmp + 1); in set_regs_parameters()
283 p_regs->sw32.ref_invd_col_0 = 16384 / (tmp - 1); in set_regs_parameters()
284 p_regs->sw32.ref_invd_col_1 = 16384 / tmp; in set_regs_parameters()
289 p_regs->sw33.ref_invd_col_2 = 16384 / (tmp - 1); in set_regs_parameters()
290 p_regs->sw33.ref_invd_col_3 = 16384 / tmp; in set_regs_parameters()
293 p_regs->sw32.ref_invd_col_0 = 16384 / (tmp - 1); in set_regs_parameters()
294 p_regs->sw32.ref_invd_col_1 = 16384 / tmp; in set_regs_parameters()
296 p_regs->sw32.ref_invd_col_0 = 16384; in set_regs_parameters()
297 p_regs->sw32.ref_invd_col_1 = 16384 / tmp; in set_regs_parameters()
298 p_regs->sw33.ref_invd_col_2 = 16384 / (tmp + 1); in set_regs_parameters()
305 p_regs->sw33.ref_invd_col_2 = 16384 / (tmp - 1); in set_regs_parameters()
306 p_regs->sw33.ref_invd_col_3 = 16384 / tmp; in set_regs_parameters()
308 p_regs->sw33.ref_invd_col_3 = 16384 / tmp; in set_regs_parameters()
320 p_regs->sw30.ref_dist_cur_0 = 1; in set_regs_parameters()
321 p_regs->sw31.ref_dist_cur_2 = tmp + 1; in set_regs_parameters()
323 p_regs->sw28.ref_invd_cur_0 = 512; in set_regs_parameters()
324 p_regs->sw29.ref_invd_cur_2 = 512 / (tmp + 1); in set_regs_parameters()
326 p_regs->sw30.ref_dist_cur_0 = tmp - 1; in set_regs_parameters()
327 p_regs->sw28.ref_invd_cur_0 = 512 / (tmp - 1); in set_regs_parameters()
329 p_regs->sw30.ref_dist_cur_1 = tmp; in set_regs_parameters()
330 p_regs->sw28.ref_invd_cur_1 = 512 / tmp; in set_regs_parameters()
340 p_regs->sw31.ref_dist_cur_2 = tmp - 1; in set_regs_parameters()
341 p_regs->sw31.ref_dist_cur_3 = tmp; in set_regs_parameters()
343 p_regs->sw29.ref_invd_cur_2 = 512 / (tmp - 1); in set_regs_parameters()
344 p_regs->sw29.ref_invd_cur_3 = 512 / tmp; in set_regs_parameters()
346 p_regs->sw31.ref_dist_cur_3 = tmp; in set_regs_parameters()
347 p_regs->sw29.ref_invd_cur_3 = 512 / tmp; in set_regs_parameters()
350 p_regs->sw32.ref_invd_col_0 = 0; in set_regs_parameters()
351 p_regs->sw32.ref_invd_col_1 = 0; in set_regs_parameters()
352 p_regs->sw33.ref_invd_col_2 = 0; in set_regs_parameters()
353 p_regs->sw33.ref_invd_col_3 = 0; in set_regs_parameters()
357 p_regs->sw48.startmb_x = 0; in set_regs_parameters()
358 p_regs->sw48.startmb_y = 0; in set_regs_parameters()
360 p_regs->sw03.filtering_dis = p_syn->pp.loopFilterDisable; in set_regs_parameters()
361 p_regs->sw05.alpha_offset = p_syn->pp.alphaOffset; in set_regs_parameters()
362 p_regs->sw05.beta_offset = p_syn->pp.betaOffset; in set_regs_parameters()
363 p_regs->sw03.skip_mode = p_syn->pp.skipModeFlag; in set_regs_parameters()
364 p_regs->sw04.pic_refer_flag = p_syn->pp.pictureReferenceFlag; in set_regs_parameters()
368 p_regs->sw03.write_mvs_e = 1; in set_regs_parameters()
370 p_regs->sw03.write_mvs_e = 0; in set_regs_parameters()
373 p_regs->sw41.dir_mv_base = mpp_buffer_get_fd(p_hal->mv_buf); in set_regs_parameters()
393 p_regs->sw18.prev_anc_type = prev_anc_type; in set_regs_parameters()
403 p_regs->sw03.dec_out_dis = 0; in set_regs_parameters()
404 p_regs->sw01.dec_e = 1; in set_regs_parameters()
442 AvsdVdpu1Regs_t *p_regs = (AvsdVdpu1Regs_t *)p_hal->p_regs; in repeat_other_field() local
445 p_hal->data_offset = p_regs->sw12.rlc_vlc_base >> 10; in repeat_other_field()
489 p_hal->p_regs = mpp_calloc_size(RK_U32, sizeof(AvsdVdpu1Regs_t)); in hal_avsd_vdpu1_init()
490 MEM_CHECK(ret, p_hal->p_regs); in hal_avsd_vdpu1_init()
529 MPP_FREE(p_hal->p_regs); in hal_avsd_vdpu1_deinit()
586 wr_cfg.reg = p_hal->p_regs; in hal_avsd_vdpu1_start()
596 rd_cfg.reg = p_hal->p_regs; in hal_avsd_vdpu1_start()
645 param.regs = (RK_U32 *)p_hal->p_regs; in hal_avsd_vdpu1_wait()
647 if (!((AvsdVdpu1Regs_t *)p_hal->p_regs)->sw01.dec_rdy_int) { in hal_avsd_vdpu1_wait()
654 … p_hal->p_regs[1], task->dec.flags.used_for_ref, task->dec.flags.ref_err, param.hard_err); in hal_avsd_vdpu1_wait()
657 memset(&p_hal->p_regs[1], 0, sizeof(RK_U32)); in hal_avsd_vdpu1_wait()