116     M2vdVdpu1Reg_t *p_regs = (M2vdVdpu1Reg_t *)ctx->regs;  in hal_m2vd_vdpu1_init_hwcfg()  local
118     memset(p_regs, 0, sizeof(M2vdVdpu1Reg_t));  in hal_m2vd_vdpu1_init_hwcfg()
119     p_regs->sw02.dec_axi_rn_id = 0;  in hal_m2vd_vdpu1_init_hwcfg()
120     p_regs->sw02.dec_timeout_e = 1;  in hal_m2vd_vdpu1_init_hwcfg()
121     p_regs->sw02.dec_strswap32_e = 1;  in hal_m2vd_vdpu1_init_hwcfg()
122     p_regs->sw02.dec_strendian_e = 1;  in hal_m2vd_vdpu1_init_hwcfg()
123     p_regs->sw02.dec_inswap32_e = 1;  in hal_m2vd_vdpu1_init_hwcfg()
124     p_regs->sw02.dec_outswap32_e = 1;  in hal_m2vd_vdpu1_init_hwcfg()
126     p_regs->sw02.dec_clk_gate_e = 1;  in hal_m2vd_vdpu1_init_hwcfg()
127     p_regs->sw02.dec_in_endian = 1;  in hal_m2vd_vdpu1_init_hwcfg()
128     p_regs->sw02.dec_out_endian = 1;  in hal_m2vd_vdpu1_init_hwcfg()
130     p_regs->sw02.dec_out_tiled_e = 0;  in hal_m2vd_vdpu1_init_hwcfg()
131     p_regs->sw02.dec_max_burst = DEC_BUS_BURST_LENGTH_16;  in hal_m2vd_vdpu1_init_hwcfg()
132     p_regs->sw02.dec_scmd_dis = 0;  in hal_m2vd_vdpu1_init_hwcfg()
133     p_regs->sw02.dec_adv_pre_dis = 0;  in hal_m2vd_vdpu1_init_hwcfg()
134     p_regs->sw55.apf_threshold = 8;  in hal_m2vd_vdpu1_init_hwcfg()
135     p_regs->sw02.dec_latency = 0;  in hal_m2vd_vdpu1_init_hwcfg()
136     p_regs->sw02.dec_data_disc_e = 0;  in hal_m2vd_vdpu1_init_hwcfg()
137     p_regs->sw01.dec_irq = 0;  in hal_m2vd_vdpu1_init_hwcfg()
138     p_regs->sw02.dec_axi_rn_id = 0;  in hal_m2vd_vdpu1_init_hwcfg()
139     p_regs->sw03.dec_axi_wr_id = 0;  in hal_m2vd_vdpu1_init_hwcfg()
140     p_regs->sw03.dec_mode = 8;  in hal_m2vd_vdpu1_init_hwcfg()
155         M2vdVdpu1Reg_t *p_regs = (M2vdVdpu1Reg_t*) ctx->regs;  in hal_m2vd_vdpu1_gen_regs()  local
164         p_regs->sw18.mv_accuracy_fwd = 1;  in hal_m2vd_vdpu1_gen_regs()
165         p_regs->sw18.mv_accuracy_bwd = 1;  in hal_m2vd_vdpu1_gen_regs()
167             p_regs->sw03.dec_mode = 5;  in hal_m2vd_vdpu1_gen_regs()
168             p_regs->sw18.fcode_fwd_hor = dx->pic.full_pel_forward_vector;  in hal_m2vd_vdpu1_gen_regs()
169             p_regs->sw18.fcode_fwd_ver = dx->pic.forward_f_code;  in hal_m2vd_vdpu1_gen_regs()
170             p_regs->sw18.fcode_bwd_hor = dx->pic.full_pel_backward_vector;  in hal_m2vd_vdpu1_gen_regs()
171             p_regs->sw18.fcode_bwd_ver = dx->pic.backward_f_code;  in hal_m2vd_vdpu1_gen_regs()
173             p_regs->sw03.dec_mode = 6;  in hal_m2vd_vdpu1_gen_regs()
174             p_regs->sw18.fcode_fwd_hor = dx->pic.forward_f_code;  in hal_m2vd_vdpu1_gen_regs()
175             p_regs->sw18.fcode_fwd_ver = dx->pic.forward_f_code;  in hal_m2vd_vdpu1_gen_regs()
176             p_regs->sw18.fcode_bwd_hor = dx->pic.backward_f_code;  in hal_m2vd_vdpu1_gen_regs()
177             p_regs->sw18.fcode_bwd_ver = dx->pic.backward_f_code;  in hal_m2vd_vdpu1_gen_regs()
179                 p_regs->sw18.mv_accuracy_fwd = 0;  in hal_m2vd_vdpu1_gen_regs()
181                 p_regs->sw18.mv_accuracy_bwd = 0;  in hal_m2vd_vdpu1_gen_regs()
184         p_regs->sw04.pic_mb_width = (dx->seq.decode_width + 15) >> 4;  in hal_m2vd_vdpu1_gen_regs()
185         p_regs->sw04.pic_mb_height_p = (dx->seq.decode_height + 15) >> 4;  in hal_m2vd_vdpu1_gen_regs()
186         p_regs->sw03.pic_interlace_e = 1 - dx->seq_ext.progressive_sequence;  in hal_m2vd_vdpu1_gen_regs()
188             p_regs->sw03.pic_fieldmode_e = 0;  in hal_m2vd_vdpu1_gen_regs()
190             p_regs->sw03.pic_fieldmode_e = 1;  in hal_m2vd_vdpu1_gen_regs()
191             p_regs->sw03.pic_topfield_e = dx->pic_code_ext.picture_structure == 1;  in hal_m2vd_vdpu1_gen_regs()
194             p_regs->sw03.pic_b_e = 1;  in hal_m2vd_vdpu1_gen_regs()
196             p_regs->sw03.pic_b_e = 0;  in hal_m2vd_vdpu1_gen_regs()
198             p_regs->sw03.pic_inter_e = 0;  in hal_m2vd_vdpu1_gen_regs()
200             p_regs->sw03.pic_inter_e = 1;  in hal_m2vd_vdpu1_gen_regs()
202         p_regs->sw04.topfieldfirst_e = dx->pic_code_ext.top_field_first;  in hal_m2vd_vdpu1_gen_regs()
203         p_regs->sw03.fwd_interlace_e = 0;  in hal_m2vd_vdpu1_gen_regs()
204         p_regs->sw03.write_mvs_e = 0;  in hal_m2vd_vdpu1_gen_regs()
205         p_regs->sw04.alt_scan_e = dx->pic_code_ext.alternate_scan;  in hal_m2vd_vdpu1_gen_regs()
206         p_regs->sw18.alt_scan_flag_e = dx->pic_code_ext.alternate_scan;  in hal_m2vd_vdpu1_gen_regs()
208         p_regs->sw05.qscale_type = dx->pic_code_ext.q_scale_type;  in hal_m2vd_vdpu1_gen_regs()
209         p_regs->sw05.intra_dc_prec = dx->pic_code_ext.intra_dc_precision;  in hal_m2vd_vdpu1_gen_regs()
210         p_regs->sw05.con_mv_e = dx->pic_code_ext.concealment_motion_vectors;  in hal_m2vd_vdpu1_gen_regs()
211         p_regs->sw05.intra_vlc_tab = dx->pic_code_ext.intra_vlc_format;  in hal_m2vd_vdpu1_gen_regs()
212         p_regs->sw05.frame_pred_dct = dx->pic_code_ext.frame_pred_frame_dct;  in hal_m2vd_vdpu1_gen_regs()
213         p_regs->sw06.init_qp = 1;  in hal_m2vd_vdpu1_gen_regs()
216         p_regs->sw12.rlc_vlc_base = mpp_buffer_get_fd(streambuf);  in hal_m2vd_vdpu1_gen_regs()
225             p_regs->sw13.dec_out_base = mpp_buffer_get_fd(framebuf);  in hal_m2vd_vdpu1_gen_regs()
227             p_regs->sw13.dec_out_base = mpp_buffer_get_fd(framebuf);  in hal_m2vd_vdpu1_gen_regs()
232         p_regs->sw14.refer0_base = mpp_buffer_get_fd(framebuf);  in hal_m2vd_vdpu1_gen_regs()
235         p_regs->sw15.refer1_base = mpp_buffer_get_fd(framebuf);  in hal_m2vd_vdpu1_gen_regs()
238         p_regs->sw16.refer2_base = mpp_buffer_get_fd(framebuf);  in hal_m2vd_vdpu1_gen_regs()
241         p_regs->sw17.refer3_base = mpp_buffer_get_fd(framebuf);  in hal_m2vd_vdpu1_gen_regs()
243         p_regs->sw40.qtable_base = mpp_buffer_get_fd(ctx->qp_table);  in hal_m2vd_vdpu1_gen_regs()
245         p_regs->sw48.startmb_x = 0;  in hal_m2vd_vdpu1_gen_regs()
246         p_regs->sw48.startmb_y = 0;  in hal_m2vd_vdpu1_gen_regs()
247         p_regs->sw03.dec_out_dis = 0;  in hal_m2vd_vdpu1_gen_regs()
248         p_regs->sw03.filtering_dis = 1;  in hal_m2vd_vdpu1_gen_regs()
249         p_regs->sw06.stream_len = dx->bitstream_length;  in hal_m2vd_vdpu1_gen_regs()
250         p_regs->sw05.stream_start_bit = dx->bitstream_start_bit;  in hal_m2vd_vdpu1_gen_regs()
251         p_regs->sw01.dec_e = 1;  in hal_m2vd_vdpu1_gen_regs()