| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 292 void __iomem *base, ulong pll_id, in rk3036_pll_set_rate() argument
354 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id); in rk3036_pll_set_rate()
371 void __iomem *base, ulong pll_id) in rk3036_pll_get_rate() argument
445 void __iomem *base, ulong pll_id, in rk3588_pll_set_rate() argument
463 if (pll_id == 3) in rk3588_pll_set_rate()
469 if (pll_id == 0) in rk3588_pll_set_rate()
473 else if (pll_id == 1) in rk3588_pll_set_rate()
477 else if (pll_id == 2) in rk3588_pll_set_rate()
506 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); in rk3588_pll_set_rate()
511 if (pll_id == 0) { in rk3588_pll_set_rate()
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| H A D | clk_px30.c | 105 enum px30_pll_id pll_id);
215 enum px30_pll_id pll_id, in rkclk_set_pll() argument
241 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
242 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); in rkclk_set_pll()
263 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
264 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); in rkclk_set_pll()
270 enum px30_pll_id pll_id) in rkclk_pll_get_rate() argument
276 shift = pll_mode_shift[pll_id]; in rkclk_pll_get_rate()
277 mask = pll_mode_mask[pll_id]; in rkclk_pll_get_rate()
1230 enum px30_pll_id pll_id) in px30_clk_get_pll_rate() argument
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| H A D | clk_rk3368.c | 224 enum rk3368_pll_id pll_id) in rkclk_pll_get_rate() argument
228 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
249 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, in rkclk_set_pll() argument
252 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
874 u32 pll_div, pll_id, con_id; in rk3368_armclk_set_clk() local
895 pll_id = APLLB; in rk3368_armclk_set_clk()
899 pll_id = APLLL; in rk3368_armclk_set_clk()
904 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
922 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
925 return rkclk_pll_get_rate(priv->cru, pll_id); in rk3368_armclk_set_clk()
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| H A D | clk_rk3066.c | 110 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
111 struct rk3066_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
252 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
253 struct rk3066_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
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| H A D | clk_rk3036.c | 65 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
66 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
206 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
207 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
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| H A D | clk_rk3188.c | 108 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
109 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
250 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
251 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
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| H A D | clk_rv1108.c | 68 int pll_id = rv1108_pll_id(clk_id); in rkclk_set_pll() local
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
122 int pll_id = rv1108_pll_id(clk_id); in rkclk_pll_get_rate() local
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
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| H A D | clk_rk3288.c | 238 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
239 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
274 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
275 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
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| H A D | clk_rk3568.c | 118 ulong pll_id, ulong rate) in rk3568_pmu_pll_set_rate() argument
133 rockchip_pll_set_rate(&rk3568_pll_clks[pll_id], in rk3568_pmu_pll_set_rate()
134 pmu_priv->pmucru, pll_id, rate); in rk3568_pmu_pll_set_rate()
140 ulong pll_id) in rk3568_pmu_pll_get_rate() argument
155 return rockchip_pll_get_rate(&rk3568_pll_clks[pll_id], in rk3568_pmu_pll_get_rate()
156 pmu_priv->pmucru, pll_id); in rk3568_pmu_pll_get_rate()
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| H A D | clk_rk3399.c | 410 enum rk3399_pll_id pll_id) in rk3399_pll_get_rate() argument
415 switch (pll_id) { in rk3399_pll_get_rate()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_px30.h | 71 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
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| H A D | clock.h | 139 ulong pll_id) in rockchip_pll_get_rate() argument
145 void __iomem *base, ulong pll_id, in rockchip_pll_set_rate() argument
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| H A D | sdram_rk3328.h | 51 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
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| H A D | sdram_rv1126.h | 247 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
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