Home
last modified time | relevance | path

Searched refs:int32_t (Results 1 – 25 of 284) sorted by relevance

12345678910>>...12

/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/include/
H A Dmce_private.h89 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state,
95 int32_t (*update_cstate_info)(uint32_t ari_base,
107 int32_t (*update_crossover_time)(uint32_t ari_base,
120 int32_t (*write_cstate_stats)(uint32_t ari_base,
136 int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
146 int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
153 int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid);
158 int32_t (*cc3_ctrl)(uint32_t ari_base,
166 int32_t (*update_reset_vector)(uint32_t ari_base);
171 int32_t (*roc_flush_cache)(uint32_t ari_base);
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/include/
H A Dtegra_private.h41 int32_t uart_id;
43 int32_t l2_ecc_parity_prot_dis;
77 int32_t tegra_soc_validate_power_state(uint32_t power_state,
82 void plat_enable_console(int32_t id);
94 int32_t plat_lock_cpu_vectors(void);
98 int32_t tegra_fiq_get_intr_context(void);
111 int32_t tegra_system_suspended(void);
112 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
113 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
114 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.h13 int32_t apupwr_smc_acc_init_all(void);
15 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
16 int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);
17 int32_t apupwr_smc_bulk_pll(bool enable);
20 int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en);
21 int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
22 enum pll_set_rate_mode mode, int32_t freq);
/rk3399_ARM-atf/include/drivers/
H A Dscmi-msg.h128 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
140 int32_t plat_scmi_clock_rates_by_step(unsigned int agent_id,
153 int32_t plat_scmi_clock_get_possible_parents(unsigned int agent_id,
165 int32_t plat_scmi_clock_get_parent(unsigned int agent_id,
175 int32_t plat_scmi_clock_set_parent(unsigned int agent_id,
195 int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id,
204 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id);
213 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id,
224 int32_t plat_scmi_clock_get_extended_config(unsigned int agent_id,
237 int32_t plat_scmi_clock_set_extended_config(unsigned int agent_id,
[all …]
/rk3399_ARM-atf/include/drivers/brcm/emmc/
H A Demmc_chal_sd.h169 int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode,
171 int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed,
174 int32_t chal_sd_stop(void);
175 int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode);
177 int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width);
178 int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex,
180 int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address);
181 int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle,
184 int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data,
185 uint32_t length, int32_t dir);
[all …]
/rk3399_ARM-atf/plat/xilinx/common/
H A Dversal.c26 int32_t plat_is_smccc_feature_available(u_register_t fid) in plat_is_smccc_feature_available()
28 int32_t ret = 0; in plat_is_smccc_feature_available()
47 int32_t plat_get_soc_version(void) in plat_get_soc_version()
53 return (int32_t)(manfid | (platform_version & SOC_ID_IMPL_DEF_MASK)); in plat_get_soc_version()
64 int32_t plat_get_soc_revision(void) in plat_get_soc_revision()
66 return (int32_t)(platform_id & SOC_ID_REV_MASK); in plat_get_soc_revision()
/rk3399_ARM-atf/drivers/renesas/common/io/
H A Dio_memdrv.c20 static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)),
22 static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
42 static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, in memdrv_block_open()
66 static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode, in memdrv_block_seek()
78 static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer, in memdrv_block_read()
101 static int32_t memdrv_block_close(io_entity_t *entity) in memdrv_block_close()
131 static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)), in memdrv_dev_open()
139 static int32_t memdrv_dev_close(io_dev_info_t *dev_info) in memdrv_dev_close()
144 int32_t rcar_register_io_dev_memdrv(const io_dev_connector_t **dev_con) in rcar_register_io_dev_memdrv()
146 int32_t result; in rcar_register_io_dev_memdrv()
H A Dio_emmcdrv.c21 static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
23 static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info);
41 static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode, in emmcdrv_block_seek()
53 static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, in emmcdrv_block_read()
58 int32_t result = IO_SUCCESS; in emmcdrv_block_read()
83 static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, in emmcdrv_block_open()
127 static int32_t emmcdrv_block_close(io_entity_t *entity) in emmcdrv_block_close()
156 static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)), in emmcdrv_dev_open()
164 static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info) in emmcdrv_dev_close()
169 int32_t rcar_register_io_dev_emmcdrv(const io_dev_connector_t **dev_con) in rcar_register_io_dev_emmcdrv()
[all …]
/rk3399_ARM-atf/drivers/scmi-msg/
H A Dsensor.h33 int32_t status;
51 int32_t min_range_low;
52 int32_t min_range_high;
53 int32_t max_range_low;
54 int32_t max_range_high;
62 int32_t status;
71 int32_t status;
91 int32_t status;
99 int32_t (*sensor_reading_get)(uint32_t agent_id, uint16_t sensor_id,
H A Dclock.h46 int32_t status;
61 int32_t status;
94 int32_t status;
118 int32_t status;
134 int32_t status;
149 int32_t status;
164 int32_t status;
177 int32_t status;
215 int32_t status;
H A Dreset_domain.h43 int32_t status;
63 int32_t status;
85 int32_t status;
101 int32_t status;
109 int32_t status;
/rk3399_ARM-atf/plat/amd/versal2/
H A Dplat_psci.c35 static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) in zynqmp_nopmu_pwr_domain_on()
37 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT); in zynqmp_nopmu_pwr_domain_on()
38 int32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER; in zynqmp_nopmu_pwr_domain_on()
39 int32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER; in zynqmp_nopmu_pwr_domain_on()
42 int32_t ret = PSCI_E_SUCCESS; in zynqmp_nopmu_pwr_domain_on()
104 static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint) in zynqmp_validate_ns_entrypoint()
106 int32_t ret = PSCI_E_INVALID_ADDRESS; in zynqmp_validate_ns_entrypoint()
130 static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) in zynqmp_validate_power_state()
149 int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, in plat_setup_psci_ops()
166 static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id, in no_pm_ioctl()
[all …]
H A Dplat_psci_pm.c34 static int32_t versal2_pwr_domain_on(u_register_t mpidr) in versal2_pwr_domain_on()
36 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); in versal2_pwr_domain_on()
37 int32_t ret = (int32_t) PSCI_E_INTERN_FAIL; in versal2_pwr_domain_on()
52 ret = (int32_t) PSCI_E_SUCCESS; in versal2_pwr_domain_on()
110 int32_t ret; in versal2_system_reset()
140 } while ((ret != (int32_t)IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U)); in versal2_system_reset()
194 static int32_t versal2_validate_ns_entrypoint(uint64_t ns_entrypoint) in versal2_validate_ns_entrypoint()
196 int32_t ret = PSCI_E_SUCCESS; in versal2_validate_ns_entrypoint()
297 } while ((ret != (int32_t)IPI_MB_STATUS_RECV_PENDING) && !timeout_elapsed(timeout)); in versal2_system_off()
314 static int32_t versal2_validate_power_state(unsigned int power_state, in versal2_validate_power_state()
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dari.c80 static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req, in ari_request_wait()
85 int32_t ret = 0; in ari_request_wait()
137 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) in ari_enter_cstate()
139 int32_t ret = 0; in ari_enter_cstate()
160 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, in ari_update_cstate_info()
198 int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) in ari_update_crossover_time()
200 int32_t ret = 0; in ari_update_crossover_time()
220 int32_t ret; in ari_read_cstate_stats()
241 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) in ari_write_cstate_stats()
254 int32_t ret; in ari_enumeration_misc()
[all …]
H A Dnvg.c19 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_enter_cstate()
21 int32_t ret = 0; in nvg_enter_cstate()
47 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, in nvg_update_cstate_info()
89 int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) in nvg_update_crossover_time()
91 int32_t ret = 0; in nvg_update_crossover_time()
137 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) in nvg_write_cstate_stats()
163 int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_is_ccx_allowed()
173 int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_is_sc7_allowed()
176 int32_t ret; in nvg_is_sc7_allowed()
204 int32_t nvg_online_core(uint32_t ari_base, uint32_t core) in nvg_online_core()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/pmic_wrap/
H A Dpmic_wrap_init_v3.c81 static int32_t pwrap_swinf_acc(uint32_t swinf_no, uint32_t cmd, uint32_t write, in pwrap_swinf_acc()
86 int32_t ret = 0x0; in pwrap_swinf_acc()
166 int32_t pwrap_read(uint32_t adr, uint32_t *rdata) in pwrap_read()
172 int32_t pwrap_write(uint32_t adr, uint32_t wdata) in pwrap_write()
178 int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift) in pwrap_read_field()
181 int32_t ret; in pwrap_read_field()
192 int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift) in pwrap_write_field()
195 int32_t ret; in pwrap_write_field()
209 static int32_t pwrap_read_test(void) in pwrap_read_test()
212 int32_t ret; in pwrap_read_test()
[all …]
H A Dpmic_wrap_init_common.h15 int32_t pmic_wrap_test(void);
16 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
17 int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
18 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
19 int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
/rk3399_ARM-atf/drivers/arm/dcc/
H A Ddcc_console.c77 static int32_t dcc_status_timeout(uint32_t mask) in dcc_status_timeout()
95 static int32_t dcc_console_putc(int32_t ch, console_t *console) in dcc_console_putc()
97 int32_t status; in dcc_console_putc()
111 static int32_t dcc_console_getc(console_t *console) in dcc_console_getc()
113 int32_t status; in dcc_console_getc()
132 int32_t status; in dcc_console_flush()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/include/
H A Dmce_private.h51 int32_t nvg_set_cstate_stat_query_value(uint64_t data);
53 int32_t nvg_is_sc7_allowed(void);
54 int32_t nvg_online_core(uint32_t core);
55 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
56 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
57 int32_t nvg_roc_clean_cache_trbits(void);
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/bpmp_ipc/
H A Divc.h33 int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
38 int32_t tegra_ivc_channel_notified(struct ivc *ivc);
40 int32_t tegra_ivc_write_advance(struct ivc *ivc);
42 int32_t tegra_ivc_write(struct ivc *ivc, const void *buf, size_t size);
43 int32_t tegra_ivc_read_advance(struct ivc *ivc);
45 int32_t tegra_ivc_read(struct ivc *ivc, void *buf, size_t max_read);
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/
H A Dnvg.c101 int32_t nvg_is_sc7_allowed(void) in nvg_is_sc7_allowed()
107 return (int32_t)nvg_get_result(); in nvg_is_sc7_allowed()
116 int32_t nvg_online_core(uint32_t core) in nvg_online_core()
118 int32_t ret = 0; in nvg_online_core()
139 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) in nvg_update_ccplex_gsc()
141 int32_t ret = 0; in nvg_update_ccplex_gsc()
158 int32_t nvg_roc_clean_cache_trbits(void) in nvg_roc_clean_cache_trbits()
160 int32_t ret = 0; in nvg_roc_clean_cache_trbits()
179 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) in nvg_enter_cstate()
181 int32_t ret = 0; in nvg_enter_cstate()
H A Dmce.c43 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler()
46 int32_t ret = 0; in mce_command_handler()
85 int32_t mce_update_gsc_videomem(void) in mce_update_gsc_videomem()
87 int32_t ret; in mce_update_gsc_videomem()
104 int32_t mce_update_gsc_tzdram(void) in mce_update_gsc_tzdram()
106 int32_t ret; in mce_update_gsc_tzdram()
179 int32_t ret = 0; in mce_enable_strict_checking()
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.c238 int32_t (*parents)[];
804 static int32_t can_mio_parents[] = {
833 .parents = &((int32_t []) {CLK_APLL_PRE_SRC, CLK_NA_PARENT}),
841 .parents = &((int32_t []) {
859 .parents = &((int32_t []) {CLK_APLL_INT, CLK_NA_PARENT}),
867 .parents = &((int32_t []) {
879 .parents = &((int32_t []) {
897 .parents = &((int32_t []) {
909 .parents = &((int32_t []) {CLK_DPLL_PRE_SRC, CLK_NA_PARENT}),
917 .parents = &((int32_t []) {
[all …]
/rk3399_ARM-atf/plat/arm/board/morello/
H A Dmorello_bl31_setup.c77 int32_t plat_is_smccc_feature_available(u_register_t fid) in plat_is_smccc_feature_available()
88 int32_t plat_get_soc_version(void) in plat_get_soc_version()
94 return (int32_t) in plat_get_soc_version()
101 int32_t plat_get_soc_revision(void) in plat_get_soc_revision()
103 return (int32_t)plat_info.silicon_revision; in plat_get_soc_revision()
/rk3399_ARM-atf/drivers/renesas/common/console/
H A Drcar_printf.h12 int32_t rcar_set_log_data(int32_t c);
13 int32_t rcar_log_init(void);

12345678910>>...12