141612559SVarun Wadekar /* 222c72f2aSVarun Wadekar * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 722c72f2aSVarun Wadekar #ifndef MCE_PRIVATE_H 822c72f2aSVarun Wadekar #define MCE_PRIVATE_H 941612559SVarun Wadekar 100789758aSVignesh Radhakrishnan #include <stdbool.h> 1141612559SVarun Wadekar #include <tegra_def.h> 1241612559SVarun Wadekar 1341612559SVarun Wadekar /******************************************************************************* 1441612559SVarun Wadekar * Macros to prepare CSTATE info request 1541612559SVarun Wadekar ******************************************************************************/ 1641612559SVarun Wadekar /* Description of the parameters for UPDATE_CSTATE_INFO request */ 176152de3bSAnthony Zhou #define CLUSTER_CSTATE_MASK 0x7U 186152de3bSAnthony Zhou #define CLUSTER_CSTATE_SHIFT 0X0U 196152de3bSAnthony Zhou #define CLUSTER_CSTATE_UPDATE_BIT (1U << 7) 204b412b50SVignesh Radhakrishnan #define CCPLEX_CSTATE_MASK 0x7U 216152de3bSAnthony Zhou #define CCPLEX_CSTATE_SHIFT 8U 226152de3bSAnthony Zhou #define CCPLEX_CSTATE_UPDATE_BIT (1U << 15) 236152de3bSAnthony Zhou #define SYSTEM_CSTATE_MASK 0xFU 246152de3bSAnthony Zhou #define SYSTEM_CSTATE_SHIFT 16U 256152de3bSAnthony Zhou #define SYSTEM_CSTATE_UPDATE_BIT (1U << 23) 266152de3bSAnthony Zhou #define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31) 276152de3bSAnthony Zhou #define CSTATE_WAKE_MASK_SHIFT 32U 286152de3bSAnthony Zhou #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU 2941612559SVarun Wadekar 3041612559SVarun Wadekar /******************************************************************************* 319808032cSSteven Kao * Core ID mask (bits 3:0 in the online request) 3241612559SVarun Wadekar ******************************************************************************/ 336152de3bSAnthony Zhou #define MCE_CORE_ID_MASK 0xFU 3441612559SVarun Wadekar 3541612559SVarun Wadekar /******************************************************************************* 3668d13a2eSKrishna Sitaraman * C-state statistics macros 3768d13a2eSKrishna Sitaraman ******************************************************************************/ 386152de3bSAnthony Zhou #define MCE_STAT_ID_SHIFT 16U 3968d13a2eSKrishna Sitaraman 40ac252f95SDilan Lee /******************************************************************************* 41ac252f95SDilan Lee * Security config macros 42ac252f95SDilan Lee ******************************************************************************/ 43ac252f95SDilan Lee #define STRICT_CHECKING_ENABLED_SET (1UL << 0) 44ac252f95SDilan Lee #define STRICT_CHECKING_LOCKED_SET (1UL << 1) 45ac252f95SDilan Lee 4641612559SVarun Wadekar /* declarations for NVG handler functions */ 479808032cSSteven Kao uint64_t nvg_get_version(void); 489808032cSSteven Kao void nvg_set_wake_time(uint32_t wake_time); 499808032cSSteven Kao void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, 509808032cSSteven Kao uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); 519808032cSSteven Kao int32_t nvg_set_cstate_stat_query_value(uint64_t data); 529808032cSSteven Kao uint64_t nvg_get_cstate_stat_query_value(void); 539808032cSSteven Kao int32_t nvg_is_sc7_allowed(void); 549808032cSSteven Kao int32_t nvg_online_core(uint32_t core); 559808032cSSteven Kao int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); 569808032cSSteven Kao int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); 57bf14df1eSVarun Wadekar int32_t nvg_roc_clean_cache_trbits(void); 58532df956SVarun Wadekar void nvg_enable_strict_checking_mode(void); 59*5ce05d6bSAnthony Zhou void nvg_verify_strict_checking_mode(void); 60532df956SVarun Wadekar void nvg_system_shutdown(void); 61532df956SVarun Wadekar void nvg_system_reboot(void); 620d851195SVarun Wadekar void nvg_clear_hsm_corr_status(void); 63532df956SVarun Wadekar 64532df956SVarun Wadekar /* declarations for assembly functions */ 659808032cSSteven Kao void nvg_set_request_data(uint64_t req, uint64_t data); 669808032cSSteven Kao void nvg_set_request(uint64_t req); 679808032cSSteven Kao uint64_t nvg_get_result(void); 6872e8caa7SSteven Kao uint64_t nvg_cache_clean(void); 6972e8caa7SSteven Kao uint64_t nvg_cache_clean_inval(void); 7072e8caa7SSteven Kao uint64_t nvg_cache_inval_all(void); 71ac252f95SDilan Lee 72ac252f95SDilan Lee /* MCE helper functions */ 73ac252f95SDilan Lee void mce_enable_strict_checking(void); 74*5ce05d6bSAnthony Zhou void mce_verify_strict_checking(void); 750789758aSVignesh Radhakrishnan void mce_system_shutdown(void); 760789758aSVignesh Radhakrishnan void mce_system_reboot(void); 770d851195SVarun Wadekar void mce_clear_hsm_corr_status(void); 7841612559SVarun Wadekar 7922c72f2aSVarun Wadekar #endif /* MCE_PRIVATE_H */ 80