xref: /rk3399_ARM-atf/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h (revision 52c47c174fadb9e1398af41e9bbf290af314e8ec)
1ca93b018SBo-Chen Chen /*
2ca93b018SBo-Chen Chen  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3ca93b018SBo-Chen Chen  *
4ca93b018SBo-Chen Chen  * SPDX-License-Identifier: BSD-3-Clause
5ca93b018SBo-Chen Chen  */
6ca93b018SBo-Chen Chen 
7ca93b018SBo-Chen Chen #ifndef PMIC_WRAP_INIT_COMMON_H
8ca93b018SBo-Chen Chen #define PMIC_WRAP_INIT_COMMON_H
9ca93b018SBo-Chen Chen 
10ca93b018SBo-Chen Chen #include <stdint.h>
11ca93b018SBo-Chen Chen 
12ca93b018SBo-Chen Chen #include "platform_def.h"
13ca93b018SBo-Chen Chen 
14ca93b018SBo-Chen Chen /* external API */
15*9c9324ccSZhigang Qin int32_t pmic_wrap_test(void);
16ca93b018SBo-Chen Chen int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
17*9c9324ccSZhigang Qin int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
18ca93b018SBo-Chen Chen int32_t pwrap_write(uint32_t adr, uint32_t wdata);
19*9c9324ccSZhigang Qin int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
20ca93b018SBo-Chen Chen 
21*9c9324ccSZhigang Qin #define GET_SWINF_INIT_DONE(x)	((x>>15) & 0x00000001)
22ca93b018SBo-Chen Chen #define GET_WACS_FSM(x)		((x >> 1) & 0x7)
23ca93b018SBo-Chen Chen 
24ca93b018SBo-Chen Chen /* macro for SWINF_FSM */
25ca93b018SBo-Chen Chen #define SWINF_FSM_IDLE		(0x00)
26ca93b018SBo-Chen Chen #define SWINF_FSM_REQ		(0x02)
27ca93b018SBo-Chen Chen #define SWINF_FSM_WFDLE		(0x04)
28ca93b018SBo-Chen Chen #define SWINF_FSM_WFVLDCLR	(0x06)
29ca93b018SBo-Chen Chen #define SWINF_INIT_DONE		(0x01)
30ca93b018SBo-Chen Chen 
31ca93b018SBo-Chen Chen /* timeout setting */
32ca93b018SBo-Chen Chen #define PWRAP_READ_US		(1000)
33ca93b018SBo-Chen Chen #define PWRAP_WAIT_IDLE_US	(1000)
34ca93b018SBo-Chen Chen 
35ca93b018SBo-Chen Chen /* error information flag */
36ca93b018SBo-Chen Chen enum pwrap_errno {
37ca93b018SBo-Chen Chen 	E_PWR_INVALID_ARG		= 1,
38ca93b018SBo-Chen Chen 	E_PWR_INVALID_RW		= 2,
39ca93b018SBo-Chen Chen 	E_PWR_INVALID_ADDR		= 3,
40ca93b018SBo-Chen Chen 	E_PWR_INVALID_WDAT		= 4,
41ca93b018SBo-Chen Chen 	E_PWR_INVALID_OP_MANUAL		= 5,
42ca93b018SBo-Chen Chen 	E_PWR_NOT_IDLE_STATE		= 6,
43ca93b018SBo-Chen Chen 	E_PWR_NOT_INIT_DONE		= 7,
44ca93b018SBo-Chen Chen 	E_PWR_NOT_INIT_DONE_READ	= 8,
45ca93b018SBo-Chen Chen 	E_PWR_WAIT_IDLE_TIMEOUT		= 9,
46ca93b018SBo-Chen Chen 	E_PWR_WAIT_IDLE_TIMEOUT_READ	= 10,
47ca93b018SBo-Chen Chen 	E_PWR_INIT_SIDLY_FAIL		= 11,
48ca93b018SBo-Chen Chen 	E_PWR_RESET_TIMEOUT		= 12,
49ca93b018SBo-Chen Chen 	E_PWR_TIMEOUT			= 13,
50*9c9324ccSZhigang Qin 	E_PWR_INVALID_SWINF		= 14,
51*9c9324ccSZhigang Qin 	E_PWR_INVALID_CMD		= 15,
52*9c9324ccSZhigang Qin 	E_PWR_INVALID_PMIFID		= 16,
53*9c9324ccSZhigang Qin 	E_PWR_INVALID_SLVID		= 17,
54*9c9324ccSZhigang Qin 	E_PWR_INVALID_BYTECNT		= 18,
55ca93b018SBo-Chen Chen 	E_PWR_INIT_RESET_SPI		= 20,
56ca93b018SBo-Chen Chen 	E_PWR_INIT_SIDLY		= 21,
57ca93b018SBo-Chen Chen 	E_PWR_INIT_REG_CLOCK		= 22,
58ca93b018SBo-Chen Chen 	E_PWR_INIT_ENABLE_PMIC		= 23,
59ca93b018SBo-Chen Chen 	E_PWR_INIT_DIO			= 24,
60ca93b018SBo-Chen Chen 	E_PWR_INIT_CIPHER		= 25,
61ca93b018SBo-Chen Chen 	E_PWR_INIT_WRITE_TEST		= 26,
62ca93b018SBo-Chen Chen 	E_PWR_INIT_ENABLE_CRC		= 27,
63ca93b018SBo-Chen Chen 	E_PWR_INIT_ENABLE_DEWRAP	= 28,
64ca93b018SBo-Chen Chen 	E_PWR_INIT_ENABLE_EVENT		= 29,
65ca93b018SBo-Chen Chen 	E_PWR_READ_TEST_FAIL		= 30,
66ca93b018SBo-Chen Chen 	E_PWR_WRITE_TEST_FAIL		= 31,
67ca93b018SBo-Chen Chen 	E_PWR_SWITCH_DIO		= 32,
68ca93b018SBo-Chen Chen };
69ca93b018SBo-Chen Chen 
70ca93b018SBo-Chen Chen #endif /* PMIC_WRAP_INIT_COMMON_H */
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