Merge changes from topic "tegra-downstream-08252020" into integration

* changes:
Tegra194: remove unused tegra_mc_defs header
Tegra: memctrl: platform setup handler functions
Tegra194: memctrl

Merge changes from topic "tegra-downstream-08252020" into integration

* changes:
Tegra194: remove unused tegra_mc_defs header
Tegra: memctrl: platform setup handler functions
Tegra194: memctrl: remove streamid security cfg registers
Tegra194: memctrl: remove streamid override cfg registers
Tegra: debug prints indicating SC7 entry sequence completion
Tegra194: add strict checking mode verification
Tegra194: memctrl: update TZDRAM base at 1MB granularity
Tegra194: ras: split up RAS error clear SMC call.
Tegra: platform specific GIC sources
Tegra194: add memory barriers during DRAM to SysRAM copy
Tegra: sip: add VPR resize enabled check
Tegra194: add redundancy checks for MMIO writes
Tegra: remove unused cortex_a53.h
Tegra194: report failure to enable dual execution
Tegra194: verify firewall settings before resource use

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Tegra194: add strict checking mode verification

After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.

If the mode is found to be disabled

Tegra194: add strict checking mode verification

After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.

If the mode is found to be disabled, the code should
assert.

Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Merge changes from topic "tegra194-ras-handling" into integration

* changes:
Tegra194: ras: verbose prints for SErrors
Prevent RAS register access from lower ELs
Tegra194: SiP: clear RAS corre

Merge changes from topic "tegra194-ras-handling" into integration

* changes:
Tegra194: ras: verbose prints for SErrors
Prevent RAS register access from lower ELs
Tegra194: SiP: clear RAS corrected error records
Tegra194: add RAS exception handling

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Tegra194: SiP: clear RAS corrected error records

This patch introduces a function ID to clear all the RAS error
records for corrected errors.

Per latest requirement, ARM RAS corrected errors will b

Tegra194: SiP: clear RAS corrected error records

This patch introduces a function ID to clear all the RAS error
records for corrected errors.

Per latest requirement, ARM RAS corrected errors will be reported to
lower ELs via interrupts and cleared via SMC. This patch provides
required function to clear RAS error status.

This patch also sets up all required RAS Corrected errors in order to
route RAS corrected errors to lower ELs.

Change-Id: I554ba1d0797b736835aa27824782703682c91e51
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: David Pu <dpu@nvidia.com>

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Merge "Tegra194: mce: declare nvg_roc_clean_cache_trbits()" into integration

Tegra194: mce: declare nvg_roc_clean_cache_trbits()

This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

C

Tegra194: mce: declare nvg_roc_clean_cache_trbits()

This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

Change-Id: I313556f6799792fc0141afb5822cc157db80bc47
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "tegra-downstream-01242020" into integration

* changes:
Tegra186: memctrl: lock stream id security config
Tegra194: remove support for simulated system suspend
Tegra19

Merge changes from topic "tegra-downstream-01242020" into integration

* changes:
Tegra186: memctrl: lock stream id security config
Tegra194: remove support for simulated system suspend
Tegra194: mce: fix multiple MISRA issues
Tegra: bpmp: fix multiple MISRA issues
Tegra194: se: fix multiple MISRA issues
Tegra: compile PMC driver for Tegra132/Tegra210 platforms
Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler
Tegra: remove weakly defined per-platform SiP handler
Tegra: remove weakly defined PSCI platform handlers
Tegra: remove weakly defined platform setup handlers
Tegra: per-SoC DRAM base values

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Tegra194: mce: fix multiple MISRA issues

This patch fixes violations of the following MISRA rules

* Rule 8.5 "An external object or function shall be declared once in
one and only one

Tegra194: mce: fix multiple MISRA issues

This patch fixes violations of the following MISRA rules

* Rule 8.5 "An external object or function shall be declared once in
one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
object with a narrower essential type or of a different
esential type category"

Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "Enable -Wredundant-decls warning check" into integration

Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently,

Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "tegra-downstream-01202020" into integration

* changes:
Tegra194: mce: remove unused NVG functions
Tegra194: support for NVG interface v6.6
Tegra194: smmu: add PCIE0R1

Merge changes from topic "tegra-downstream-01202020" into integration

* changes:
Tegra194: mce: remove unused NVG functions
Tegra194: support for NVG interface v6.6
Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list
Tegra194: enable driver for general purpose DMA engine
Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms
Tegra194: organize the memory/mmio map to make it linear
Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1
Tegra194: support for boot params wider than 32-bits
Tegra194: memctrl: set reorder depth limit for PCIE blocks
Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU
Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Tegra194: memctrl: Disable PVARDC coalescer
Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent
Tegra194: Request CG7 from last core in cluster
Tegra194: toggle SE clock during context save/restore
Tegra: bpmp: fix header file paths

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Tegra194: mce: remove unused NVG functions

This patch removes unused functions from the NVG driver.

* nvg_enable_power_perf_mode
* nvg_disable_power_perf_mode
* nvg_enable_power_saver_modes
* nvg_d

Tegra194: mce: remove unused NVG functions

This patch removes unused functions from the NVG driver.

* nvg_enable_power_perf_mode
* nvg_disable_power_perf_mode
* nvg_enable_power_saver_modes
* nvg_disable_power_saver_modes
* nvg_roc_clean_cache
* nvg_roc_flush_cache

Change-Id: I0387a40dec35686deaad623a8350de89acfe9393
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "tegra-downstream-01082020" into integration

* changes:
Tegra194: platform handler for entering CPU standby state
Tegra194: memctrl: force viw and vifalr/w transactions

Merge changes from topic "tegra-downstream-01082020" into integration

* changes:
Tegra194: platform handler for entering CPU standby state
Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
Tegra194: memctrl: fix bug in client order id reg value generation
Tegra194: memctrl: enable mc coalescer
Tegra194: update scratch registers used to read boot parameters
Tegra194: implement system shutdown/reset handlers
Tegra194: mce: support for shutdown and reboot
Tegra194: request CG7 before checking if SC7 is allowed
Tegra194: config to enable/disable strict checking mode
Tegra194: remove unused platform configs
Tegra194: restore XUSB stream IDs on System Resume

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Tegra194: mce: support for shutdown and reboot

This patch adds support for shutdown/reboot handlers to the MCE
driver.

ATF communicates with mce using nvg interface for shutdown &
reboot. Both shut

Tegra194: mce: support for shutdown and reboot

This patch adds support for shutdown/reboot handlers to the MCE
driver.

ATF communicates with mce using nvg interface for shutdown &
reboot. Both shutdown and reboot use the same nvg index.
However, the 1st bit of the nvg data argument differentiates
whether its a shutdown or reboot.

Change-Id: Id2d1b0c4fec55abf69b7f8adb65ca70bfa920e73
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Merge changes from topic "tegra-misra-21.1-fixes" into integration

* changes:
Tegra194: drivers: fix violations of MISRA Rule 21.1
Tegra: include: fix violations of MISRA Rule 21.1

Tegra194: drivers: fix violations of MISRA Rule 21.1

This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved

Tegra194: drivers: fix violations of MISRA Rule 21.1

This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc

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Merge "Remove redundant declarations." into integration

Remove redundant declarations.

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by:

Remove redundant declarations.

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: int

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: introduce plat_enable_console()
Tegra: include: drivers: introduce spe.h
Tegra194: update nvg header to v6.4
Tegra194: mce: enable strict checking
Tegra194: CC6 state from last offline CPU in the cluster
Tegra194: console driver compilation from platform makefiles
Tegra194: memctrl: platform handler for TZDRAM setup
Tegra194: memctrl: override SE client as coherent
Tegra194: save system suspend entry marker to TZDRAM
Tegra194: helper functions for CPU rst handler and SMMU ctx offset
Tegra194: cleanup references to Tegra186
Tegra194: mce: display NVG header version during boot
Tegra194: mce: fix cg_cstate encoding format
Tegra194: drivers: SE and RNG1/PKA1 context save support
Tegra194: rename secure scratch register macros
Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
Tegra194: mce: remove unsupported functionality
Tegra194: sanity check target cluster during core power on
Tegra194: fix defects flagged by MISRA scan
Tegra194: mce: fix defects flagged by MISRA scan
Tegra194: remove the GPU reset register macro
Tegra194: MC registers to allow CPU accesses to TZRAM
Tegra194: increase MAX_MMAP_REGIONS macro value
Tegra194: update nvg header to v6.1
Tegra194: update cache operations supported by the ROC
Tegra194: memctrl: platform handlers to reprogram MSS
Tegra194: core and cluster count values
Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
Tegra194: add MC_SECURITY mask defines
Tegra194: Update wake mask, wake time for cpu offlining
Tegra194: program stream ids for XUSB
Tegra194: Update checks for c-state stats
Tegra194: smmu: fix mask for board revision id
Tegra194: smmu: ISO support
Tegra194: Initialize smmu on system suspend exit
Tegra194: Update cpu core-id calculation
Tegra194: read-modify-write ACTLR_ELx registers
Tegra194: Enable fake system suspend
Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
Tegra194: platform support for memctrl/smmu drivers
Tegra194: Support for cpu suspend

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Tegra194: mce: enable strict checking

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure

Tegra194: mce: enable strict checking

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure-only areas are defined
as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set.
This mode not only helps prevent issues with IO-Coherency but aids
with security as well.

This patch implements the programming sequence required to enable
strict checking mode for Tegra194 SoCs.

Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0
Signed-off-by: Dilan Lee <dilee@nvidia.com>

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Tegra194: mce: fix cg_cstate encoding format

This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9

Tegra194: mce: fix cg_cstate encoding format

This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info
- cg_cstate values can range from 0 to 7, with 7 representing cg7
- Thus, cg_cstate is to be encoded using 3 bits (val: 0-7)
- Fix this, as per ISS and ensure bits 8, 9, 10 are used

Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation

Rule 8.4, A compatible declaration shall be visible when an object
or function with external linkage is defined.

Add function delaration to the

Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation

Rule 8.4, A compatible declaration shall be visible when an object
or function with external linkage is defined.

Add function delaration to the header file.
Add suffix U to the unsigned constant define.

Change-Id: I54eba913a5fa38e4fdf3655931dc421d9510c691
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra194: mce: remove unsupported functionality

This patch cleans up the mce driver files to remove all the unsupported
functionality. The MCE/NVG interface is not restricted to the EL3 space,
so cl

Tegra194: mce: remove unsupported functionality

This patch cleans up the mce driver files to remove all the unsupported
functionality. The MCE/NVG interface is not restricted to the EL3 space,
so clients can issue commands to the MCE firmware directly.

Change-Id: Idcebc42f31805f9c1abe1c1edc17850151aca11d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Fix

Tegra194: mce: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Fix variable essential type doesn't match [Rule 10.3]

Added curly braces ({}) around if/while statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra194: update cache operations supported by the ROC

This patch updates the cache ops to use system registers in
order to trigger cache flush/clean operations.

Change-Id: I888abad22f22b8a33c7193b

Tegra194: update cache operations supported by the ROC

This patch updates the cache ops to use system registers in
order to trigger cache flush/clean operations.

Change-Id: I888abad22f22b8a33c7193b991fad8c4a78030d0
Signed-off-by: Steven Kao <skao@nvidia.com>

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