| /optee_os/core/arch/arm/plat-marvell/ |
| H A D | platform_config.h | 60 #define GIC_BASE GIC_DIST_BASE macro
72 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
73 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
98 #define GIC_BASE GIC_DIST_BASE macro
103 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
104 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
119 #define GIC_BASE 0x801000000000ll macro
122 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
141 #define GIC_BASE 0x801000000000ll macro
144 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
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| H A D | main.c | 68 #ifdef GIC_BASE
80 gicc_base = GIC_BASE + GICC_OFFSET; in boot_primary_init_intc()
82 gicd_base = GIC_BASE + GICD_OFFSET; in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | platform_config.h | 21 #define GIC_BASE 0x32010000 macro
23 #define GICD_BASE (GIC_BASE + 0x1000)
24 #define GICC_BASE (GIC_BASE + 0x2000)
49 #define GIC_BASE (MMIO_BASE + 0x06E00000) macro
52 #define GICD_BASE GIC_BASE
53 #define GICR_BASE (GIC_BASE + SIZE_M(1))
72 #define GIC_BASE 0xff130000 macro
74 #define GICD_BASE (GIC_BASE + 0x1000)
75 #define GICC_BASE (GIC_BASE + 0x2000)
91 #define GIC_BASE 0xfe600000 macro
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| /optee_os/core/arch/arm/plat-ls/ |
| H A D | platform_config.h | 44 #define GIC_BASE 0x01400000 macro
53 #define GIC_BASE 0x01400000 macro
67 #define GIC_BASE 0x01400000 macro
77 #define GIC_BASE 0x06000000 macro
87 #define GIC_BASE 0x06000000 macro
97 #define GIC_BASE 0x06000000 macro
107 #define GIC_BASE 0x06000000 macro
117 #define GIC_BASE 0x06000000 macro
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| /optee_os/core/arch/arm/plat-mediatek/ |
| H A D | platform_config.h | 22 #define GIC_BASE 0x10220000 macro
40 #define GIC_BASE 0x0C000000 macro
54 #define GIC_BASE 0x10310000 macro
68 #define GIC_BASE 0x0C000000 macro
82 #define GIC_BASE 0x0C000000 macro
96 #define GIC_BASE 0x0C000000 macro
110 #define GIC_BASE 0x0C000000 macro
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| H A D | main.c | 25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET,
27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET,
32 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-vexpress/ |
| H A D | platform_config.h | 17 #define GIC_BASE 0x2c000000 macro
31 #define GIC_BASE 0x2c010000 macro
57 #define GIC_BASE 0x08000000 macro
70 #define GIC_BASE 0x08000000 macro
85 #define GIC_BASE 0x40060000 macro
159 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
160 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
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| H A D | main.c | 60 gic_init_v3(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET, in boot_primary_init_intc()
63 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-sprd/ |
| H A D | main.c | 41 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
45 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
50 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-totalcompute/ |
| H A D | platform_config.h | 18 #define GIC_BASE 0x30000000 macro
41 #ifdef GIC_BASE
42 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
43 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
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| H A D | main.c | 31 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICC_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-corstone1000/ |
| H A D | platform_config.h | 14 #define GIC_BASE 0x1c000000 macro
38 #define GICR_BASE (GIC_BASE + GICR_OFFSET)
40 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
42 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
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| /optee_os/core/arch/arm/plat-uniphier/ |
| H A D | main.c | 22 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
26 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
40 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-rzn1/ |
| H A D | platform_config.h | 17 #define GIC_BASE 0x44100000 macro
20 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
21 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
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| /optee_os/core/arch/arm/plat-nuvoton/ |
| H A D | platform_config.h | 16 #define GIC_BASE 0xDFFF8000 macro
22 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
23 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
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| /optee_os/core/arch/arm/plat-zynqmp/ |
| H A D | main.c | 56 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
60 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
80 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-imx/ |
| H A D | main.c | 48 #ifdef GIC_BASE
49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
113 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-versal/ |
| H A D | main.c | 35 GIC_BASE, CORE_MMU_PGDIR_SIZE);
38 GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE);
51 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-aspeed/ |
| H A D | platform_ast2600.c | 47 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET, GIC_DIST_REG_SIZE);
48 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET, GIC_CPU_REG_SIZE);
65 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-sunxi/ |
| H A D | main.c | 47 #ifdef GIC_BASE
48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
128 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-zynq7k/ |
| H A D | platform_config.h | 38 #define GIC_BASE 0xF8F00000 macro
41 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
42 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
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| H A D | main.c | 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
146 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-imx/registers/ |
| H A D | imx6.h | 85 #define GIC_BASE 0x00A00000 macro
100 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
101 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
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| /optee_os/core/arch/arm/plat-synquacer/ |
| H A D | main.c | 27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
40 gic_init(0, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-stm32mp2/ |
| H A D | main.c | 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE);
148 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
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