Home
last modified time | relevance | path

Searched refs:reg32 (Results 1 – 25 of 49) sorted by relevance

12

/OK3568_Linux_fs/u-boot/drivers/video/
H A Divybridge_igd.c334 u32 reg32; in gma_pm_init_pre_vbios() local
350 reg32 = gtt_read(gtt_bar, 0x42004); in gma_pm_init_pre_vbios()
351 reg32 |= (1 << 14) | (1 << 15); in gma_pm_init_pre_vbios()
352 gtt_write(gtt_bar, 0x42004, reg32); in gma_pm_init_pre_vbios()
357 reg32 = gtt_read(gtt_bar, 0x45010); in gma_pm_init_pre_vbios()
358 reg32 |= (1 << 1) | (1 << 0); in gma_pm_init_pre_vbios()
359 gtt_write(gtt_bar, 0x45010, reg32); in gma_pm_init_pre_vbios()
363 reg32 = gtt_read(gtt_bar, 0x911c); in gma_pm_init_pre_vbios()
365 if (reg32 & (1 << 13)) { in gma_pm_init_pre_vbios()
375 if (reg32 & (1 << 13)) { in gma_pm_init_pre_vbios()
[all …]
H A Dbroadwell_igd.c358 u32 reg32; in igd_setup_panel() local
361 reg32 = (plat->dp_hotplug[0] & 0x7) << 2; in igd_setup_panel()
362 reg32 |= (plat->dp_hotplug[1] & 0x7) << 10; in igd_setup_panel()
363 reg32 |= (plat->dp_hotplug[2] & 0x7) << 18; in igd_setup_panel()
364 gtt_write(priv, PCH_PORT_HOTPLUG, reg32); in igd_setup_panel()
367 reg32 = (plat->port_select & 0x3) << 30; in igd_setup_panel()
368 reg32 |= (plat->power_up_delay & 0x1fff) << 16; in igd_setup_panel()
369 reg32 |= (plat->power_backlight_on_delay & 0x1fff); in igd_setup_panel()
370 gtt_write(priv, PCH_PP_ON_DELAYS, reg32); in igd_setup_panel()
373 reg32 = (plat->power_down_delay & 0x1fff) << 16; in igd_setup_panel()
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/cpu/broadwell/
H A Dsata.c44 u32 reg32; in broadwell_sata_init() local
63 dm_pci_read_config32(dev, 0x98, &reg32); in broadwell_sata_init()
64 reg32 &= ~((1 << 31) | (1 << 30)); in broadwell_sata_init()
65 reg32 |= 1 << 23; in broadwell_sata_init()
66 reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ in broadwell_sata_init()
67 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
75 reg32 = 0x183; in broadwell_sata_init()
76 reg32 |= (plat->port_map ^ 0xf) << 24; in broadwell_sata_init()
77 reg32 |= (plat->devslp_mux & 1) << 15; in broadwell_sata_init()
78 dm_pci_write_config32(dev, 0x94, reg32); in broadwell_sata_init()
[all …]
H A Dpch.c110 u32 reg32; in pch_enable_ioapic() local
116 reg32 = io_apic_read(0x01); in pch_enable_ioapic()
119 reg32 &= ~0x00ff0000; in pch_enable_ioapic()
120 reg32 |= 0x00270000; in pch_enable_ioapic()
122 io_apic_write(0x01, reg32); in pch_enable_ioapic()
377 u32 reg32; in pch_cg_init() local
409 reg32 = readl(RCB_REG(CG)); in pch_cg_init()
411 reg32 &= ~(1 << 29); /* LPC Dynamic */ in pch_cg_init()
413 reg32 |= (1 << 29); /* LPC Dynamic */ in pch_cg_init()
414 reg32 |= 1 << 31; /* LP LPC */ in pch_cg_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/cpu/ivybridge/
H A Dsata.c21 u32 reg32; in common_sata_init() local
25 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; in common_sata_init()
26 dm_pci_write_config32(dev, IDE_CONFIG, reg32); in common_sata_init()
45 u32 reg32; in bd82x6x_sata_init() local
78 reg32 = readl(abar + 0x00); in bd82x6x_sata_init()
79 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ in bd82x6x_sata_init()
80 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ in bd82x6x_sata_init()
83 reg32 &= ~0x00f00000; in bd82x6x_sata_init()
84 reg32 |= (speed_support & 0x03) << 20; in bd82x6x_sata_init()
86 writel(reg32, abar + 0x00); in bd82x6x_sata_init()
[all …]
H A Dlpc.c32 u32 reg32; in pch_enable_apic() local
43 reg32 = readl(IO_APIC_DATA); in pch_enable_apic()
45 writel(reg32, IO_APIC_DATA); in pch_enable_apic()
48 reg32 = readl(IO_APIC_DATA); in pch_enable_apic()
49 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); in pch_enable_apic()
50 if (reg32 != (1 << 25)) { in pch_enable_apic()
59 reg32 = readl(IO_APIC_DATA); in pch_enable_apic()
60 debug(" 0x%08x\n", reg32); in pch_enable_apic()
134 u32 reg32; in pch_power_options() local
224 reg32 = inl(pmbase + 0x04); /* PM1_CNT */ in pch_power_options()
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/pcie/
H A Daer.c145 u32 reg32; in enable_ecrc_checking() local
150 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32); in enable_ecrc_checking()
151 if (reg32 & PCI_ERR_CAP_ECRC_GENC) in enable_ecrc_checking()
152 reg32 |= PCI_ERR_CAP_ECRC_GENE; in enable_ecrc_checking()
153 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) in enable_ecrc_checking()
154 reg32 |= PCI_ERR_CAP_ECRC_CHKE; in enable_ecrc_checking()
155 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); in enable_ecrc_checking()
169 u32 reg32; in disable_ecrc_checking() local
174 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32); in disable_ecrc_checking()
175 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); in disable_ecrc_checking()
[all …]
H A Daspm.c172 u32 reg32; in pcie_clkpm_cap_init() local
179 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32); in pcie_clkpm_cap_init()
180 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_clkpm_cap_init()
663 u32 reg32, encoding; in pcie_aspm_cap_init() local
671 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32); in pcie_aspm_cap_init()
673 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; in pcie_aspm_cap_init()
676 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; in pcie_aspm_cap_init()
811 u32 reg32; in pcie_aspm_sanity_check() local
834 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32); in pcie_aspm_sanity_check()
835 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { in pcie_aspm_sanity_check()
H A Dportdrv_core.c67 u32 reg32; in pcie_message_numbers() local
72 &reg32); in pcie_message_numbers()
73 *aer = (reg32 & PCI_ERR_ROOT_AER_IRQ) >> 27; in pcie_message_numbers()
/OK3568_Linux_fs/u-boot/board/tqc/tqm834x/
H A Dpci.c59 u32 reg32; in pci_init_board() local
71 reg32 = OCCR_PCICOE1; in pci_init_board()
74 reg32 = 0xff000000; in pci_init_board()
79 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); in pci_init_board()
81 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ in pci_init_board()
86 clk->occr = reg32; in pci_init_board()
/OK3568_Linux_fs/kernel/drivers/pci/
H A Dpci-acpi.c286 u32 reg32; in program_hpx_type2() local
336 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32); in program_hpx_type2()
337 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; in program_hpx_type2()
338 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpx_type2()
341 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32); in program_hpx_type2()
342 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; in program_hpx_type2()
343 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpx_type2()
346 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32); in program_hpx_type2()
347 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; in program_hpx_type2()
348 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpx_type2()
[all …]
/OK3568_Linux_fs/kernel/drivers/infiniband/hw/hfi1/
H A Daspm.c49 u32 reg32; in aspm_hw_set_l1_ent_latency() local
51 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, &reg32); in aspm_hw_set_l1_ent_latency()
52 reg32 &= ~PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK; in aspm_hw_set_l1_ent_latency()
53 reg32 |= l1_ent_lat << PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT; in aspm_hw_set_l1_ent_latency()
54 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, reg32); in aspm_hw_set_l1_ent_latency()
H A Dpcie.c996 u32 reg32, fs, lf; in do_pcie_gen3_transition() local
1118 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; in do_pcie_gen3_transition()
1119 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1128 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; in do_pcie_gen3_transition()
1129 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1387 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, &reg32); in do_pcie_gen3_transition()
1394 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
77 reg32 &= 0xc0000000; in ar9002_hw_set_channel()
149 reg32 = reg32 | in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
H A Dar5008_phy.c116 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ar5008_hw_phy_modify_rx_buffer() argument
123 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ar5008_hw_phy_modify_rx_buffer()
216 u32 reg32 = 0; in ar5008_hw_set_channel() local
271 reg32 = in ar5008_hw_set_channel()
275 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
H A Dar9003_phy.c152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel() local
205 reg32 = (bMode << 29); in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
213 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
219 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
H A Deeprom_4k.c296 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local
360 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_4k_power_cal_table()
361 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
366 reg32); in ath9k_hw_set_4k_power_cal_table()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/vp8d/
H A Dhal_vp8d_vdpu1.c532 regs->reg32.sw_filt_level_0 = pic_param->filter_level; in hal_vp8d_vdpu1_gen_regs()
534 regs->reg32.sw_filt_level_0 = in hal_vp8d_vdpu1_gen_regs()
536 regs->reg32.sw_filt_level_1 = in hal_vp8d_vdpu1_gen_regs()
538 regs->reg32.sw_filt_level_2 = in hal_vp8d_vdpu1_gen_regs()
540 regs->reg32.sw_filt_level_3 = in hal_vp8d_vdpu1_gen_regs()
543 regs->reg32.sw_filt_level_0 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
546 regs->reg32.sw_filt_level_1 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
549 regs->reg32.sw_filt_level_2 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
552 regs->reg32.sw_filt_level_3 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
/OK3568_Linux_fs/kernel/drivers/ipack/carriers/
H A Dtpci200.c524 u32 reg32; in tpci200_pci_probe() local
558 reg32 = ioread32(tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
559 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
560 iowrite32(reg32, tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
562 reg32 = ioread32(tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
563 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
564 iowrite32(reg32, tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c860 u32 reg32; in cdns_mhdp_link_training_init() local
867 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_TYPE(1); in cdns_mhdp_link_training_init()
869 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_init()
871 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_init()
1031 u32 reg32; in cdns_mhdp_link_training_channel_eq() local
1038 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_EN | in cdns_mhdp_link_training_channel_eq()
1041 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_channel_eq()
1042 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_channel_eq()
1248 u32 reg32; in cdns_mhdp_link_training() local
1306 ret = cdns_mhdp_reg_read(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG, &reg32); in cdns_mhdp_link_training()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/mellanox/mlx5/core/
H A Dfw_reset.c257 u32 reg32; in mlx5_pci_link_toggle() local
296 err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, &reg32); in mlx5_pci_link_toggle()
299 if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) { in mlx5_pci_link_toggle()
300 mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32); in mlx5_pci_link_toggle()
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/
H A D_pcie.c2404 u32 reg_addr_l, reg_addr_h, reg32, val32, bd_num; in trx_init_bd() local
2485 ret = get_txbd_num_reg(adapter, ch, &reg32); in trx_init_bd()
2491 val16 = SET_CLR_WORD(MAC_REG_R16(reg32), bd_num, in trx_init_bd()
2493 MAC_REG_W16(reg32, val16); in trx_init_bd()
2495 ret = get_txbd_ram_reg(adapter, ch, &reg32); in trx_init_bd()
2501 val32 = MAC_REG_R32(reg32); in trx_init_bd()
2508 MAC_REG_W32(reg32, val32); in trx_init_bd()
2528 ret = get_rxbd_num_reg(adapter, ch, &reg32); in trx_init_bd()
2549 val16 = SET_CLR_WORD(MAC_REG_R16(reg32), bd_num, in trx_init_bd()
2551 MAC_REG_W16(reg32, val16); in trx_init_bd()
[all …]
/OK3568_Linux_fs/u-boot/drivers/serial/
H A Dserial_lpuart.c387 struct lpuart_fsl_reg32 *reg32 = plat->reg; in lpuart_serial_pending() local
394 lpuart_read32(plat->flags, &reg32->stat, &stat); in lpuart_serial_pending()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/freescale/fman/
H A Dfman_memac.c1031 u32 reg32 = 0; in memac_init() local
1074 reg32 = ioread32be(&memac->regs->command_config); in memac_init()
1075 reg32 &= ~CMD_CFG_CRC_FWD; in memac_init()
1076 iowrite32be(reg32, &memac->regs->command_config); in memac_init()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_vdpu2.c471 reg->reg32.sw_contrast_off1 = off1; in jpegd_setup_pp()
472 reg->reg32.sw_contrast_off2 = off2; in jpegd_setup_pp()
479 reg->reg32.sw_contrast_off1 = 0; in jpegd_setup_pp()
480 reg->reg32.sw_contrast_off2 = 0; in jpegd_setup_pp()

12