1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2005
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <asm/mmu.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <mpc83xx.h>
13*4882a593Smuzhiyun #include <pci.h>
14*4882a593Smuzhiyun #include <i2c.h>
15*4882a593Smuzhiyun #include <asm/fsl_i2c.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static struct pci_region pci1_regions[] = {
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MEM_BASE,
22*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
23*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MEM_SIZE,
24*4882a593Smuzhiyun flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
25*4882a593Smuzhiyun },
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_IO_BASE,
28*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_IO_PHYS,
29*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_IO_SIZE,
30*4882a593Smuzhiyun flags: PCI_REGION_IO
31*4882a593Smuzhiyun },
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
34*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
35*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MMIO_SIZE,
36*4882a593Smuzhiyun flags: PCI_REGION_MEM
37*4882a593Smuzhiyun },
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun * pci_init_board()
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
44*4882a593Smuzhiyun * per TQM834x design physical connections to external devices (PCI sockets)
45*4882a593Smuzhiyun * are routed only to the PCI1 we do not account for the second one - this code
46*4882a593Smuzhiyun * supports PCI1 module only. Should support for the PCI2 be required in the
47*4882a593Smuzhiyun * future it needs a separate pci_controller structure (above) and handling -
48*4882a593Smuzhiyun * please refer to other boards' implementation for dual PCI host controllers,
49*4882a593Smuzhiyun * for example board/Marvell/db64360/pci.c, pci_init_board()
50*4882a593Smuzhiyun *
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun void
pci_init_board(void)53*4882a593Smuzhiyun pci_init_board(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
56*4882a593Smuzhiyun volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
57*4882a593Smuzhiyun volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
58*4882a593Smuzhiyun struct pci_region *reg[] = { pci1_regions };
59*4882a593Smuzhiyun u32 reg32;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Configure PCI controller and PCI_CLK_OUTPUT
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
65*4882a593Smuzhiyun * line actually used for clocking all external PCI devices in TQM83xx.
66*4882a593Smuzhiyun * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
67*4882a593Smuzhiyun * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
68*4882a593Smuzhiyun * are known to hang the board; this issue is under investigation
69*4882a593Smuzhiyun * (13 oct 05)
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun reg32 = OCCR_PCICOE1;
72*4882a593Smuzhiyun #if 0
73*4882a593Smuzhiyun /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
74*4882a593Smuzhiyun reg32 = 0xff000000;
75*4882a593Smuzhiyun #endif
76*4882a593Smuzhiyun if (clk->spmr & SPMR_CKID) {
77*4882a593Smuzhiyun /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
78*4882a593Smuzhiyun * fields accordingly */
79*4882a593Smuzhiyun reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
82*4882a593Smuzhiyun | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
83*4882a593Smuzhiyun | OCCR_PCICD6 | OCCR_PCICD7);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun clk->occr = reg32;
87*4882a593Smuzhiyun udelay(2000);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Configure PCI Local Access Windows */
90*4882a593Smuzhiyun pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
91*4882a593Smuzhiyun pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
94*4882a593Smuzhiyun pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun udelay(2000);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun mpc83xx_pci_init(1, reg);
99*4882a593Smuzhiyun }
100