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/OK3568_Linux_fs/kernel/drivers/clk/ingenic/
H A Djz4780-cgu.c294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
344 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
350 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
356 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
[all …]
H A Djz4770-cgu.c104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
153 .parents = { JZ4770_CLK_PLL0, },
161 .parents = { JZ4770_CLK_PLL0, },
169 .parents = { JZ4770_CLK_PLL0, },
178 .parents = { JZ4770_CLK_PLL0, },
186 .parents = { JZ4770_CLK_PLL0, },
195 .parents = { JZ4770_CLK_PLL0, },
206 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
213 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
[all …]
H A Dx1830-cgu.c114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
228 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
235 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
241 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
[all …]
H A Djz4725b-cgu.c56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
90 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
99 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
108 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
117 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
126 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
143 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
150 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
[all …]
H A Dx1000-cgu.c186 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
209 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
234 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
242 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
248 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
254 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
261 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
267 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
274 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
280 .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
[all …]
H A Djz4740-cgu.c71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
105 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
114 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
123 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
132 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
141 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
157 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
165 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
[all …]
/OK3568_Linux_fs/yocto/poky/meta/recipes-kernel/linux/
H A Dkernel-devsrc.bb63 cp --parents $(find -type f -name "Makefile*" -o -name "Kconfig*") $kerneldir/build
64 cp --parents $(find -type f -name "Build" -o -name "Build.include") $kerneldir/build
95 cp -a --parents scripts/module.lds $kerneldir/build/ 2>/dev/null || :
110 cp -a --parents arch/powerpc/lib/crtsavres.[So] $kerneldir/build/
116 cp -a --parents arch/${ARCH}/kernel/vdso/vdso.lds $kerneldir/build/
120 cp -a --parents arch/powerpc/kernel/vdso32/vdso32.lds $kerneldir/build 2>/dev/null || :
121 cp -a --parents arch/powerpc/kernel/vdso64/vdso64.lds $kerneldir/build 2>/dev/null || :
129 cp -a --parents include/generated/autoconf.h $kerneldir/build 2>/dev/null || :
151 cp -a --parents tools/build/Build.include $kerneldir/build/
152 cp -a --parents tools/build/Build $kerneldir/build/
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/st/
H A Dclkgen-mux.c21 const char **parents; in clkgen_mux_get_parents() local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
29 if (!parents) in clkgen_mux_get_parents()
32 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
33 return parents; in clkgen_mux_get_parents()
57 const char **parents; in st_of_clkgen_mux_setup() local
66 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgen_mux_setup()
67 if (IS_ERR(parents)) { in st_of_clkgen_mux_setup()
69 __func__, PTR_ERR(parents)); in st_of_clkgen_mux_setup()
73 clk = clk_register_mux(NULL, np->name, parents, num_parents, in st_of_clkgen_mux_setup()
[all …]
H A Dclk-flexgen.c273 const char **parents; in flexgen_get_parents() local
280 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in flexgen_get_parents()
281 if (!parents) in flexgen_get_parents()
284 *num_parents = of_clk_parent_fill(np, parents, nparents); in flexgen_get_parents()
286 return parents; in flexgen_get_parents()
315 const char **parents; in st_of_flexgen_setup() local
333 parents = flexgen_get_parents(np, &num_parents); in st_of_flexgen_setup()
334 if (!parents) { in st_of_flexgen_setup()
387 clk = clk_register_flexgen(clk_name, parents, num_parents, in st_of_flexgen_setup()
396 kfree(parents); in st_of_flexgen_setup()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/zynqmp/
H A Dclkc.c98 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; member
122 const char * const *parents,
286 const char * const *parents, in zynqmp_clk_register_fixed_factor() argument
307 parents[0], in zynqmp_clk_register_fixed_factor()
448 static int __zynqmp_clock_get_parents(struct clock_parent *parents, in __zynqmp_clock_get_parents() argument
455 for (i = 0; i < ARRAY_SIZE(response->parents); i++) { in __zynqmp_clock_get_parents()
456 if (response->parents[i] == NA_PARENT) in __zynqmp_clock_get_parents()
459 parent = &parents[i]; in __zynqmp_clock_get_parents()
460 parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]); in __zynqmp_clock_get_parents()
461 if (response->parents[i] == DUMMY_PARENT) { in __zynqmp_clock_get_parents()
[all …]
H A Dclk-zynqmp.h37 const char * const *parents,
42 const char * const *parents,
48 const char * const *parents,
53 const char * const *parents,
59 const char * const *parents,
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sun8i-mbus.c27 const char **parents; in sun8i_a23_mbus_setup() local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL); in sun8i_a23_mbus_setup()
38 if (!parents) in sun8i_a23_mbus_setup()
60 of_clk_parent_fill(node, parents, num_parents); in sun8i_a23_mbus_setup()
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents, in sun8i_a23_mbus_setup()
89 kfree(parents); /* parents is deep copied */ in sun8i_a23_mbus_setup()
107 kfree(parents); in sun8i_a23_mbus_setup()
H A Dclk-sun4i-display.c19 u8 parents; member
104 const char *parents[4]; in sun4i_a10_display_init() local
123 ret = of_clk_parent_fill(node, parents, data->parents); in sun4i_a10_display_init()
124 if (ret != data->parents) { in sun4i_a10_display_init()
158 parents, data->parents, in sun4i_a10_display_init()
224 .parents = 4,
242 .parents = 3,
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-vop-clk-set.dtsi17 assigned-clock-parents = <&cru PLL_GPLL>;
23 assigned-clock-parents = <&cru PLL_GPLL>;
28 assigned-clock-parents = <&cru PLL_GPLL>;
33 assigned-clock-parents = <&cru PLL_GPLL>;
38 assigned-clock-parents = <&cru PLL_GPLL>;
43 assigned-clock-parents = <&pmucru PLL_PPLL>;
48 assigned-clock-parents = <&cru PLL_GPLL>;
53 assigned-clock-parents = <&cru PLL_GPLL>;
58 assigned-clock-parents = <&cru PLL_GPLL>;
63 assigned-clock-parents = <&cru PLL_GPLL>;
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-bpmp.c23 unsigned int parents[MRQ_CLK_MAX_PARENTS]; member
35 unsigned int *parents; member
203 request.parent_id = clk->parents[index]; in tegra_bpmp_clk_set_parent()
244 if (clk->parents[i] == response.parent_id) in tegra_bpmp_clk_get_parent()
351 info->parents[i] = response.parents[i]; in tegra_bpmp_clk_get_info()
395 dev_printk(level, bpmp->dev, " %03u\n", info->parents[i]); in tegra_bpmp_clk_info_dump()
472 const char **parents; in tegra_bpmp_clk_register() local
483 clk->parents = devm_kcalloc(bpmp->dev, info->num_parents, in tegra_bpmp_clk_register()
484 sizeof(*clk->parents), GFP_KERNEL); in tegra_bpmp_clk_register()
485 if (!clk->parents) in tegra_bpmp_clk_register()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk.h120 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
121 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
242 u8 shift, u8 width, const char * const *parents,
265 u8 shift, u8 width, const char * const *parents, in imx_clk_hw_mux_ldb() argument
268 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux_ldb()
440 u8 shift, u8 width, const char * const *parents, in imx_clk_hw_mux() argument
443 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux()
450 u8 width, const char * const *parents, int num_parents) in imx_dev_clk_hw_mux() argument
452 return clk_hw_register_mux(dev, name, parents, num_parents, in imx_dev_clk_hw_mux()
458 u8 shift, u8 width, const char * const *parents, in imx_clk_mux2() argument
[all …]
H A Dclk-scu.h14 struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
23 static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents, in imx_clk_scu2() argument
26 return __imx_clk_scu(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos-clkout.c57 struct clk *parents[EXYNOS_CLKOUT_PARENTS]; in exynos_clkout_init() local
74 parents[i] = of_clk_get_by_name(node, name); in exynos_clkout_init()
75 if (IS_ERR(parents[i])) { in exynos_clkout_init()
80 parent_names[i] = __clk_get_name(parents[i]); in exynos_clkout_init()
124 if (!IS_ERR(parents[i])) in exynos_clkout_init()
125 clk_put(parents[i]); in exynos_clkout_init()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy_clk.c148 const char *parents[2]; in sun8i_phy_clk_create() local
150 parents[0] = __clk_get_name(phy->clk_pll0); in sun8i_phy_clk_create()
151 if (!parents[0]) in sun8i_phy_clk_create()
155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
156 if (!parents[1]) in sun8i_phy_clk_create()
166 init.parent_names = parents; in sun8i_phy_clk_create()
H A Dsun4i_hdmi_tmds_clk.c207 const char *parents[2]; in sun4i_tmds_create() local
209 parents[0] = __clk_get_name(hdmi->pll0_clk); in sun4i_tmds_create()
210 if (!parents[0]) in sun4i_tmds_create()
213 parents[1] = __clk_get_name(hdmi->pll1_clk); in sun4i_tmds_create()
214 if (!parents[1]) in sun4i_tmds_create()
223 init.parent_names = parents; in sun4i_tmds_create()
/OK3568_Linux_fs/kernel/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c539 const char *parents[CLK_SRC_MAX]; in lpc18xx_cgu_register_div() local
545 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); in lpc18xx_cgu_register_div()
547 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_cgu_register_div()
559 const char *parents[CLK_SRC_MAX]; in lpc18xx_register_base_clk() local
567 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); in lpc18xx_register_base_clk()
571 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_register_base_clk()
575 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_register_base_clk()
586 const char *parents[CLK_SRC_MAX]; in lpc18xx_cgu_register_pll() local
592 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); in lpc18xx_cgu_register_pll()
594 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_cgu_register_pll()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/x86/
H A Dclk-pmc-atom.c47 struct clk_plt_fixed **parents; member
248 plt_clk_unregister_fixed_rate(data->parents[i]); in plt_clk_unregister_fixed_rate_loop()
279 data->parents = devm_kcalloc(&pdev->dev, nparents, in plt_clk_register_parents()
280 sizeof(*data->parents), GFP_KERNEL); in plt_clk_register_parents()
281 if (!data->parents) in plt_clk_register_parents()
290 data->parents[i] = in plt_clk_register_parents()
294 if (IS_ERR(data->parents[i])) { in plt_clk_register_parents()
295 err = PTR_ERR(data->parents[i]); in plt_clk_register_parents()
/OK3568_Linux_fs/kernel/drivers/clk/keystone/
H A Dpll.c302 const char *parents[2]; in of_pll_mux_clk_init() local
312 of_clk_parent_fill(node, parents, 2); in of_pll_mux_clk_init()
313 if (!parents[0] || !parents[1]) { in of_pll_mux_clk_init()
328 clk = clk_register_mux(NULL, clk_name, (const char **)&parents, in of_pll_mux_clk_init()
329 ARRAY_SIZE(parents) , 0, reg, shift, mask, in of_pll_mux_clk_init()
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx7ulp.dtsi212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
234 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
246 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
258 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
270 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
282 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
353 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
368 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
382 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-ep93xx.c378 girq->parents = devm_kcalloc(dev, 1, in ep93xx_gpio_add_bank()
379 sizeof(*girq->parents), in ep93xx_gpio_add_bank()
381 if (!girq->parents) in ep93xx_gpio_add_bank()
385 girq->parents[0] = ab_parent_irq; in ep93xx_gpio_add_bank()
400 girq->parents = devm_kcalloc(dev, 8, in ep93xx_gpio_add_bank()
401 sizeof(*girq->parents), in ep93xx_gpio_add_bank()
403 if (!girq->parents) in ep93xx_gpio_add_bank()
407 girq->parents[i - 1] = platform_get_irq(pdev, i); in ep93xx_gpio_add_bank()

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